EL5108, EL5308 ® Data Sheet August 10, 2010 450MHz Fixed Gain Amplifiers with Enable Features The EL5108 and EL5308 are fixed gain amplifiers with a bandwidth of 450MHz. This makes these amplifiers ideal for today’s high speed video and monitor applications. They feature internal gain-setting resistors and can be configured in a gain of +1, -1 or +2. The same bandwidth is seen in both gain-of-1 and gain-of-2 applications. • Pb-free available (RoHS compliant) The EL5108 and EL5308 also incorporate an enable and disable function to reduce the supply current to 25µA typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. The EL5108 is offered in the 6 Ld SOT-23 and the industrystandard 8 Ld SOIC packages and the EL5308 is available in the 16 Ld SOIC and 16 Ld QSOP packages. All operate over the industrial temperature range of -40°C to +85°C. FN7358.7 • Gain selectable (+1, -1, +2) • 450MHz -3dB BW (AV = -1, +1, +2) • 3.5mA supply current per amplifier • Single and dual supply operation, from 5V to 12V • Available in SOT-23 packages • 350MHz, 1.5mA product available (EL5106 and EL5306) Applications • Battery powered equipment • Handheld, portable devices • Video amplifiers • Cable drivers • RGB amplifiers Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL5108IW-T7* r 6 Ld SOT-23 MDP0038 EL5108IW-T7A* r 6 Ld SOT-23 MDP0038 EL5108IWZ-T7* (Note) BAGA 6 Ld SOT-23 (Pb-free) MDP0038 EL5108IWZ-T7A* (Note) BAGA 6 Ld SOT-23 (Pb-free) MDP0038 EL5108IS 5108IS 8 Ld SOIC (150 mil) MDP0027 EL5108IS-T7* 5108IS 8 Ld SOIC (150 mil) MDP0027 EL5108IS-T13* 5108IS 8 Ld SOIC (150 mil) MDP0027 EL5108ISZ (Note) 5108ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5108ISZ-T7* (Note) 5108ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5108ISZ-T13* (Note) 5108ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5308IS EL5308IS 16 Ld SOIC (150 mil) MDP0027 EL5308IS-T7* EL5308IS 16 Ld SOIC (150 mil) MDP0027 EL5308IS-T13* EL5308IS 16 Ld SOIC (150 mil) MDP0027 EL5308IU 5308IU 16 Ld QSOP (150 mil) MDP0040 EL5308IU-T7* 5308IU 16 Ld QSOP (150 mil) MDP0040 EL5308IU-T13* 5308IU 16 Ld QSOP (150 mil) MDP0040 EL5308IUZ (Note) 5308IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5308IUZ-T7* (Note) 5308IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5308IUZ-T13* (Note) 5308IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2004, 2006, 2007, 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5108, EL5308 Pinouts EL5308 (16 LD SOIC, QSOP) TOP VIEW EL5108 (8 LD SOIC) TOP VIEW NC 1 IN- 2 + IN+ 3 8 CE INA+ 1 7 VS+ CEA 2 6 OUT VS- 3 5 NC VS- 4 CEB 4 16 INA+ 14 VS+ + - INB+ 5 EL5108 (6 LD SOT-23) TOP VIEW 6 VS+ OUT 1 VS- 2 INC+ 8 13 OUTB 12 INB- NC 6 CEC 7 15 OUTA 11 NC + - 10 OUTC 9 INC- 5 CE + - IN+ 3 4 IN- 2 FN7358.7 August 10, 2010 EL5108, EL5308 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Maximum Slewrate from VS+ to VS- . . . . . . . . . . . . . . . . . . . . 1V/µs Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = +1 440 MHz AV = -1 445 MHz AV = +2 450 MHz 40 MHz 4500 V/µs 10 ns 2 nV/√Hz BW1 0.1dB Bandwidth AV = +2 SR Slew Rate VO = -2.5V to +2.5V, AV = +2 tS 0.1% Settling Time VOUT = -2.5V to +2.5V, AV = +2 eN Input Voltage Noise iN Input Current Noise f = 2kHz 12 pA/√Hz dG Differential Gain Error (Note 1) AV = +2 0.01 % dP Differential Phase Error (Note 1) AV = +2 0.01 ° 3500 DC PERFORMANCE VOS Offset Voltage TCVOS Input Offset Voltage Temperature Coefficient Measured from TMIN to TMAX AE Gain Error VO = -3V to +3V, RL = 150Ω RF, RG Internal RF and RG -8 +3 +8 mV 5 0.7 µV/°C 2.5 % 325 Ω ±3.3 V INPUT CHARACTERISTICS CMIR Common Mode Input Range +IIN + Input Current RIN Input Resistance CIN Input Capacitance ±3 2 at IN+ 8 µA 0.7 MΩ 1 pF OUTPUT CHARACTERISTICS VO RL = 150Ω to GND ±3.6 ±3.8 V RL = 1kΩ to GND ±3.8 ±4.0 V Output Current RL = 10Ω to GND 100 135 mA ISON Supply Current - Enabled (per amplifier) No load, VIN = 0V 3.18 3.7 4.35 mA ISOFF Supply Current - Disabled (per amplifier) No load, VIN = 0V 9 25 µA PSRR Power Supply Rejection Ratio 75 IOUT Output Voltage Swing SUPPLY 3 DC, VS = ±4.75V to ±5.25V dB FN7358.7 August 10, 2010 EL5108, EL5308 Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C Unless Otherwise Specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT ENABLE tEN Enable Time 280 ns tDIS Disable Time (Note 2) 560 ns IIHCE CE Pin Input High Current CE = VS+ -1 IILCE CE Pin Input Low Current CE = VS- +1 VIHCE CE Input High Voltage for Power-down VILCE CE Input Low Voltage for Enable 5 25 µA -1 µA VS+ -1 V VS+ -3 V NOTES: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz 2. Measured from the application of the CE logic signal until the output voltage is at the 50% point between initial and final values Pin Descriptions EL5108 (SO8) EL5108 (SOT23-6) 1, 5 2 4 EL5308 (SO16, QSOP16) PIN NAME 6, 11 NC Not connected 9, 12, 16 IN- Inverting input FUNCTION EQUIVALENT CIRCUIT RG IN+ IN- RF CIRCUIT 1 3 3 1, 5, 8 IN+ Non-inverting input 4 2 3 VS- Negative supply 6 1 10, 13, 15 OUT Output (Reference Circuit 1) OUT RF CIRCUIT 2 7 6 14 VS+ Positive supply 8 5 2, 4, 7 CE Chip enable VS+ CE VSCIRCUIT 3 4 FN7358.7 August 10, 2010 EL5108, EL5308 Typical Performance Curves 3 135 VS = ±5V VIN = 200mVP-P RL = 150Ω 45 AV = -1 1 PHASE (°) NORMALIZED GAIN (dB) 5 AV = 2 -1 VS = ±5V VIN = 200VP-P RL = 150Ω AV = -1 -45 -135 AV = 1 AV = 2 -225 -3 AV = 1 -5 100k 1M 10M 100M -315 100k 1G 1M 9 1G 100M FIGURE 2. PHASE RESPONSE FIGURE 1. FREQUENCY RESPONSE 11 10M FREQUENCY (Hz) FREQUENCY (Hz) 11 VS = ±5V AV = 2 RL = 150Ω 9 VS = ±5V AV = 2 RL = 500Ω 7 5 GAIN (dB) GAIN (dB) RL = 150Ω VOP-P = 400mV VOP-P = 2V 3 7 5 RL = 100Ω 3 1 100k 1M 10M 100M RL = 50Ω 1 100k 1G 1M FREQUENCY (Hz) 1.2 CL = 6.8pF 1 CL = 4.7pF DELAY (ns) GAIN (dB) 9 VS = ±5V AV = 2 RL = 150Ω 7 CL = 2.2pF 5 CL = 0pF 3 1 100k 1G 100M FIGURE 4. FREQUENCY RESPONSE vs RL FIGURE 3. FREQUENCY RESPONSE vs OUTPUT VOLTAGE 11 10M FREQUENCY (Hz) VS = ±5V RL = 150Ω AV = -1 AV = 1 0.8 AV = 2 0.6 0.4 0.2 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS CL 5 0 100k 1M 10M 1G 100M FREQUENCY (Hz) FIGURE 6. GROUP DELAY vs FREQUENCY FN7358.7 August 10, 2010 EL5108, EL5308 Typical Performance Curves GAIN (dB) -5 100 AV = 2 RL = 150Ω 10 IMPEDENCE (Ω) 15 (Continued) -25 -45 -65 -85 100k 1 0.1 0.01 1M 10M 100M 1G 0.002 10k 100k FREQUENCY (Hz) FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY (FOR DISABLE MODE) 0 -10 VS = ±5V AV = 2 -20 100 PSRR (dB) VN (nV/√Hz), IN (pA/√Hz) 100M 10M FIGURE 8. OUTPUT IMPEDENCE vs FREQUENCY 1K IN 10 -30 -40 -50 -60 VN 1 100 1k 10k -70 100k 1M -80 1k 10M 10k FIGURE 9. VOLTAGE AND CURRENT NOISE vs FREQUENCY 480 460 AV = 2 420 AV = -1 380 360 10M 100M AV = 1 340 RL = 150Ω 1.2 PEAKING (dB) 440 400 1M FIGURE 10. POWER SUPPLY REJECTION RATIO vs FREQUENCY 1.4 RL = 150Ω 100k FREQUENCY (Hz) FREQUENCY (Hz) BANDWIDTH (MHz) 1M FREQUENCY (Hz) 1 AV = -1 0.8 AV = 2 0.6 AV = 1 0.4 320 300 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 VS (V) FIGURE 11. BANDWIDTH vs SUPPLY VOLTAGE 6 0.2 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 VS (V) FIGURE 12. PEAKING vs SUPPLY VOLTAGE FN7358.7 August 10, 2010 EL5108, EL5308 Typical Performance Curves 3.9 VS = ±5V AV = 2 RL = 150Ω VO = 2VP-P -50 HD2 3.7 3.5 HD3 -60 IS (mA) DISTORTION (dB) -40 (Continued) -70 IS+, IS- 3.3 3.1 2.9 -80 -90 2.7 0 10 20 30 40 50 60 2.5 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 FREQUENCY (MHz) VS (V) FIGURE 13. DISTORTION vs FREQUENCY FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE VO = VO = ±2V 100mV/DIV 1V/DIV 10ns/DIV 10ns/DIV FIGURE 15. LARGE SIGNAL RESPONSE FIGURE 16. SMALL SIGNAL RESPONSE M=100ns M=100ns CH1 2.00V/DIV CH1 2.00V/DIV CH2 1.00V/DIV FIGURE 17. DISABLED RESPONSE 7 CH2 1.00V/DIV FIGURE 18. ENABLED RESPONSE FN7358.7 August 10, 2010 EL5108, EL5308 Typical Performance Curves JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.4 909mW 0.9 SO16 (0.150”) θJA=110°C/W 0.8 POWER DISSIPATION (W) 1 (Continued) 0.7 625mW 0.6 633mW SO8 θJA=160°C/W 0.5 0.4 391mW 0.3 SOT23-6 θJA=256°C/W 0.2 QSOP16 θJA=158°C/W 0.1 0 0 25 50 75 85 100 125 150 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.250W 1.2 1 909mW 0.8 893mW Applications Information Product Description The EL5108 and EL5308 are fixed gain amplifiers that offer a wide -3dB bandwidth of 450MHz and a low supply current of 3.5mA per amplifier. They work with supply voltages ranging from a single 5V to 10V and they are also capable of swinging to within 1.2V of either supply on the output. These combinations of high bandwidth, low power, and high slew rate make the EL5108 and EL5308 the ideal choice for many low-power/high-bandwidth applications such as portable, handheld, or battery-powered equipment. For varying bandwidth and higher gains, consider the EL5166 with 1GHz on a 9mA supply current or the EL5164 with 600MHz on a 3.5mA supply current. Versions include single, dual, and triple amp packages with 6 Ld SOT-23, 16 Ld QSOP, and 8 Ld SOIC or 16 Ld SOIC outlines. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a 4.7µF tantalum capacitor in parallel with a 0.01µF capacitor has been shown to work well when placed at each supply pin. 435mW 0.4 0.2 0.1 0 SOT23-6 θJA=230°C/W 0 25 8 50 QSOP16 θJA=112°C/W 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE amplifier is enabled by floating or pulling its CE pin to at least 3V below the positive supply. For ±5V supply, this means that the amplifier will be enabled when CE is 2V or less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allow the EL5108 and EL5308 to be enabled by tying CE to ground, even in 5V single supply applications. The CE pins can be driven from CMOS outputs. Gain Setting The EL5108 and EL5308 are built with internal feedback and gain resistors. The internal feedback resistors have equal value; as a result, the amplifier can be configured into gain of +1, -1, and +2 without any external resistors. Figure 21 shows the amplifier in gain of +2 configuration. The gain error is ±2% maximum. Figure 22 shows the amplifier in gain-of-1 configuration. For gain of +1, IN+ and IN- should be connected together as shown in Figure 23. This configuration avoids the effects of any parasitic capacitance on the IN- pin. Since the internal feedback and gain resistors change with temperature and process, external resistor should not be used to adjust the gain settings. 325Ω IN- 325Ω IN+ + FIGURE 21. AV = +2 325Ω Disable/Power-Down The EL5108 and EL5308 amplifiers can be disabled and placing their outputs in a high impedance state. When disabled, the amplifier supply current is reduced to <25µA. The EL5108 and EL5308 are disabled when the CE pin is pulled up to within 1V of the positive supply. Similarly, the SO8 θJA=110°C/W 0.6 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE SO16 (0.150”) θJA=80°C/W IN- 325Ω GND + FIGURE 22. AV = -1 FN7358.7 August 10, 2010 EL5108, EL5308 Output Drive Capability 325Ω IN- 325Ω In spite of its low 3.5mA of supply current per amplifier, the EL5108 and EL5308 are capable of providing a maximum of ±130mA of output current. + IN+ Driving Cables and Capacitive Loads FIGURE 23. AV = +1 Supply Voltage Range and Single-Supply Operation The EL5108 and EL5308 have been designed to operate with supply voltages having a span of greater than or equal to 5V and less than 12V. In practical terms, this means that they will operate on dual supplies ranging from ±2.5V to ±5V. With single-supply, they will operate from 5V to 10V. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5108 and EL5308 have an input range which extends to within 2V of either supply. So, for example, on ±5V supplies, the input range is about ±3V. The output range is also quite large, extending to within 1V of the supply rail. On a ±5V supply, the output is therefore capable of swinging from -4V to +4V. Single-supply output range is larger because of the increased negative swing due to the external pull-down resistor to ground. Figure 24 shows an AC-coupled, gain of +2, +5V single supply circuit configuration. 325Ω +5 4.7µF 325Ω + +5 0.1µF VOUT 1k Current Limiting The EL5108 and EL5308 have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation With the high output drive capability of the EL5108 and EL5308, it is possible to exceed the +125°C Absolute Maximum junction temperature under certain very high load current conditions. Generally speaking when RL falls below about 25Ω, it is important to calculate the maximum junction temperature (TJMAX) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the EL5108 and EL5308 to remain in the safe operating area. These parameters are calculated as follows: T JMAX = T MAX + ( θ JA × n × PD MAX ) where: 0.1µF VIN When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, the back-termination series resistor will decouple the EL5108 and EL5308 from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. In these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output to eliminate most peaking. 1k TMAX = Maximum ambient temperature θJA = Thermal resistance of the package FIGURE 24. Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω, because of the change in output current with DC level. Previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variations in output impedance). Special circuitry has been incorporated in the EL5108 and EL5308 to reduce the variation of output impedance with current output. This results in dG and dP specifications of 0.01% and 0.01°, while driving 150Ω at a gain of 2. 9 n = Number of amplifiers in the package PDMAX = Maximum power dissipation of each amplifier in the package PDMAX for each amplifier can be calculated as follows: V OUTMAX PD MAX = ( 2 × V S × I SMAX ) + ( V S - V OUTMAX ) × ---------------------------R L where: VS = Supply voltage ISMAX = Maximum supply current of 1A VOUTMAX = Maximum output voltage (required) RL = Load resistance FN7358.7 August 10, 2010 EL5108, EL5308 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 10 FN7358.7 August 10, 2010 EL5108, EL5308 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 SEATING PLANE 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 11 0.25 0° +3° -0° FN7358.7 August 10, 2010 EL5108, EL5308 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7358.7 August 10, 2010