DATASHEET

CD4063BMS
CMOS 4-Bit Magnitude Comparator
December 1992
Features
Pinout
• High Voltage Type (20V Rating)
CD4063BMS
TOP VIEW
• Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units
• Medium Speed Operation
- Compares Two 4-Bit Words in 250ns (Typ.) at 10V
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
B3
1
16 VDD
(A < B) IN
2
15 A3
(A = B) IN
3
14 B2
(A > B) IN
4
13 A2
(A > B) OUT
5
12 A1
(A = B) OUT
6
11 B1
(A < B) OUT
7
10 A0
VSS
8
9 B0
Functional Diagram
4
Applications
WORD A
• Servo Motor Controls
• Process Controllers
CASCADING
INPUTS
Description
CD4063BMS is a 4-bit magnitude comparator designed for use
in computer and logic applications that require the comparison of
two 4-bit words. This logic circuit determines whether one 4-bit
word (Binary or BCD) is “less than”, “equal to”, or “greater than” a
second 4-bit word.
A>B
A>B
A=B
A=B
A<B
A<B
4
WORD B
The CD4063BMS has eight comparing inputs (A3, B3, through
A0, B0), three outputs (A < B, A = B, A > B) and three cascading
inputs (A < B, A = B, A > B) that permit systems designers to
expand the comparator function to 8, 12, 16 . . . 4N bits. When a
single CD4063BMS is used, the cascading inputs are connected
as follows: (A < B) = low, (A = B) = high, (A > B) = low.
For words longer than 4 bits, CD4063BMS devices may be cascaded by connecting the outputs of the less significant comparator to the corresponding cascading inputs of the more significant
comparator. Cascading inputs (A < B, A = B, and A > B) on the
least significant comparator are connected to a low, a high, and a
low level, respectively.
The CD4063BMS is supplied in these 16 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-958
File Number
3318
Specifications CD4063BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP Package . . . . . . . . . . . . . 80oC/W
20C/W
Flatpack Package . . . . . . . . . . . . . . . . 20oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
+25
-
10
µA
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25o
C
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
-
100
nA
-
50
mV
-
V
3
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
UNITS
1
-55oC
VDD = 18V
MAX
2
oC
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
1
+25oC
-
-1.8
mA
Output Current (Source)
Output Current (Source)
IOH5A
IOH5B
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
1
+25oC
0.7
2.8
V
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES:
1. All voltages referenced to device GND. 100% testing being implemented
2. Go/No Go test with limit applied to inputs
7-959
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4063BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay Comparator Input to Output
Propagation Delay
Cascade Input to Output
Transition Time
SYMBOL
TPHL
TPLH
(NOTE 1, 2)
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
TTHL
VDD = 5V, VIN = VDD or GND
9
+25oC
+125oC,
-55oC
+25oC
o
o
LIMITS
MIN
MAX
UNITS
-
1250
ns
-
1688
ns
-
1000
ns
10, 11
+125 C, -55 C
-
1350
ns
9
+25oC
-
200
ns
-
270
ns
10, 11
+125oC,
-55oC
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
1, 2
-55oC,
+25oC
+125oC
VDD = 15V, VIN = VDD or GND
1, 2
MIN
MAX
UNITS
-
5
µA
-
150
µA
-
10
µA
-
300
µA
-
10
µA
+125oC
-
600
µA
-55oC,
+25oC
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VIL
VDD = 10V, VOUT = 0.5V
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
1, 2
VDD =15V, VOUT = 13.5V
VDD = 10V, VOH > 9V, VOL <
1V
7-960
1, 2
1, 2
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-2.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
+25oC, +125oC,
-
3
V
-55oC
Specifications CD4063BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Input Voltage High
VIH
Propagation Delay
Comparator Input to Output
Propagation Delay
Cascade Input to Output
Transition Time
Input Capacitance
CONDITIONS
VDD = 10V, VOH > 9V, VOL <
1V
TPHL1
TPLH1
VDD = 10V
VDD = 15V
TPHL2
TPLH2
VDD = 10V
TTHL
TTLH
VDD = 15V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+25oC, +125oC,
+7
-
V
-55oC
1, 2, 3
+25oC
-
500
ns
1, 2, 3
+25oC
-
350
ns
o
1, 2, 3
+25 C
-
400
ns
VDD = 15V
1, 2, 3
+25oC
-
280
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2
+25oC
-
7.5
pF
CIN
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K; input TR, TF < 20ns
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 20V, VIN = VDD or GND
TEMPERATURE
1, 4
+25
oC
o
MAX
UNITS
-
25
µA
-2.8
-0.2
V
-
±1
V
1, 4
+25 C
VDD = 10V, ISS= -10µA
1, 4
+25
oC
VPTH
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
∆VPTH
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VNTH
P Threshold Voltage
P Threshold Voltage
Delta
Functional
F
VDD = 10V, ISS = -10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
MIN
TPHL
TPLH
VDD = 5V (Worst Case)
NOTES:
1. All voltages referenced to device GND.
2. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF = 20ns
3. See Table 2 for +25oC limit.
4. Read and record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
7-961
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD4063BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
READ AND RECORD
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 5% parametric, 3% functional; cumulative for static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE GROUPS
READ AND RECORD
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9, Deltas
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
5-7
1, 2, 4, 8-15
3, 16
Static Burn-In 2
Note 1
5-7
3, 8
1, 2, 4, 9-16
Dynamic BurnIn Note 1
-
1, 2, 4, 8, 10, 11,
13
3, 16
5-7
3, 8
1, 2, 4, 9-16
Irradiation
Note 2
9V ± -0.5V
50kHz
25kHz
5-7
12, 15
9, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
A0 A1 A2 A3
VDD
CD4063
(A < B) OUT
A4 A5 A6 A7
A8 A9 A10 A11
CD4063
CD4063
B4 B5 B6 B7
B8 B9 B10 B11
(A < B) IN
(A = B) OUT
(A = B) IN
(A > B) IN
B0 B1 B2 B3
(A > B) OUT
tP TOTAL = tP (COMPARE INPUTS) + 2 x tP (CASCADE INPUTS), AT VDD = 10V
(3 STAGES)
= 250 + (2 x 200) = 650ns (TYP.)
FIGURE 1. TYPICAL SPEED CHARACTERISTICS OF A 12-BIT COMPARATOR
7-962
CD4063BMS
Logic Diagram
A3
B3
A0 10
A1 12
A2 13
A3 15
COMPARING
INPUTS
B0 9
B1 11
B2 14
B3 1
(A < B) IN 2
CASCADING
INPUTS
(A > B) IN 4
(A = B) IN 3
A0
*
A0
A2
B2
A1
*
A1
A2
B2
A2
*
A2
A1
B1
A3
*
A3
A1
B1
B0
*
A0
B0
B0
B1
*
A0
B0
B1
7
(A < B) OUT
6
(A = B) OUT
5
(A > B) OUT
B2
*
(A < B) i - I
B2
B3
*
B3
B3
A3
*
(A < B) i - I
*
A>B
B3
A3
(A > B) i - I
B2
A2
*
B2
A2
B1
A1
VDD
*
A<B
A3
B3
B1
A1
ALL INPUTS PROTECTED
BY THE CMOS
PROTECTION NETWORK
B0
A0
INPUT
TERMINAL
B0
A0
VSS
(A > B) i - I
FIGURE 2. LOGIC DIAGRAM
TRUTH TABLE
INPUTS
COMPARING
CASCADING
OUTPUTS
A3, B3
A2, B2
A1, B1
A0, B0
A <B
A=B
A>B
A<B
A=B
A>B
A3 > B3
A3 = B3
A3 = B3
A3 = B3
X
A2 > B2
A2 = B2
A2 = B2
X
X
A1 > B1
A1 = B1
X
X
X
A0 > B0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
A3 = B3
A3 = B3
A3 = B3
A3 < B3
A2 = B2
A2 = B2
A2 < B2
X
A1 = B1
A1 < B1
X
X
A0 < B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
0
0
0
0
0
X = Don’t Care
Logic 1 = High Level
Logic 0 = Low Level
7-963
CD4063BMS
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
0
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
-30
-5
-10V
PROPAGATION DELAY TIME (tTHL, tTLH) (ns)
PROPAGATION DELAY TIME (tTHL, tTLH) (ns)
500
AMBIENT TEMPERATURE (TA) = +25oC
400
10V
15V
100
0
10
20
30
40
50
60
70
80
LOAD CAPACITANCE (CL) (pF)
-15
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
600
200
-10
-15V
SUPPLY VOLTAGE (VDD) = 5V
300
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
700
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN
CHARACTERISTICS
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
90
1750
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
1500
1250
1000
750
500
250
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
SUPPLY VOLTAGE (VDD) (V)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (“COMPARING INPUTS” TO OUTPUTS)
7-964
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs SUPPLY
VOLTAGE (“COMPARING INPUTS” TO OUTPUTS)
CD4063BMS
(Continued)
POWER DISSIPATION PER GATE (PD) (µW)
Typical Performance Characteristics
TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
50
104
6
4
AMBIENT TEMPERATURE (TA) = +25oC
2
103
6
4
SUPPLY VOLTAGE (VDD) = 15V
LOAD CAPACITANCE (CL) = 50pF
2
10V, 50pF
102
6
4
10V, 15pF
2
10
5V, 50pF
6
4
2
1
0
0
20
2
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
0.1
FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
4 68
2
4 68
2
4 68
2
1
10
102
INPUT FREQUENCY (f) (kHz)
4 68
2
4 68
103
FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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