DATASHEET

CD4585BMS
CMOS 4-Bit Magnitude Comparator
December 1992
Features
Pinout
• High Voltage Type (20V Rating)
CD4585BMS
TOP VIEW
• Expansion to 8, 12, 16 . . .4N Bits by Cascading Units
B2
1
16 VDD
A2
2
15 A3
(A = B)OUT
3
14 B3
(A > B)IN
4
13 (A > B)OUT
(A < B)IN
5
12 (A < B)OUT
(A = B)IN
6
11 B0
A1
7
10 A0
VSS
8
9 B1
• Medium Speed Operation
- Compares Two 4-Bit Words in 180ns (Typ.) at 10V
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Functional Diagram
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
10
A0
Applications
WORD “A”
A1
A2
• Servo Motor Controls
A3
• Process Controllers
CASCADING
INPUTS
Description
A>B
A=B
A<B
CD4585BMS is a 4-bit magnitude comparator designed for
use in computer and logic applications that require the comparison of two 4-bit words. This logic circuit determines
whether one 4-bit word (Binary or BCD) is “less than”, “equal
to” or “greater than” a second 4-bit word.
7
2
15
4
13
6
3
5
12
A>B
A=B
A<B
11
B0
WORD “B”
The CD4585BMS has eight comparing inputs (A3, B3,
through A0, B0), three outputs (A < B, = B, A > B) and three
cascading inputs (A < B, A = B, A > B) that permit system
designers to expand the comparator function to 8, 12, 16 . .
.4N bits. When a single CD4585BMS is used, the cascading
inputs are connected as follows: (A < B) = low, (A = B) =
high, (A > B) = high.
B1
B2
B3
9
1
14
VDD = 16
VSS = 8
Cascading thses units for comparision of more than 4 bits is
accomplished as shown in Figure 9.
The CD4585BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1259
File Number
3347
Specifications CD4585BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
VOL15
VOH15
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1, 2, 3
+25oC,
+125oC,
-55oC
-
50
mV
1, 2, 3
+25oC,
+125oC,
-55oC
14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
Output Current (Sink)
Output Current (Source)
IOL15
IOH5A
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
IOH15
VNTH
VPTH
F
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-1260
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4585BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
Propagation Delay
Comparing
Inputs to Outputs
TPHL1
TPLH1
VDD = 5V, VIN = VDD or GND
Propagation Delay
Cascading Inputs to Outputs
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
Transition Time
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
9
+25oC
+125oC,
-55oC
+25oC
o
o
LIMITS
MIN
MAX
UNITS
-
600
ns
-
810
ns
-
400
ns
10, 11
+125 C, -55 C
-
540
ns
9
+25oC
-
200
ns
-
270
ns
10, 11
+125oC,
-55oC
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55oC, +25oC
-
5
µA
+125oC
-
150
µA
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
-
10
µA
+125oC
-
300
µA
-
10
µA
o
-55oC,
o
+25oC
-
600
µA
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
oC
+125
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
1, 2
1, 2
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
+7
-
V
7-1261
Specifications CD4585BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Propagation Delay
Comparing Inputs to
Outputs
TPHL1
TPLH1
Propagation Delay
Cascading Inputs to Outputs
Transition Time
Input Capacitance
CONDITIONS
VDD = 10V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
-
250
ns
o
VDD = 15V
1, 2, 3
+25 C
-
160
ns
TPHL2
TPLH2
VDD = 10V
1, 2, 3
+25oC
-
160
ns
VDD = 15V
1, 2, 3
+25oC
-
120
ns
TTHL
TTLH
VDD = 10V
1, 2, 3
+25oC
VDD = 15V
CIN
1, 2, 3
Any Inputs
1, 2
-
100
ns
o
+25 C
-
80
ns
oC
-
7.5
pF
+25
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
-
25
µA
1, 4
+25oC
-2.8
-0.2
V
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Supply Current
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
∆VTP
Functional
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
7-1262
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD4585BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
PDA (Note 1)
Final Test
Group A
Group B
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
READ AND RECORD
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group D
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
3, 12, 13
1, 2, 4 - 11, 14, 15
16
Static Burn-In 2
Note 1
3, 12, 13
8
1, 2, 4 - 7, 9 - 11,
14 - 16
Dynamic BurnIn Note 1
-
5 - 9, 11, 14, 15
1, 4, 16
3, 12, 13
8
1, 2, 4 - 7, 9 - 11,
14 - 16
Irradiation
Note 2
9V ± -0.5V
50kHz
25kHz
3, 12, 13
2
10
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
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CD4585BMS
Logic Diagram
*
A3
15
B3
14
VDD
*
VSS
*
A2
2
B2
1
* INPUTS PROTECTED BY
CMOS PROTECTION
NETWORK
*
(A < B)OUT
*
A1
7
B1
9
A0
10
B0
11
(A < B)IN
5
(A = B)IN
6
12
*
*
*
*
*
(A = B)OUT
3
*
(A > B)IN
(A > B)OUT
4
13
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
INPUTS
COMPARING
A3, B3
A2, B2
A1, B1
CASCADING
A0, B0
A<B
OUTPUTS
A=B
A>B
A<B
A=B
A>B
A3 > B3
X
X
X
X
X
1
0
0
1
A3 = B3
A2 > B2
X
X
X
X
1
0
0
1
A3 = B3
A2 = B2
A1 > B1
X
X
X
1
0
0
1
A3 = B3
A2 = B2
A1 = B1
A0 > B0
X
X
1
0
0
1
A3 = B3
A2 = B2
A1 = B1
A0 = B0
0
0
1
0
0
1
A3 = B3
A2 = B2
A1 = B1
A0 = B0
0
1
X
0
1
0
A3 = B3
A2 = B2
A1 = B1
A0 = B0
1
0
X
1
0
0
A3 = B3
A2 = B2
A1 = B1
A0 < B0
X
X
X
1
0
0
A3 = B3
A2 = B2
A1 < B1
X
X
X
X
1
0
0
A3 = B3
A2 < B2
X
X
X
X
X
1
0
0
A3 < B3
X
X
X
X
X
X
1
0
0
X = Don’t Care
Logic 1 = High Level
7-1264
Logic 0 = Low Level
CD4585BMS
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-15V
-30
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0
0
-10
-15V
-15
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
TRANSITION TIME (tTHL, tTLH) (ns)
5V
-10V
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
20
2.5
-5
200
0
0
5.0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
AMBIENT TEMPERATURE (TA) = +25oC
50
10V
7.5
AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
150
10.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-5
-10V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
AMBIENT TEMPERATURE (TA) = +25oC
15.0
0
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
300
SUPPLY VOLTAGE (VDD) = 5V
200
10V
100
15V
0
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 7. TYPICAL PROPAGATION DELAY TIME (“COMPARING INPUTS” TO OUTPUTS) AS A FUNCTION OF
LOAD CAPACITANCE
7-1265
CD4585BMS
DYNAMIC POWER DISSIPATION (PD) (µW)
Typical Performance Characteristics
104 8
6
4
2
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
103 8
SUPPLY VOLTAGE (VDD) = 15V
6
4
2
102 8
10V
6
4
2
10V
10 8
5V
6
4
2
CL = 50pF
CL = 15pF
2
0.1
4 68
2
4 68
2
4 68
2
4 68
2
4 68
1
10
102
103
CLOCK INPUT FREQUENCY (fIN) (kHz)
104
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY
A0
A1
A2
A3
A4
VDD
A5
A6
A7
VDD
A8
A9
A10 A11
VDD
CD4585BMS
CD4585BMS
CD4585BMS
(A > B)OUT
(A > B)IN
(A = B)OUT
(A = B)IN
(A < B)OUT
(A < B)IN
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11
tp TOTAL = tp (COMPARE) + 2 x tp (CASCADE) , AT VDD = 10V
INPUTS
INPUTS
FIGURE 9. TYPICAL SPEED CHARACTERISTICS OF A 12-BIT COMPARATOR
Chip Dimensions and Pad Layout
Dimensions in parenthese are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
BOND PADS:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1266
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