HI-506, HI-507, HI-508, HI-509 Data Sheet Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Application Note AN520). June 14, 2016 FN3142.10 Features • Pb-Free Available (RoHS Compliant) (See Ordering Info) • Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . 180 • Wide Analog Signal Range ±15V • TTL/CMOS Compatible • Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V • Break-Before-Make Switching • No Latch-Up The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic “1” and maximum 0.8V for logic “0”. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200 resistor and diode clamp to each supply. • Replaces DG506A/DG506AA and DG507A/DG507AA The HI-506 is a single 16-channel, the HI-507 is an 8-channel differential, the HI-508 is a single 8-channel and the HI-509 is a 4-channel differential multiplexer. • Selector Switch • Replaces DG508A/DG508AA and DG509A/DG509AA Applications • Data Acquisition Systems • Precision Instrumentation • Demultiplexing If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003, 2005, 2007, 2015, 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HI-506, HI-507, HI-508, HI-509 Ordering Information PART NUMBER PART MARKING HI1-0506-2 HI1-506-2 HI4P0506-5Z (Note 1) HI4P 506-5Z HI9P0506-9Z (Note 1) TEMP. RANGE (°C) -55 to +125 PACKAGE PKG. DWG. # 28 Ld CERDIP F28.6 0 to +75 28 Ld PLCC (Pb-free) N28.45 HI9P506-9Z -40 to +85 28 Ld SOIC (Pb-free) M28.3 HI3-0507-5Z (No longer available, recommended replacement: HI3-0547-5Z) HI3-507-5Z 0 to +75 HI1-0508-2 HI1-508-2 HI3-0508-5Z (Note 1) HI3-508-5Z 0 to +75 16 Ld PDIP (Note 3) (Pb-free) E16.3 HI9P0508-5Z (Notes 1, 2) HI9P508-5Z 0 to +75 16 Ld SOIC (Pb-free) M16.15 HI9P0508-9Z (Note 1) HI9P508-9Z -40 to +85 16 Ld SOIC (Pb-free) M16.15 HI1-0509-2 HI1-509-2 -55 to +125 16 Ld CERDIP F16.3 HI4P0509-5Z (Notes 1, 2) (No longer available, recommended replacement: DG409DYZ) HI4P 509-5Z 20 Ld PLCC (Pb-free) N20.35 -55 to 125 0 to +75 28 Ld PDIP (Note 3) (Pb-free) E28.6 16 Ld CERDIP F16.3 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Submit Document Feedback 2 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Pinouts NC +VSUPPLY OUT -VSUPPLY IN 8 28 OUT 1 NC +VSUPPLY HI-506 (PLCC) TOP VIEW IN 16 HI-506 (CERDIP, SOIC) TOP VIEW 4 3 2 1 28 27 26 NC 2 27 -VSUPPLY NC 3 26 IN 8 IN 16 4 25 IN 7 IN 15 5 25 IN 7 IN 15 5 24 IN 6 IN 14 6 24 IN 6 IN 14 6 23 IN 5 IN 13 7 22 IN 4 IN 13 7 23 IN 5 IN 12 8 21 IN 3 IN 12 8 22 IN 4 9 20 IN 2 IN 11 9 21 IN 3 IN 10 10 19 IN 1 IN 10 10 20 IN 2 IN 9 11 19 IN 1 HI-507 (PDIP, CERDIP) TOP VIEW +VSUPPLY 28 OUT A 1 OUT B 2 27 -VSUPPLY NC 3 26 IN 8A IN 8B 4 25 IN 7A IN 7B 5 24 IN 6A IN 6B 6 23 IN 5A IN 5B 7 22 IN 4A IN 4B 8 21 IN 3A IN 3B 9 20 IN 2A IN 2B 10 19 IN 1A IN 1B 11 18 ENABLE GND 12 17 ADDRESS A0 NC 13 16 ADDRESS A1 NC 14 15 ADDRESS A2 Submit Document Feedback 3 16 17 18 ENABLE 15 ADDRESS A2 15 A0 ADDRESS A3 14 14 A1 16 ADDRESS A1 13 A2 NC 13 12 A3 17 ADDRESS A0 GND 12 NC 18 ENABLE IN 9 11 GND IN 11 HI-508 (PDIP, CERDIP, SOIC) TOP VIEW A0 1 16 A1 ENABLE 2 15 A2 -VSUPPLY 3 14 GND IN 1 4 13 +VSUPPLY IN 2 5 12 IN 5 IN 3 6 11 IN 6 IN 4 7 10 IN 7 OUT 8 9 IN 8 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Pinouts (Continued) 15 GND A0 NC A1 GND 14 +VSUPPLY 3 2 1 20 19 16 A1 IN 3A 6 11 IN 3B IN 4A 7 10 IN 4B 9 OUT B OUT A 8 4 -VSUPPLY 4 18 +VSUPPLY IN 1A 5 17 IN 1B NC 6 16 NC IN 2A 7 15 IN 2B IN 3A 8 14 IN 3B 9 10 11 12 13 IN 4B 12 IN 2B OUT B 13 IN 1B IN 2A 5 NC IN 1A 4 OUT A ENABLE 2 -VSUPPLY 3 IN 4A A0 1 Submit Document Feedback HI-509 (PLCC) TOP VIEW ENABLE HI-509 (PDIP, CERDIP, SOIC) TOP VIEW FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Truth Tables HI-508 HI-506 A3 A2 A1 A0 EN “ON” CHANNEL A2 A1 A0 EN “ON” CHANNEL X X X X L None X X X L None L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 A1 A0 EN “ON” CHANNEL PAIR H L H H H 12 X X L None H H L L H 13 L L H 1 H H L H H 14 L H H 2 H H H L H 15 H L H 3 H H H H H 16 H H H 4 HI-509 HI-507 A2 A1 A0 EN “ON” CHANNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 Submit Document Feedback 5 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Functional Diagrams HI-506 HI-507 IN 1 OUT IN 2 IN 1A OUT A IN 8A DECODER/ DRIVER IN 1B OUT B IN 16 DECODER/ DRIVER 5V REF IN 8B LEVEL SHIFT † DIGITAL INPUT PROTECTION † † † † † A0 A1 A2 A3 EN 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION HI-508 † † † † A0 A1 A2 EN HI-509 IN 1 OUT IN 2 IN 1A OUT A IN 4A DECODER/ DRIVER IN 1B OUT B IN 8 5V REF † DIGITAL INPUT PROTECTION DECODER/ DRIVER IN 4B LEVEL SHIFT † † † † A0 A1 A2 EN 5V REF † DIGITAL Submit Document Feedback 6 INPUT PROTECTION LEVEL SHIFT † † † A0 A1 EN FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Schematic Diagrams ADDRESS DECODER V+ P P P P A0 OR A0 A1 OR A1 P P P N N N N N A2 OR A2 TO P-CHANNEL DEVICE OF THE SWITCH TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-507, HI-508, HI-509 DELETE A2 OR A2 INPUT FOR HI-509 V- ADDRESS INPUT BUFFER LEVEL SHIFTER V+ P3 P1 P5 A V+ D1 P4 N1 VL VR D2 P2 P7 P8 P9 P10 N6 N7 N8 N9 N10 N4 200 A N5 N2 V- P6 N3 AIN ALL N-CHANNEL BODIES TO VALL P-CHANNEL BODIES TO V+ UNLESS OTHERWISE INDICATED V- TTL REFERENCE CIRCUIT MULTIPLEX SWITCH V+ P15 Q1P Q2P Q3P N18 FROM DECODE Q4P Q5N V+ Q6N VL Q8N R2 16.8k N12 Q7P Q11P VVR R3 6.8k Q9P N13 N14 OUT P17 D3 Q10N N17 N19 IN N15 P18 P16 Q12N FROM DECODE V- Submit Document Feedback GND 7 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (VIN, VOUT, Note 5) . . . . . . . . . . (V-) -2V to (V+) +2V Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) . 40mA Thermal Resistance (Typical, Note 4) Operating Conditions Temperature Ranges HI-50X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C HI-50X-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C HI-50X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C HI-50X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Typical Minimum Supply Voltage . . . . . . . . . . . . 10V or Single 20V JA (°C/W) JC (°C/W) 16 Ld CERDIP Package. . . . . . . . . . . . 85 32 16 Ld SOIC Package . . . . . . . . . . . . . . 115 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 100 N/A 20 Ld PLCC Package. . . . . . . . . . . . . . 80 N/A 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A 28 Ld PLCC Package. . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. Signals on IN or OUT exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Intersil HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section -2 TEST CONDITIONS PARAMETER TEMP (°C) MIN (Note 11) TYP -4, -5, -9 MAX MIN (Note 11) TYP MAX UNITS DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) Enable Delay (OFF), tOFF(EN) 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns 25 25 80 - 25 80 - ns 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns To 0.1% 25 - 1.2 - - 1.2 - s To 0.01% 25 - 2.4 - - 2.4 - s Settling Time, tS (HI-508 and HI-509) To 0.1% 25 - 360 - - 360 - ns To 0.01% 25 - 600 - - 600 - ns Off Isolation Note 9 Settling Time, tS (HI-506 and HI-507) 25 - 68 - - 68 - dB Channel Input Capacitance, CS(OFF) 25 - 10 - - 10 - pF Channel Output Capacitance, CD(OFF) HI-506 25 - 52 - - 52 - pF HI-507 25 - 30 - - 30 - pF HI-508 25 - 17 - - 17 - pF HI-509 25 - 12 - - 12 - pF Digital Input Capacitance, CA 25 - 6 - - 6 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.08 - - 0.08 - pF DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH Full 2.4 - - 2.4 - - V Submit Document Feedback 8 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) -2 TEST CONDITIONS PARAMETER Input Leakage Current (High or Low), IA Note 8 TEMP (°C) MIN (Note 11) TYP Full - - Full -15 25 - 25 - 5 -4, -5, -9 MAX MIN (Note 11) TYP MAX UNITS 1.0 - - 1.0 A - +15 -15 - +15 V 180 300 - 180 400 - - 5 - % nA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN Note 6 On Resistance, rON rON , (Any Two Channels) Off Input Leakage Current, IS(OFF) Note 7 Note 7 Off Output Leakage Current, ID(OFF) HI-506 25 - 0.03 - - 0.03 - Full - - 50 - - 50 nA 25 - 0.3 - - 0.3 - nA Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA 25 - 0.3 - - 0.3 - nA HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA Full - - 50 - - 50 nA On Channel Leakage Current, ID(ON) Note 7 Differential Off Output Leakage Current, IDIFF (HI-507, HI-509 Only) POWER SUPPLY CHARACTERISTICS Current, I+ HI-506/HI-507 Note 10 Full - 1.5 3.0 - 1.5 3.0 mA HI-508/HI-509 Note 10 Full - 1.5 2.4 - 1.5 2.4 mA Current, IHI-506/HI-507 Note 10 Full - 0.4 1.0 - 0.4 1.0 mA HI-508/HI-509 Note 10 Full - 0.4 1.0 - 0.4 1.0 mA Power Dissipation, PD HI-506/HI-507 Full - - 60 - - 60 mW HI-508/HI-509 Full - - 51 - - 51 mW NOTES: 6. VOUT = ±10V, IOUT = +1mA. 7. 10nA is the practical lower limit for high speed measurement in the production test environment. 8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25°C. 9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS , f = 100kHz. 10. VEN , VA = 0V or 2.4V. 11. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. Submit Document Feedback 9 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 1mA V2 IN OUT VIN rON = V2 1mA FIGURE 1A. TEST CIRCUIT 2.2 NORMALIZED RESISTANCE (REFERRED TO VALUE AT15V) ON RESISTANCE () 400 300 +125°C 200 +25°C 100 -55°C 0 -15 -10 -5 0 5 ANALOG INPUT (V) 10 15 -55°C TO +125°C VIN = 0V 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 10 11 12 13 14 15 SUPPLY VOLTAGE (V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA OFF OUTPUT LEAKAGE CURRENT ID(OFF) LEAKAGE CURRENT 10nA 0.8V EN ID(ON) OUT 1nA A 100pA 10pA 10V OFF INPUT LEAKAGE CURRENT IS(OFF) 25 50 75 100 ID(OFF) 10V 125 TEMPERATURE (°C) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE Submit Document Feedback 10 FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 12) FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A A 0.8V EN 10V A0 10V +10V +10V ID(ON) EN A1 2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 12) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 12) FIGURE 2. LEAKAGE CURRENTS NOTE: 12. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V) 70 SWITCH CURRENT (mA) 60 -55°C 50 +25°C 40 30 +125°C 20 A VIN 10 0 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (V) 14 16 FIGURE 3A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 3B. TEST CIRCUIT FIGURE 3. ON CHANNEL CURRENT +15V/+10V 8 A +ISUPPLY SUPPLY CURRENT (mA) VSUPPLY = 15V V+ IN 1 6 A3 A2 4 VA 2 3.5V VSUPPLY = 10V 0 50 1k 10k 100k TOGGLE FREQUENCY (Hz) 1M VA 10M A1 IN 2 THRU IN 7/15 A0 IN 8/16 EN HIGH = 3.5V LOW = 0V 50% DUTY CYCLE † Similar connection for HI-507/ HI-508/HI-509 FIGURE 4A. SUPPLY CURRENT vs TOGGLE FREQUENCY 10V/5V HI-506 † GND OUT V- A +10V/+5V 10 M 14 pF -ISUPPLY -15V/-10V FIGURE 4B. TEST CIRCUIT FIGURE 4. DYNAMIC SUPPLY CURRENT Submit Document Feedback 11 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) +15V V+ ACCESS TIME (ns) 600 50 VA 400 A3 IN 1 A2 IN 2 THRU IN 7/15 A1 HI-506 † A0 0 EN 3.5V 200 10V +10V IN 16 GND OUT V- 10 k 50 pF -15V 3 2 4 5 13 LOGIC LEVEL (HIGH) (V) 14 † Similar connection for HI-507/ 15 HI-508/HI-509 FIGURE 5A. ACCESS TIME vs LOGIC LEVEL (HIGH) 3.5V FIGURE 5B. TEST CIRCUIT ADDRESS DRIVE (VA) VA INPUT 2V/DIV. 50% 0V S1 ON +10V OUTPUT 10% OUTPUT 5V/DIV. -10V tA S16 ON 200ns/DIV. FIGURE 5D. WAVEFORMS FIGURE 5C. MEASUREMENT POINTS FIGURE 5. ACCESS TIME +15V A3 A2 VA 50 A1 V+ HI-506 † +5V IN 1 IN 2 THRU IN 7/IN 15 IN 8 /16 A0 3.5V VOUT EN GND OUT V- 200 50pF -15V † Similar connection for HI-507/HI-508/HI-509 FIGURE 6A. TEST CIRCUIT Submit Document Feedback 12 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) 3.5V VA INPUT 2V/DIV. S1 ON ADDRESS DRIVE (VA) 0V S16 ON OUTPUT 1V/DIV. OUTPUT 50% 50% tOPEN 100ns/DIV. FIGURE 6B. MEASUREMENT POINTS FIGURE 6C. WAVEFORMS FIGURE 6. BREAK-BEFORE-MAKE DELAY +15V A3 A2 A1 V+ HI-506 † IN 1 +10V IN 2 THRU IN 7/IN 15 IN 8 /16 A0 VOUT EN VA 50 GND OUT V- 50pF 200 -15V † Similar connection for HI-507/HI-508/HI-509 FIGURE 7A. TEST CIRCUIT ENABLE DRIVE 2V/DIV. 3.5V 50% ENABLE DRIVE (VA) 50% 0V OUTPUT 90% 10% DISABLED 0V ENABLED (S1 ON) OUTPUT 2V/DIV. tON(EN) tOFF(EN) 100ns/DIV FIGURE 7B. MEASUREMENT POINTS FIGURE 7C. WAVEFORMS FIGURE 7. ENABLE DELAYS Submit Document Feedback 13 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Typical Performance Curves TA = 25°C, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 100 (VS), (VD) OFF ISOLATION (dB) INPUT LOGIC THRESHOLD (V) 4 3 2 1 0 10 12 14 16 18 80 RL = 1k 60 RL = 10M 40 VEN = 0V CLOAD = 28pF VS = 7VRMS 20 0 104 20 105 POWER SUPPLY VOLTAGE (V) FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE 3 POWER SUPPLY CURRENT (mA) POWER SUPPLY CURRENT (mA) 107 FIGURE 9. OFF ISOLATION vs FREQUENCY 3 2 VEN = 2.4V VEN = 0V 1 0 -55 106 FREQUENCY (Hz) 2 EN = 5V 1 EN = 0V 0 -35 -15 -5 25 45 65 85 105 125 -55 -35 -15 TEMPERATURE (°C) FIGURE 10A. HI-506/HI-507 -5 25 45 65 85 105 125 TEMPERATURE (°C) FIGURE 10B. HI-508/HI-509 FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE Submit Document Feedback 14 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Die Characteristics METALLIZATION: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 Type: CuAl Thickness: 16kÅ ±2kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL (NOTE): 421 -VSUPPLY PROCESS: PASSIVATION: CMOS-DI Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-506 EN A0 A1 A2 HI-507 A3 GND EN A0 A1 A2 NC GND IN 1 IN 9 IN 1A IN 1B IN 2 IN 10 IN 2A IN 2B IN 3 IN 11 IN 3A IN 3B IN 4 IN 12 IN 4A IN 4B IN 5 IN 13 IN 5A IN 5B IN 6 IN 14 IN 6A IN 6B IN 7 IN 15 IN 7A IN 7B IN 8 IN 16 IN 8A IN 8B -V OUT Submit Document Feedback +V 15 NC -V OUT A +V OUT B FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Die Characteristics METALLIZATION: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 Type: CuAl Thickness: 16kÅ 2kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL (NOTE): 234 -VSUPPLY PROCESS: PASSIVATION: CMOS-DI Type: Nitride/Silox Nitride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-508 EN A0 A1 A2 HI-509 GND EN A0 +VSUP -VSUP A1 GND -VSUP +VSUP IN 1 IN 5 IN 1A IN 1B IN 2 IN 6 IN 2A IN 2B IN 3A IN 3 IN 3B IN 7 IN 4 OUT Submit Document Feedback IN 8 16 IN 4A OUT A OUT B IN 4B FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE May 24, 2016 FN3142.10 Updated ordering information table on page 2. August 7, 2015 FN3142.9 Updated ordering information table on page 2. Added Revision History and About Intersil sections. Updated M28.3 to most recent revision with change as follows: Added land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support Submit Document Feedback 17 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Dual-In-Line Plastic Packages (PDIP) N E16.3 (JEDEC MS-001-BB ISSUE D) E1 INDEX AREA 1 2 3 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE N/2 INCHES -B- SYMBOL -AE D BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 eA A1 eC B 0.010 (0.25) M C L C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. MILLIMETERS MIN MAX MIN MAX A - A1 0.015 NOTES 0.210 - 5.33 4 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 0.150 2.93 3.81 4 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . N 16 16 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). Submit Document Feedback 18 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. D 1.380 1.565 D1 0.005 - 35.1 0.13 39.7 5 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 28 28 9 Rev. 1 12/00 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). Submit Document Feedback 19 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL (c) E M -Bbbb S C A-B S Q -C- SEATING PLANE S1 b2 b ccc M C A-B S eA/2 - 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 c aaa M C A - B S D S D S NOTES 0.014 eA e MAX b A A MIN A A L MILLIMETERS MAX M (b) D BASE PLANE MIN b1 SECTION A-A D S INCHES SYMBOL NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. N 16 16 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 20 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL (c) E M -Bbbb S C A-B S Q -C- SEATING PLANE S1 b2 b ccc M C A-B S eA/2 - 0.232 - 5.92 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 15.49 5 c aaa M C A - B S D S D S NOTES 0.014 eA e MAX b A A MIN A A L MILLIMETERS MAX M (b) D BASE PLANE MIN b1 SECTION A-A D S INCHES SYMBOL NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 12.70 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. N 28 28 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 21 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 16 0° 16 8° 0° 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. Submit Document Feedback 22 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45o a e A1 B C 0.10(0.004) 0.25(0.010) M C A M B S MAX MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e -C- MIN 0.05 BSC h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 10.00 - 0.394 N 0.419 1.27 BSC H 28 0o 10.65 - 28 8o 0o 7 8o Rev. 1, 1/13 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. TYPICAL RECOMMENDED LAND PATTERN (1.50mm) 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.38mm) 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) (1.27mm TYP) Submit Document Feedback (0.51mm TYP) 23 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 E1 E C L D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.385 0.395 9.78 10.03 - D1 0.350 0.356 8.89 9.04 3 D2 0.141 0.169 3.59 4.29 4, 5 E 0.385 0.395 9.78 10.03 - E1 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4, 5 N 20 20 6 Rev. 2 11/97 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN N20.35 (JEDEC MS-018AA ISSUE A) VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. Submit Document Feedback 24 FN3142.10 June 14, 2016 HI-506, HI-507, HI-508, HI-509 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) PIN (1) IDENTIFIER 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 E1 E C L D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D N28.45 (JEDEC MS-018AB ISSUE A) 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN 6 Rev. 2 11/97 VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 25 FN3142.10 June 14, 2016