ISL12057 ® Low Cost and Low Power I2C RTC Real Time Clock/Calendar Data Sheet June 15, 2009 Low Power and Low Cost RTC with Alarm Function and Dual IRQ pins The ISL12057 device is a low power real time clock that is pin compatible and functionally equivalent to Maxim DS1337 with clock/calendar and alarm function. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. Pinouts FN6755.0 Features • Pin Compatible to Maxim DS1337 • Functionally Equivalent to Maxim DS1337 • Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds - Day of the Week, Date, Month, and Year • Dual Interrupts for Frequency Output and Alarm interrupts • 4 Selectable Frequency Outputs • 2 Alarms - Settable to the Second, Minute, Hour, Day of the Week, and Date • I2C Interface - 400kHz Data Transfer Rate ISL12057 (8 LD SOIC, MSOP) TOP VIEW X1 1 8 VDD X2 2 7 IRQ1/FOUT IRQ2 3 6 SCL GND 4 5 SDA • Small Package Options - 8 Ld 2mmx2mm µTDFN - 8 Ld MSOP - 8 Ld SOIC - Pb-Free (RoHS Compliant) Applications • Utility Meters • HVAC Equipment • Audio/Video Components ISL12057 (8 LD µTDFN) TOP VIEW • Set-Top Box/Television • Modems 8 VDD • Network Routers, Hubs, Switches, Bridges 7 IRQ1/FOUT • Cellular Infrastructure Equipment 3 6 SCL 4 5 SDA X1 1 X2 2 IRQ2 GND • Fixed Broadband Wireless Equipment • Pagers/PDA • Point Of Sale Equipment • Test Meters/Fixtures • Office Automation (Copiers, Fax) • Home Appliances • Computer Products • Other Industrial/Medical/Automotive 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL12057 Ordering Information PART NUMBER PART MARKING VDD RANGE (V) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL12057IBZ (Note 1) 12057 IBZ 1.4 to 3.6 -40 to +85 8 Ld SOIC ISL12057IBZ-T* (Note 1) 12057 IBZ 1.4 to 3.6 -40 to +85 8 Ld SOIC (Tape and Reel) M8.15 ISL12057IUZ (Note 1) 12057 1.4 to 3.6 -40 to +85 8 Ld MSOP M8.118 ISL12057IUZ-T* (Note 1) 12057 1.4 to 3.6 -40 to +85 8 Ld MSOP (Tape and Reel) M8.118 1.4 to 3.6 -40 to +85 8 Ld µTDFN (Tape and Reel) L8.2x2 ISL12057IRUZ-T* (Note 2) 057 M8.15 *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram SDA SDA BUFFER SCL SCL BUFFER SECONDS I2C INTERFACE RTC CONTROL LOGIC MINUTES HOURS DAY OF WEEK X1 X2 CRYSTAL OSCILLATOR RTC DIVIDER DATE MONTH VDD POR YEAR FREQUENCY OUT ALARM2 ALARM1 CONTROL REGISTERS IRQ2 INTERNAL SUPPLY IRQ1/ FOUT 2 FN6755.0 June 15, 2009 ISL12057 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. This pin can also be driven by an external 32.768kHz oscillator with X2 pin floating. 2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 3 IRQ2 Interrupt Output 2 is a multi-functional pin that can be used as alarm interrupt. This pin is open drain and requires an external pull-up resistor. This pin is at high impedance at power up. 4 GND Ground 5 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. 6 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 7 IRQ1/FOUT 8 VDD Interrupt Output 1/Frequency Output is a multi-functional pin that can be used as alarm interrupt or frequency output pin. The function is set via the configuration register. This pin is open drain and requires an external pull-up resistor. It has a default output of 32.768kHz at power up. Power supply 3 FN6755.0 June 15, 2009 ISL12057 Absolute Maximum Ratings Thermal Information Voltage on VDD (respect to GND) . . . . . . . . . . . . . . . . . . -0.2V to 4V Thermal Resistance (Typical) Voltage on IRQ1/FOUT, IRQ2, SCL and SDA (respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 6V Voltage on X1 and X2 Pins (respect to GND) . . . . . . . . . -0.2V to 4V ESD Rating ((Per MIL-STD-883 Method 3014) Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>350V 8 Lead SOIC (Note 3) . . . . . . . . . . . . . . . . . . . . . . . 120 8 Lead MSOP (Note 3). . . . . . . . . . . . . . . . . . . . . . . 169 8 Lead µTDFN (Note 3) . . . . . . . . . . . . . . . . . . . . . . 160 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp θJA (°C/W) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN (Note 6) TYP (Note 5) MAX (Note 6) UNITS VDD Full Operation Power Supply 1.8 3.6 V VDDT Timekeeping Power Supply 1.4 1.8 V IDD1 Standby Supply Current 950 nA IDD2 Timekeeping Current IDD3 Supply Current With I2C Active at Clock VDD = 3.6V 600 VDD = 3.3V 500 VDD = 1.8V 400 VDD = 1.6V 350 VDD = 3.6V 15 NOTES 4, 10 nA 650 nA 4, 10 nA 40 µA 4 Speed of 400kHz ILI Input Leakage Current on SCL -100 100 nA ILO I/O Leakage Current on SDA -100 100 nA 0.4 V IRQ1/FOUT and IRQ2 VOL Output Low Voltage VDD = 1.8V, IOL = 3mA Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 5) MAX (Note 6) UNITS NOTES SERIAL INTERFACE SPECS VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD 5.5 V Hysteresis SDA and SCL Input Buffer Hysteresis VPULLUP 0.04 x VDD Maximum Pull-up voltage on SDA during I2C communication VOL SDA Output Buffer LOW Voltage, VDD > 1.8V, VPULLUP = 5.0V Sinking 3mA Cpin SDA and SCL Pin Capacitance fSCL SCL Frequency TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V 0 V VDD + 2 V 0.4 V 10 pF 400 kHz tIN Pulse width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns 4 9 7, 8 9 FN6755.0 June 15, 2009 ISL12057 Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 5) MAX (Note 6) UNITS NOTES tBUF Time the Bus Must Be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window 0 tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD 600 ns tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both crossing 70% of VDD 600 ns Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window 0 ns tR SDA and SCL Rise Time From 30% to 70% of VDD 20 + 0.1 x Cb 300 ns 7, 8 tF SDA and SCL Fall Time From 70% to 30% of VDD 20 + 0.1 x Cb 300 ns 7, 8, 9 10 400 pF 7, 8 kΩ 7, 8 tDH Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip Rpu SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2kΩ to~2.5kΩ. For Cb = 40pF, max is about 15kΩ to ~20kΩ 900 1 ns NOTES: 4. IRQ1/FOUT inactive. 5. Typical values are for T = +25°C and 3.3V supply voltage. 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits should be considered typical and are not production tested. 8. These are I2C specific parameters and are not production tested, however, they are used to set conditions for testing devices to validate specification. 9. Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I2C parameters are not guaranteed. 10. Specified at +25°C. 5 FN6755.0 June 15, 2009 ISL12057 SDA vs SCL Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533Ω FOR VOL= 0.4V AND IOL = 3mA SDA, IRQ1/FOUT AND IRQ2 100pF FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V 6 FN6755.0 June 15, 2009 ISL12057 Typical Performance Curves Temperature is +25°C unless otherwise specified 0.7 1.0 0.6 0.8 3.6 IDD1 (µA) IDD1 (µA) 0.5 0.4 0.3 0.2 0.6 3.0 0.4 0.1 0 1.4 1.8 1.4 1.9 2.4 2.9 3.4 0.2 -40 -20 0 FIGURE 2. IDD1 vs VDD 60 80 32769.0 1.1 32768.8 32768Hz 1.0 32768.6 32768.4 FOUT (Hz) 0.9 IDD (µA) 40 FIGURE 3. IDD1 vs TEMPERATURE 1.2 0.8 8192Hz 0.7 0.6 4096Hz 32768.2 32768.0 32767.8 32767.6 0.5 32767.4 0.4 1Hz 0.3 0.2 1.4 20 TEMPERATURE (°C) VDD (V) 1.9 2.4 2.9 32767.2 3.4 32767.0 1.4 1.9 VDD (V) FIGURE 4. IDD vs VDD vs FOUT Pin Description The ISL12057 device is a low power real time clock with clock/calendar, power fail indicator, and alarm function. X1, X2 The ISL12057 has two flexible alarms; each can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on 1st day of a month. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ1/FOUT or IRQ2 pin. There is a repeat mode for the alarm allowing a periodic interrupt every second or every minute. 7 2.9 3.4 FIGURE 5. FOUT VS VDD WITH A TYPICAL 32.768kHZ CRYSTAL General Description The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. 2.4 VDD (V) The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12057 to supply a timebase for the real time clock. Refer to Figure 6. The device can also be driven directly from a 32.768kHz square wave source with peak-to-peak voltage from 0V to VDD at X1 pin with X2 pin floating. X1 X2 FIGURE 6. RECOMMENDED CRYSTAL CONNECTION FN6755.0 June 15, 2009 ISL12057 IRQ1/FOUT (Interrupt Output 1/Frequency Output) This dual function pin can be used as an alarm interrupt or frequency output pin. The IRQ1/FOUT mode is selected via the control register (address 0Eh). The IRQ1/FOUT is an open drain output. This pin has a default output of 32.768kHz at power-up. • Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. • Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. IRQ2 (Interrupt Output 2) The IRQ2 pin is used as an Alarm1 interrupt or/and Alarm2 interrupt. The IRQ2 mode is selected via the control register (address 0Eh). The IRQ2 is an open drain output. This pin is high impedance at power-up. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. Serial Clock (SCL) The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). The SCL pin can accept a logic high voltage up to 5.5V. corrects for months having fewer than 31 days and has a bit that controls 24-hour or AM/PM format. The clock will begin incrementing after power-up with valid oscillator condition. ACCURACY OF THE REAL TIME CLOCK The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer. I2C Serial Interface The ISL12057 has an I2C serial bus interface that provides access to the real time clock registers, control and status registers and the alarm registers. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bidirectional data signal (SDA) and a clock signal (SCL). Register Descriptions The registers are accessible following a slave byte of “1101000x” and reads or writes to addresses [00h:0Fh]. The defined addresses and default values are described in Table 1. REGISTER ACCESS Serial Data (SDA) SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor, and it can accept a pull-up voltage up to 5.5V. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. NOTE: Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I2C parameters are not guaranteed. VDD, GND Chip power supply and ground pins. The device will have full operation with a power supply from 1.8V to 3.6VDC, and timekeeping function with a power supply from 1.4V to 1.8V. A 0.1µF decoupling capacitor is recommended on the VDD pin to ground. Functional Description The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The address will wrap around from 0Fh to 00h. The registers are divided into 3 sections. These are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Alarm (7 bytes): Address 07h to 0Dh. 3. Control and Status (2 bytes): Address 0Eh to 0Fh. There are no addresses above 0Fh. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read or write instruction, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. Real Time Clock Operation The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The RTC also 8 FN6755.0 June 15, 2009 ISL12057 TABLE 1. REGISTER MEMORY MAP BIT REG REG NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0-59 00h 01H MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0-59 00h 02H HR 0 MIL AM/PM HR20 HR13 HR12 HR11 HR10 1-12 +AM/PM 00h ADDR SECTION 00H RTC HR21 0-23 03H DW 0 0 0 0 0 DW12 DW11 DW10 1-7 01h 04H DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1-31 01h 05H MO CENTUR 0 0 MO20 MO13 MO12 MO11 MO10 0-12 +Century 01h Y 06h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0-99 00h A1SC A1M1 A1SC22 A1SC21 A1SC20 A1SC13 A1SC12 A1SC11 A1SC10 0-59 00h 08h A1MN A1M2 A1MN22 A1MN21 A1MN20 A1MN13 A1MN12 A1MN11 A1MN10 0-59 00h 09h A1HR A1M3 A1MIL A1AM/PM A1HR20 A1HR13 A1HR12 A1HR11 A1HR10 1-12 +AM/PM 00h 07h Alarm1 A1HR21 0Ah 0Bh A1DW/ DT Alarm2 0Ch A1M4 A1DW/DT 0-23 0 0 0 A1DW12 A1DW11 A1DW10 1-7 00h A1DT21 A1DT20 A1DT13 A1DT12 A1DT11 A1DT10 1-31 00h A2MN A2M2 A2MN22 A2MN21 A2MN20 A2MN13 A2MN12 A2MN11 A2MN10 0-59 00h A2HR A2M3 A2MIL A2AM/PM A2HR20 A2HR13 A2HR12 A2HR11 A2HR10 1-12 +AM/PM 00h A2HR21 0Dh A2DW/ DT A2M4 A2DW/DT 0-23 0 0 0 A2DW12 A2DW11 A2DW10 1-7 00h A2DT21 A2DT20 A2DT13 A2DT12 A2DT11 A2DT10 1-31 00h 0Eh Control INT EOSC 0 0 RS2 RS1 INTCN A2IE A1IE N/A 18h 0Fh Status SR OSF 0 0 0 0 0 A2F A1F N/A 80h Real Time Clock Registers Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR) These registers depict BCD representations of the time. As such, SC (Seconds, address 00h) and MN (Minutes, address 01h) range from 0 to 59, HR (Hour, address 02h) can either be a 12-hour or 24-hour mode, DW (Day of the Week, address 03h) is 1 to 7, DT (Date, address 04h) is 1 to 31, MO (Month, address 05h) is 1 to 12, and YR (Year, address 06h) is 0 to 99. The DW register provides a Day of the Week status and uses 3 bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 1-2-3-4-5-6-7-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. bit with logic high being PM. The clock defaults to 24-hour format time. CENTURY INDICATOR The century bit (bit 7 of the MO register) is toggled when the years register overflows from 99 to 00 to indicator the change of century. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL12057 does not correct for the leap year in the year 2100. Addresses [0Eh to 0Fh] The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register. 24-HOUR TIME If the MIL bit of the HR register is “0”, the RTC uses a 24-hour format and bit 5 of the HR register is the second 10-hour bit (20–23 hours). If the MIL bit is “1”, the RTC uses a 12-hour format and bit 5 of the HR register is the AM/PM 9 FN6755.0 June 15, 2009 ISL12057 Interrupt Control Register (INT) [Address 0Eh] Status Register (SR) [Address 0Fh] TABLE 2. INTERRUPT CONTROL REGISTER (INT) ADDR 7 6 5 4 3 2 1 0 0Eh EOSC 0 0 RS2 RS1 INTCN A2IE A1IE Default 0 0 0 1 1 0 0 0 OSCILLATOR ENABLE BIT (EOSC) The EOSC bit enables the crystal oscillator function when it is set to “0”. When the EOSC bit is set to “1”, the crystal oscillator function is disable and the device enters into power saving mode. The EOSC bit is set to “0” at power-up. FREQUENCY OUT CONTROL BITS (RS2, RS1) These bits select the output frequency at the IRQ1/FOUT pin. INTCN must be set to “0” for frequency output at the IRQ1/FOUT pin. Please see Table 3 for Frequency Selection of the FOUT pin. TABLE 3. FREQUENCY SELECTION OF FOUT PIN FREQUENCY FOUT (Hz) RS2 RS1 32768 1 1 Free running crystal clock 8192 1 0 Free running crystal clock 4096 0 1 Free running crystal clock 1 0 0 Sync at RTC write COMMENT INTERRUPT CONTROL BIT (INTCN) AND ALARM INTERRUPT ENABLE BITS (A2IE, A1IE) The INTCN bit controls the relationship between the alarm interrupts and the IRQ1/FOUT and IRQ2 pins. The A2IE and A1IE bits enable the alarm interrupts, A2F and A1F, to assert the IRQ1/FOUT and IRQ2 pins. Please see Table 4 for Alarm Interrupt Selection with INTCN, A2IE and A1IE bits. TABLE 4. ALARM INTERRUPT SELECTION WITH INTCN, A2IE AND A1IE BITS INTCN A2IE A1IE IRQ1/FOUT IRQ2 0 0 0 FOUT HIGH 0 0 1 FOUT A1F 0 1 0 FOUT A2F 0 1 1 FOUT A1F or A2F 1 0 0 HIGH HIGH 1 0 1 HIGH A1F 1 1 0 A2F HIGH 1 1 1 A2F A1F 10 The Status Register is located in the memory map at address 0Fh. This is a volatile register that provides status of oscillator failure and alarm interrupts. TABLE 5. STATUS REGISTER (SR) ADDR 7 6 5 4 3 2 1 0 0Fh OSF 0 0 0 0 0 A2F A1F Default 1 0 0 0 0 0 0 0 ALARM1 INTERRUPT BIT (A1F) These bits announce if the Alarm1 matches the real time clock. If there is a match, the respective bit is set to “1”. This bit is manually reset to “0” by the user. A write to this bit in the SR can only set it to “0”, not “1”. ALARM2 INTERRUPT BIT (A2F) These bits announce if the Alarm2 matches the real time clock. If there is a match, the respective bit is set to “1”. This bit is manually reset to “0” by the user. A write to this bit in the SR can only set it to “0”, not “1”. OSCILLATOR FAILURE BIT (OSF) This bit is set to a “1” when there is no oscillation on X1 pin. This is set by hardware (ISL12057 internally), and can only be disabled by having an oscillation on X1 and and manually reset to “0” to reset it.. Alarm1 Registers Addresses [Address 07h to 0Ah] The Alarm1 register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “0”). These enable bits specify which alarm registers (seconds, minutes, etc) are used to make the comparison. When all the enable bits are set to “1”, the Alarm1 will trigger once per second. Note that there is no alarm byte for month and year. The Alarm1 function works as a comparison between the Alarm1 registers and the RTC registers. As the RTC advances, the Alarm1 will be triggered once a match occurs between the Alarm1 registers and the RTC registers. Any one Alarm1 register, multiple registers, or all registers can be enabled for a match. To clear an Alarm1, the A1F status bit must be set to “0” with a write. TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS SELECTION A1DW/DT A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT X 1 1 1 1 Every Second X 0 1 1 1 Match Second X 1 0 1 1 Match Minute FN6755.0 June 15, 2009 ISL12057 TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS SELECTION (Continued) A1DW/DT A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT make the comparison. When all the enable bits are set to “1”, the Alarm2 will trigger once per minute. Note that there are no alarm bytes for second, month and year. The Alarm2 function works as a comparison between the Alarm2 registers and the RTC registers. As the RTC advances, the Alarm2 will be triggered once a match occurs between the Alarm2 registers and the RTC registers. Any one Alarm2 register, multiple registers, or all registers can be enabled for a match. X 1 1 0 1 Match Hour 0 1 1 1 0 Match Date 1 1 1 1 0 Match Day 0 0 0 1 1 Match Second and Minute 0 0 1 0 1 Match Second and Hour 0 0 0 0 0 Match Second, Minute and Hour To clear an Alarm2, the A2F status bit must be set to “0” with a write. . . . . . . . . . . . . TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS SELECTION 0 1 0 0 0 Match Minute Hour and Date 0 0 0 0 0 Match Second, Minute Hour and Date A2DW/DT A2M2 A2M3 A2M4 ALARM2 INTERRUPT X 1 1 1 Every Minute (Second=00) X 0 1 1 Match Minute . . . . . . . . . . . . X 1 0 1 Match Hour 0 1 1 0 Match Date 1 1 0 0 0 Match Minute, Hour, and Day 1 1 1 0 Match Day 1 0 0 0 0 Match Second, Minute, Hour, and Day X 0 0 1 Match Minute and Hour 0 1 0 0 Match Hour and Date 0 0 1 0 Match Minute and Date 0 0 0 0 Match Minute, Hour, and Date 1 0 1 0 Match Minute and Day 1 1 0 0 Match Hour and Day 1 0 0 0 Match Minute, Hour, and Day Note: X is don’t care, it can be set to 0 or 1. Following is example of Alarm1 Interrupt. Example – A single alarm will occur on Monday at 11:30am (Monday is when DW = 2). A. Set Alarm1 registers as follows: ALARM1 REGISTER 7 BIT Note: X is don’t care, it can be set to 0 or 1. 6 5 4 3 2 1 0 HEX DESCRIPTION Following is example of Alarm2 Interrupt. A1SC 1 0 0 0 0 0 0 0 80h Seconds disabled A1MN 0 0 1 1 0 0 0 0 30h Minutes set to 30, enabled Example – A single alarm will occur on every 1st day of the month at 20:00 military time. A1HR 0 1 0 1 0 0 0 1 51h Hours set to 11am, enabled A. Set Alarm registers as follows: A1DW/DT 0 1 0 0 0 0 1 0 42h Day set to 1, enabled After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the A1F bit in the status register to “1”. Alarm2 Registers Addresses [Address 12h to 14h] The Alarm2 register bytes are set up identical to the RTC register bytes except that the MSB of each byte functions as an enable bit (enable = “0”). These enable bits specify which alarm registers (minutes, hour, and date/day) are used to 11 ALARM2 REGISTER 7 BIT 6 5 4 3 2 1 0 HEX A2MN 1 0 0 0 0 0 0 0 80h Minutes disabled DESCRIPTION A2HR 0 0 1 0 0 0 0 0 20h Hours set to 20, enabled A2DW/DT 0 0 0 0 0 0 0 1 01h Date set to 1st, enabled After these registers are set, an alarm will be generated when the RTC advances to exactly 20:00 on Monday (after minutes changes from 59 to 00) by setting the A2F bit in the status register to “1”. FN6755.0 June 15, 2009 ISL12057 I2C Serial Interface The ISL12057 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL12057 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 7). On power-up of the ISL12057, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL12057 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 7). A START condition is ignored during the power-up sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 7). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure 8). The ISL12057 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL12057 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. SCL SDA DATA STABLE START DATA CHANGE DATA STABLE STOP FIGURE 7. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 SDA OUTPUT FROM TRANSMITTER 9 HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER 12 FN6755.0 June 15, 2009 ISL12057 WRITE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA ADDRESS BYTE IDENTIFICATION BYTE 1 1 0 1 0 0 0 0 SIGNALS FROM THE ISL12057 S T O P LAST DATA BYTE FIRST DATA BYTE 0 0 0 0 A C K A C K A C K A C K A C K FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE Device Addressing Write Operation Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are “1101000”. Slave bits “1101” access the register. Slave bits “000” specify the device select bits. A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL12057 responds with an ACK. At this time, the I2C interface enters a standby state. The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a “1”, then a read operation is selected. A “0” selects a write operation (refer to Figure 10). After loading the entire Slave Address Byte from the SDA bus, the ISL12057 compares the device identifier and device select bits with “1101000”. Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up, the internal address counter is set to address 0h, so a current address read of the RTC array starts at address 0h. When required, as part of a random read, the master must supply the 1 Word Address Bytes as shown in Figure 11. In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the “read” section. For a random read of the Clock/Control Registers, the slave byte must be “1101000x” in both places. R/W SLAVE ADDRESS BYTE A1 A0 WORD ADDRESS D1 D0 DATA BYTE 1 1 0 1 0 0 0 A7 A6 A5 A4 A3 A2 D7 D6 D5 D4 D3 D2 Read Operation A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 11). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL12057 responds with an ACK. Then the ISL12057 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (see Figure 11). The Data Bytes are from the memory location indicated by an internal pointer. This pointer’s initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 13h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES 13 FN6755.0 June 15, 2009 ISL12057 Application Section SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 S T IDENTIFICATION A BYTE WITH R R/W = 1 T ADDRESS BYTE S T O P A C K 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 A C K SIGNALS FROM THE SLAVE A C K A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 11. READ SEQUENCE Oscillator Crystal Requirements The ISL12057 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 8 lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL12057 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 6pF and an equivalent series resistance of less than 50k. The crystal’s temperature range specification should match the application. Many crystals are rated for -10°C to +60°C (especially through-hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. TABLE 8. SUGGESTED SURFACE MOUNT CRYSTALS MANUFACTURER PART NUMBER Citizen CM200S MicroCrystal MS3V ECS ECX-306 2. Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device. FIGURE 12. SUGGESTED LAYOUT FOR ISL12057 AND CRYSTAL In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. If the IRQ1/FOUT pin is used as a clock, it should be routed away from the RTC device as well. The trace for the VCC pins can be treated as a ground, and should be routed around the crystal. Layout Considerations The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies (such as 32.768kHz) are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. Figure 12 shows a suggested layout for the ISL12057 device using a surface mount crystal. Two main precautions should be followed: 1. Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit to cause misclocking. 14 FN6755.0 June 15, 2009 ISL12057 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X θ L1 SEATING PLANE C 0.20 (0.008) C a CL E1 C D MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC -B- 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N C 0.20 (0.008) MIN A L1 -A- SIDE VIEW SYMBOL e L MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 15 FN6755.0 June 15, 2009 ISL12057 Package Outline Drawing L8.2x2 8 Lead Ultra Thin Dual Flat No-Lead COL Plastic Package (UTDFN COL) Rev 3, 11/07 2X 1.5 2.00 A 6 PIN 1 INDEX AREA PIN #1 INDEX AREA 6 B 6X 0.50 1 4 7X 0.4 ± 0.1 1X 0.5 ±0.1 2.00 (4X) 0.15 8 5 TOP VIEW 0.10 M C A B 4 0.25 +0.05 / -0.07 BOTTOM VIEW ( 8X 0 . 25 ) SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX 0.10 C C BASE PLANE SEATING PLANE 0.08 C (1.8 ) SIDE VIEW C ( 7X 0 . 60 ) 0 . 2 REF 0 . 00 MIN. 0 . 05 MAX. ( 6X 0 . 5 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 16 FN6755.0 June 15, 2009 ISL12057 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6755.0 June 15, 2009