DATASHEET

ACTS630MS
TM
Radiation Hardened EDAC
(Error Detection and Correction)
January 1996
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96721 and Intersil’s QM Plan
itle
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28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835
DESIGNATOR CDIP-T28, LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
DEF 1
28 VCC
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
DB0 2
27 SEF
DB1 3
26 S1
DB2 4
25 S0
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
DB3 5
24 CB0
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
DB4 6
23 CB1
DB5 7
22 CB2
DB6 8
21 CB3
DB7 9
20 CB4
DB8 10
19 CB5
DB9 11
18 DB15
DB10 12
17 DB14
DB11 13
16 DB13
GND 14
15 DB12
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
• Dose Rate Survivability . . . . . . . . . . . >10
12
-10
Errors/Bit/Day
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
oC
to
+125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)
Description
The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error
detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is
stored with the data word during a memory write cycle; during a memory
read cycle a 22-bit word is taken form memory and checked for errors.
Single bit errors in the data words are flagged and corrected. Single bit
errors in check words are flagged but not corrected. The position of the
incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome
code which is output during the error correction cycle.
The ACTS630MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
28 PIN CERAMIC FLATPACK, MIL-STD-1835
DESIGNATOR CDFP3-F28, LEAD FINISH C
TOP VIEW
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
SEF
S1
S0
CB0
CB1
CB2
CB3
CB4
CB5
DB15
DB14
DB13
DB12
The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or
a 28 Lead Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
5962F9672101VXC
-55oC
5962F9672101VYC
-55oC
SCREENING LEVEL
PACKAGE
to
+125oC
MIL-PRF-38535 Class V
28 Lead SBDIP
to
+125oC
MIL-PRF-38535 Class V
28 Lead Ceramic Flatpack
ACTS630D/Sample
o
25 C
Sample
28 Lead SBDIP
ACTS630K/Sample
25oC
Sample
28 Lead Ceramic Flatpack
ACTS630HMSR
25oC
Die
Die
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
Spec Number
File Number
518786
3204.1
ACTS630MS
Function Tables
Control Functions
CONTROL
ERROR FLAGS
MEMORY
CYCLE
S1
S0
WRITE
Low
Low
Generates Checkword
Input Data
READ
Low
High
Read Data and Checkword
READ
High
High
READ
High
Low
EDAC FUNCTION
DATA I/O
CHECKWORD
SEF
DEF
Output Checkword
Low
Low
Input Data
Input Checkword
Low
Low
Latch and Flag Error
Latch Data
Latch Checkword
Enabled
Enabled
Correct Data Word and
Generate Syndrome Bits
Output Corrected
Data
Output Syndrome
Bits
Enabled
Enabled
12
14
Check Word Generation
16-BIT DATA WORD
CHECKWORD BIT
0
1
CB0
X
X
CB1
X
X
CB2
CB3
2
X
X
X
X
X
CB4
3
4
X
X
5
X
6
X
X
X
7
X
9
10
X
X
X
X
X
11
X
X
X
X
X
X
X
X
15
X
X
CB5
13
X
X
X
X
8
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTE: The six check bits are parity bits derived from the matrix of data bits as indicated by “x” for each bit
Error Syndrome Codes
ERROR LOCATIONS
SYNDROME
ERROR
CODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
NO
ERROR
CB0
L
L
H
L
L
H
H
H
L
L
L
H
H
L
H
H
L
H
H
H
H
H
H
CB1
L
H
L
L
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
H
H
H
H
CB2
H
L
L
H
L
L
H
L
H
L
H
H
L
H
H
L
H
H
L
H
H
H
H
CB3
L
L
L
H
H
H
L
L
H
H
L
L
L
H
H
H
H
H
H
L
H
H
H
CB4
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
H
H
H
H
L
H
H
CB5
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
DB
CB
Error Functions
TOTAL NUMBER OF ERRORS
ERROR FLAGS
16-BIT DATA
6-BIT CHECKWORD
SEF
DEF
DATA CORRECTION
0
0
Low
Low
Not Applicable
1
0
High
Low
Correction
0
1
High
Low
Correction
1
1
High
High
Interrupt
2
0
High
High
Interrupt
0
2
High
High
Interrupt
Spec Number
2
518786
ACTS630MS
Die Characteristics
DIE DIMENSIONS:
171 mils x 159 mils
6.7µm x 6.3µm
METALLIZATION:
Type: Al/Si/
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
110µm x 110µm
4.3 mils x 4.3 mils
Metallization Mask Layout
ACTS630MS
DB2 DB1 DB0 DEF VCC SEF S1
(4)
(3) (2)
(1) (28) (27) (26)
DB3 (5)
(25) S0
DB4 (6)
(24) CB0
DB5 (7)
(23) CB1
DB6 (8)
(22) CB2
DB7 (9)
(21) CB3
DB8 (10)
(20) CB4
DB9 (11)
(19) CB5
(12) (13) (14) (15) (16) (17) (118)
DB10 DB11 GND DB12 DB13 DB14 DB15
Spec Number
3
518786
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