DATASHEET

HCS157MS
Radiation Hardened
Quad 2-Input Multiplexers
September 1995
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
16 VCC
S 1
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s, 20ns Pulse
1I0 2
15 E
1I1 3
14 4I0
1Y 4
13 4I1
• Latch-Up Free Under Any Conditions
2I0 5
12 4Y
• Military Temperature Range: -55oC to +125oC
2I1 6
11 3I0
• Significant Power Reduction Compared to LSTTL ICs
2Y 7
10 3I1
GND 8
9 3Y
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Description
The Intersil HCS157MS is a Radiation Hardened quad 2-input
multiplexers which select four bits of data from two sources under
the control of a common select input (S). The Enable input (E
NOT) is active low. When the enable pin is high all of the outputs
(1Y-4Y) are forced low regardless of all other input conditions.
Moving data from two groups of registers to four common output
busses is a common use of these devices. The state of the Select
input determines the particular register from which the data comes.
They can also be used as function generators.
S
1
16
1I0
2
15
E
1I1
3
14
4I0
VCC
1Y
4
13
4I1
2I0
5
12
4Y
2I1
6
11
3I0
2Y
7
10
3I1
GND
8
9
3Y
The HCS157MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS157MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS157DMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead SBDIP
HCS157KMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
+25oC
Sample
16 Lead SBDIP
HCS157K/Sample
+25oC
Sample
16 Lead Ceramic Flatpack
HCS157HMSR
+25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
173
DB NA
HCS157D/Sample
Spec Number
File Number
518833
3561.1
HCS157MS
Functional Block Diagram
S
E
4I1
4I0
3I1
3I0
2I1
2I0
1I1
1I0
1
15
13
12
4Y
14
10
11
9
3Y
6
3 CIRCUITS IDENTICAL TO CIRCUIT
IN ABOVE DASHED OUTLINE
5
7
3
4
2
2Y
1Y
TRUTH TABLE
ENABLE
SELECT
INPUTS
E
S
I0
I1
Y
H
X
X
X
L
L
L
L
X
L
L
L
H
X
H
L
H
X
L
L
L
H
X
H
H
DATA INPUTS
OUTPUT
H = High Level
L = Low Level
X = Immaterial
Spec Number
174
518833
Specifications HCS157MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W
29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .100ns Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . VCC to 70% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . .0V to 30% of VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
750
µA
1
+25oC
7.2
-
mA
2, 3
+125oC, -55oC
6.0
-
mA
1
+25oC
-7.2
-
mA
2, 3
+125oC, -55oC
-6.0
-
mA
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-
±0.5
µA
2, 3
+125oC, -55oC
-
±5.0
µA
7, 8A, 8B
+25oC, +125oC, -55oC
-
-
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V,
(Note 2)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V, (Note 2)
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 3)
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. Force/Measure functions may be interchanged.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
175
518833
Specifications HCS157MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Data to Output
SYMBOL
TPHL
TPLH
Propagation Delay
Enable to Output
TPHL
TPLH
Propagation Delay
Select to Output
(NOTES 1, 2)
CONDITIONS
TPHL
TPLH
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
26
ns
10, 11
+125oC, -55oC
2
30
ns
9
+25oC
2
20
ns
10, 11
+125oC, -55oC
2
24
ns
9
+25oC
2
22
ns
10, 11
+125oC, -55oC
2
25
ns
9
+25oC
2
22
ns
10, 11
+125oC, -55oC
2
25
ns
9
+25oC
2
31
ns
10, 11
+125oC, -55oC
2
37
ns
9
+25oC
2
25
ns
10, 11
+125oC, -55oC
2
29
ns
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
Output Transition
Time
CIN
TTHL,
TTLH
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
68
pF
1
+125oC, -55oC
-
84
pF
1
+25oC
-
10
pF
1
+125oC, -55oC
-
10
pF
1
+25oC
-
15
ns
1
+125oC, -55oC
-
22
ns
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
VCC = 4.5V VIH = 4.5V,
VIL = 0V,
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
176
518833
Specifications HCS157MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
TEMPERATURE
MIN
MAX
UNITS
Supply Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.75
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25oC
6.0
-
mA
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25oC
-6.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V , VIH = 3.15,
VIL = 1.35V, IOL = 50µA
+25oC
-
0.1
V
VCC = 5.5V, VIH = 3.85,
VIL =1.65V, IOL = 50µA
+25oC
-
0.1
V
VCC = 4.5V, VIH = 3.15,
VIL = 1.35V, IOH = -50µA
+25oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 3.85,
VIL = 1.65V, IOH = -50µA
+25oC
VCC
-0.1
-
V
Output Voltage High
VOH
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±5
µA
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 3.15V, VIL = 1.35V,
(Note 3)
+25oC
-
-
-
TPHL
VCC = 4.5V
+25oC
2
30
ns
TPLH
VCC = 4.5V
+25oC
2
24
ns
TPHL
VCC = 4.5V
+25oC
2
25
ns
TPLH
VCC = 4.5V
+25oC
2
25
ns
TPHL
VCC = 4.5V
+25oC
2
37
ns
TPLH
VCC = 4.5V
+25oC
2
29
ns
Propagation Delay
Data to Output
Propagation Delay
Enable to Output
Propagation Delay
Select to Output
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
12µA
IOL/IOH
5
-15% of 0 Hour
PARAMETER
Spec Number
177
518833
Specifications HCS157MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
Group D
READ AND RECORD
ICC, IOL/H, IOZL/H
Subgroups 1, 2, 3, 9, 10, 11
NOTE:
1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE
GROUPS
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
Group E Subgroup 2
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC BURN-IN AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
16
-
-
-
1 - 3, 5, 6, 10, 11,
13 - 16
-
-
4, 7, 9, 12
16
2, 3, 5, 6, 10, 11,
13, 14
1
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
4, 7, 9, 12
1 - 3, 5, 6, 8, 10, 11,
13 - 15
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
4, 7, 9, 12
8
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
8, 15
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 680Ω ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
4, 7, 9, 12
8
1, 2, 3, 5, 6, 10, 11, 13 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
178
518833
HCS157MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
179
518833
HCS157MS
Propagation Delay Timing Diagram and
Load Circuit
Transition Timing Diagram
VOH
TTLH
TTHL
80%
VIH
VOL
INPUT
VS
20%
80%
20%
OUTPUT
VSS
TPLH
TPHL
VOLTAGE LEVELS
VOH
VS
PARAMETER
OUTPUT
VOL
TEST
POINT
DUT
CL
RL
HCS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
CL = 50pF
RL = 500Ω
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
180
518833
HCS157MS
Die Characteristics
DIE DIMENSIONS:
84 x 84 mils
METALLIZATION:
Type: SiAl
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
(15) E
(16) VCC
(1) S
(2) 1I0
HCS157MS
1I1 (3)
(14) 4I0
(13) 4I1
1Y (4)
(12) 4Y
2I0 (5)
(11) 3I0
2I1 (6)
3Y (9)
GND (8)
2Y (7)
(10) 3I1
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCS157 is TA14371A.
Spec Number
181
518833
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