DATASHEET

DATASHEET
Radiation Hardened Fast Sample and Hold
HS-2420EH
Features
The HS-2420EH is a radiation hardened monolithic circuit
consisting of a high performance operational amplifier with its
output in series with an ultra-low leakage analog switch and a
MOSFET input unity gain amplifier.
• Electrically screened to SMD #5962-95669
With an external hold capacitor connected to the switch
output, a versatile high performance sample-and-hold or
track-and-hold circuit is formed. When the switch is closed, the
device behaves as an operational amplifier and any of the
standard op amp feedback networks may be connected
around the device to control gain, frequency response, etc.
When the switch is opened, the output will remain at its last
level.
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling amplifiers.
• QML qualified per MIL-PRF-38535 requirements
• Maximum acquisition time
- 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs
- 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6µs
• Maximum drift current . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA
(maximum over-temperature)
• TTL compatible control input
• Power supply rejection . . . . . . . . . . . . . . . . . . . . . . . . . 80dB
• Radiation tolerance
- High dose rate (50 to 300rad(Si)/s) . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Only the EH device is wafer-by-wafer acceptance tested at
the low dose rate and guaranteed to 50krad(Si). The
100krad(Si) limit is established by characterization only.
• No latch-up
Applications
• Data acquisition systems
The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc.
• D to A deglitcher
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
• Auto zero systems
• Peak detector
• Gated op amp
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95669.
OFFSET
ADJUST
3
- INPUT
+ INPUT
1
-
+
V+
5
-
+
7
OUTPUT
2
14
SAMPLE/
HOLD
CONTROL
4
HS-2420EH
13
5
11
GND VHOLD
CAPACITOR
FIGURE 1. FUNCTIONAL DIAGRAM
March 17, 2015
FN8727.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HS-2420EH
HS-2420EH
14 LD METAL-SEALED SIDE-BRAZED CERAMIC DIP
MIL-STD-1835, CDIP2-T14
TOP VIEW
IN- 1
14 SAMPLE/HOLD
CONTROL
IN+ 2
13 GND
OFFSET ADJUST 3
12 NC
OFFSET ADJUST 4
11 HOLD CAPACITOR
V- 5
10 NC
NC 6
9 V+
OUTPUT 7
8 NC
Pin Descriptions
PIN #
PIN NAME
1
IN-
Inverting input to the operational amplifier
DESCRIPTION
2
IN+
Non-inverting input to the operational amplifier
3, 4
OFFSET ADJUST
Connect a 100kΩ potentiometer across these pins to null out the offset voltage.
5
V-
Negative power supply
6, 8, 10, 12
NC
No connect pin.
7
OUTPUT
9
V+
11
HOLD CAPACITOR
13
GND
14
SAMPLE/HOLD CONTROL
Output of the unity gain amplifier
Positive Power Supply
Connect the hold capacitor between this pin and GND.
Ground connection of the device
Control input to the series analog switch.
Ordering Information
ORDERING SMD NUMBER
(Note 1)
PART NUMBER
(Note 2)
TEMPERATURE RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962R9566902VCC
HS1B-2420EH-Q
-55 to +125
14 Ld SBDIP
D14.3
HS1B-2420EH/PROTO
HS1B-2420EH/PROTO
-55 to +125
14 Ld SBDIP
D14.3
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
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HS-2420EH
Test Circuits
ALL RESISTORS = 1%
ALL CAPACITORS = 10%
VDC
100kΩ
10kΩ
+VCC -VCC
2
S2
1
2
1
S7
S/H
A
-
1
S4
DUT
S7
1
50Ω
1
50Ω
2
1
S1
2
GND
+
1 OPEN
2
100kΩ
-
NULL
AMP
+
3
X1
X-1
S5
2
CH =
1000pF
S6
S3
BUFFER
2
1 50pF
2kΩ
3
+VCC
1MΩ
VAC
ILOAD
-
50Ω
+
AOUT
4
3
2
EOUT
S8
1
FIGURE 2. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION)
+5V
SINEWAVE
INPUT
IN2
IN1
IN3
IN4
IN5
IN6
IN7
IN8
A2
A1
EN
+15V
-15V
-
+
OUT
-
VOUT
DUT +
VOUT
DUT
2kΩ
VIN
-15V
+15V
2kΩ
50pF
CH =
1000pF
50Ω
S/H
50pF
CH =
1000pF
A0
SAMPLE/HOLD
CONTROL INPUT
NOTE: Compute Hold mode feedthrough attenuation from the formula:
 V OUT HOLD
FeedthroughAttenuation = 20 log  --------------------------------
 V IN HOLD 
Where VOUT HOLD = peak-to-peak value of output Sinewave during the
Hold mode.
FIGURE 3. HOLD MODE FEEDTHROUGH ATTENUATION
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NOTE: GBWP is the frequency of VINPUT at which:
 V OUT 
20 log  --------------------- = – 3dB
 V INPUT
FIGURE 4. GAIN BANDWIDTH PRODUCT
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HS-2420EH
Test Circuits
(Continued)
SEND SAMPLE
COMMAND
SET t2 TO 7µs
INITIALLY
FINE tACQ
MEASUREMENT LOOP
COURSE tACQ
MEASUREMENT LOOP
INCREMENT t2
BY 50ns
(50ns LONGER DELAY)
DIGITIZE V1
AT t1 (10µs)
DIGITIZE V2
AT t2
DECREMENT
t2 BY 50ns
DIGITIZE V1
AT t1 (10µs)
CALCULATE V1 - V2
IS V  0.01%?
YES
DIGITIZE V2
AT t2
NO
DECREMENT
t2 BY 50ns
YES
RECORD
tACQ
CALCULATE V1 - V2
IS V  0.01%?
NO
NOTE: See Test Diagram, Timing Diagram
FIGURE 5. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER)
t1
V1
V1 DIGITIZER
HS-2420EH
-
-
50pF
+10V
V2 DIGITIZER
2kΩ
V2
1000pF
0V
t1
OR
10µs
0V
-10V
COMPUTER
CONTROLLER
+
+
t2 DELAY
CONTROL
DELAY
S/H
CONTROL
t2
VARIABLE
DELAY
FIGURE 6. BLOCK DIAGRAM FOR ACQUISITION TIME MEASUREMENT
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HS-2420EH
Timing Waveforms
10V
VIN
(POS tACQ CASE)
0V
S/H CONTROL
0V
2V
0.01% OR 0.1%
ENVELOPE
10V
DUT OUTPUT
(POS tACQ CASE)
0V
t1  10µs
(t1 DIGITIZER COMMAND)
t1
t2
t2
(t2 DIGITIZER COMMAND)
FIGURE 7. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE)
+V
0V
VFINAL
VPEAK
90%
10%
INPUT
0V
-V
+OS, tR
10%
-OS, tF
90%
tR
FIGURE 8A.
VFINAL
VPEAK
tF
FIGURE 8B.
FIGURE 8. OVERSHOOT, RISE AND FALL TIME WAVEFORMS
+V
+V
+V
+V
75%
25%
25%
75%
INPUT
-V
-V
+SL
FIGURE 9A.
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-V
-SL
5
-V
t
t
FIGURE 9B.
FIGURE 9. SLEW RATE WAVEFORMS
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HS-2420EH
Typical Performance Curves
VSUPPLY = 15VDC , TA = +25°C, CH = 1000pF, Unless Otherwise Specified
1000
1000
LOWER 3dB FREQUENCY = 10Hz
DRIFT DURING HOLD
AT +25°C mV/s
OUTPUT NOISE
“HOLD” MODE
100
UNITY GAIN PHASE
MARGIN (°)
HOLD STEP
OFFSET
ERROR (mV)
1.0
UNITY GAIN
BANDWIDTH
(MHz)
MIN SAMPLE TIME
FOR 0.1% ACCURACY
10V SWINGS (ms)
0.1
0.01
10pF
100pF
mVRMS
10
100
EQUIV. INPUT NOISE
“SAMPLE” MODE - 100K
SOURCE RESISTANCE
10
EQUIV. INPUT NOISE
“SAMPLE” MODE - 0K
SOURCE RESISTANCE
SLEW RATE/
CHARGE RATE
V/(ms)
1000pF
0.01µF
0.1µF
1
10
1.0µF
100
1k
CH VALUE
FIGURE 10. TYPICAL SAMPLE AND HOLD PERFORMANCE vs
HOLDING CAPACITOR
100k
1M
FIGURE 11. BROADBAND NOISE CHARACTERISTICS
1000
OPEN LOOP VOLTAGE GAIN (dB)
100
ID (pA)
100
10
1
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
125
CH = 1000pF
60
40
CH = 1.0µF
20
CH = 0.1µF
0
-20
10
100
0
-40
-60
-70
-80
-90
1M
±10V SINUSOIDAL INPUT FREQUENCY (Hz)
FIGURE 14. HOLD MODE FEEDTHROUGH ATTENUATION
CH = 1000pF
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10M
OPEN LOOP PHASE ANGLE (°)
-50
100k
100k
1M
CH = 0.01µF
CH = 1000pF
40
10k
10k
10M
100M
FIGURE 13. OPEN LOOP FREQUENCY RESPONSE
20
1k
1k
FREQUENCY (Hz)
-30
100
CH = 0.01µF
CH = 100pF
80
FIGURE 12. DRIFT CURRENT vs TEMPERATURE
ATTENUATION (dB)
10k
BANDWIDTH
CH = 1.0µF
CH = 0.1µF
60
80
100
120
CH ≤ 100pF
140
160
180
200
220
240
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 15. OPEN LOOP PHASE RESPONSE
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HS-2420EH
Burn-in Circuit
Irradiation Circuit
HS-2420EH CERDIP
1
R1
-15V
C2
D2
S/H
CTL 14
-IN
2
+IN
3
4
OFFSET
NC 12
ADJ
OFFSET HOLD
ADJ
CAP 11
5
-V
6
7
GND 13
GND
+V
OUT
NC
14
2
13
3
12
4
11
5
10
6
9
7
8
GND
V2
NC 10
NC
1
R
+15V
9
D1
8
C1
NOTES:
NOTES:
R1 = 100kΩ ±5% (per socket)
C1 = C2 = 0.1µF (one per row) or 0.01µF (one per socket)
D1 = D2 = 1N4002 or equivalent (per board)
V1 = +15V
V2 = -15V
R = 100kΩ
HOLD STEP VOLTAGE (V)
S/H
CONTROL
+10
V+
CH
+5
-10
-5
+5
V1
+10
DC INPUT VOLTAGE (V)
-5
CH = 0.1µF
-10
-
+
-
+
CH = 10,000pF
CH = 1000pF
-15
HS-2420EH
-20
-25
-IN
-30
CH = 100pF
-35
FIGURE 16. HOLD STEP vs INPUT VOLTAGE
+IN
OUT
V-
100kΩ
OFFSET TRIM
(±25mV RANGE)
FIGURE 17. BASIC SAMPLE-AND-HOLD with OFFSET TRIM
INPUT
0.002RF
RF
OUTPUT
+IN
HS-2420EH
OUT
INPUT
-IN
RI
-IN
OUTPUT
RF
HS-2420EH
OUT
+IN
S/H
CONTROL
S/H
CONTROL
RI
S/H CONTROL
INPUT
0.002RI
S/H CONTROL
INPUT
GAIN ~
-RF
RI
FIGURE 18. INVERTING CONFIGURATION with GAIN ADJUST
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GAIN ~ I +
-RF
RI
FIGURE 19. NONINVERTING CONFIGURATION WITH GAIN ADJUST
FN8727.0
March 17, 2015
HS-2420EH
Offset and Gain Adjustment
Offset Adjustment
The offset voltage of the HS-2420EH may be adjusted using a
100kΩ trim pot, as shown in Figure 17. The recommended
adjustment procedure is:
1. Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
2. Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold.
Figures 18 and 19 illustrate how to implement gain error
adjust on the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a -10V
output.
Measure the output hold voltage (V-10 NOMINAL). Adjust the
trim pot for an output hold voltage of:
 V-10 NOMINAL  +  – 10V 
----------------------------------------------------------------------2
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HS-2420EH
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
TRANSISTOR COUNT:
97mils x 61mils x 19mils
78
METALLIZATION:
PROCESS:
Type: Al
Thickness: 16kÅ  2kÅ
Bipolar-Di
GLASSIVATION:
Type: Silox
Thickness: 14kÅ  2kÅ
Metallization Mask Layout
HS-2420EH
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HS-2420EH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
March 17, 2015
FN8727.0
CHANGE
Initial Release
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
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HS-2420EH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
LEAD FINISH
c1
-A-
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
(c)
SECTION A-A
D S
D
BASE
PLANE
Q
S2
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
eA/2
c
aaa M C A - B S D S
ccc M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip
or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.
5. Dimension Q shall be measured from the seating plane to the base
plane.
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
-
E
0.220
0.310
5.59
e
0.100 BSC
-
7.87
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7

90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
N
14
0.038
14
2
8
Rev. 0 4/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
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