DATASHEET

ACTS08MS
Radiation Hardened
Quad 2-Input AND Gate
April 1995
Features
Pinouts
• 1.25 Micron Radiation Hardened SOS CMOS
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
A1 1
14 VCC
B1 2
13 B4
Y1 3
12 A4
• Latch-Up Free Under Any Conditions
A2 4
11 Y4
• Military Temperature Range: -55oC to +125oC
B2 5
10 B3
• Significant Power Reduction Compared to ALSTTL Logic
Y2 6
9 A3
GND 7
8 Y3
2
• SEU LET Threshold >80 MEV-cm /mg
11
• Dose Rate Upset >10
RAD (Si)/s, 20ns Pulse
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
14 LEAD CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
- VIH = VCC/2 Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ACTS08MS is a radiation hardened quad 2-Input
AND Gate. A high on both inputs forces the output to a high
logic level.
The ACTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of a
radiation hardened, high-speed, CMOS/SOS Logic Family.
A1
1
14
VCC
B1
2
13
B4
Y1
3
12
A4
A2
4
11
Y4
B2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
Ordering Information
PART NUMBER
TEMPERATURE RANGE
ACTS08DMSR
-55oC
ACTS08KMSR
-55oC
SCREENING LEVEL
PACKAGE
to
+125oC
Intersil Class S Equivalent
14 Lead SBDIP
to
+125oC
Intersil Class S Equivalent
14 Lead Ceramic Flatpack
ACTS08D/Sample
+25oC
Sample
14 Lead SBDIP
ACTS08K/Sample
+25oC
Sample
14 Lead Ceramic Flatpack
ACTS08HMSR
+25oC
Die
Die
Functional Diagram
Truth Table
INPUTS
(1, 4, 9, 12)
An
OUTPUT
An
Bn
Yn
L
L
L
L
H
L
H
L
L
H
H
H
(3, 6, 8, 11)
Yn
(2, 5, 10, 13)
Bn
NOTE: L = Logic Level Low, H = Logic Level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
518851
File Number 3994
Spec Number
Specifications ACTS08MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±50mA
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
(All voltages reference to VSS)
Thermal Impedance
θJA
θJC
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74oC/W
24oC/W
Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . 116oC/W 30oC/W
Maximum Package Power Dissipation at +125oC
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4W
Maximum Device Power Dissipation. . . . . . . . . . . . . . . . . . .(TBD)W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Gates
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . VCC to VCC/2V
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . 10ns/ V Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Delta ICC
(NOTE 1)
CONDITIONS
SYMBOL
ICC
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
5
µA
-
100
µA
-
1.6
mA
-12
-
mA
-8
-
mA
12
-
mA
8
-
mA
VCC = 5.5V,
VIN = VCC or GND
2, 3
DICC
VCC = 5.5V
VIN = VCC or GND
1 Input = 3.4V
1, 2, 3
Output Current
(Source)
IOH
VCC = VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V (Note 2)
1
Output Current
(Sink)
IOL
Output Voltage High
VOH
Output Voltage Low
Input Leakage
Current
Noise Immunity
Functional Test
VOL
IIN
FN
2, 3
VCC = VIH = 4.5V,
VOUT = 0.4V,
VIL = 0V (Note 2)
LIMITS
+125oC,
+25oC,
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
1
2, 3
-55oC
+125oC,
-55oC
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1
-
V
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1
-
V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1
+25oC
-
±0.5
µA
-
±1.0
µA
-
-
V
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 3)
2, 3
7, 8A, 8B
+125oC,
+25oC,
-55oC
+125oC,
-55oC
NOTE:
1. All voltages reference to device GND.
2. Force/measure functions may be interchanged.
3. Per functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.
Spec Number
2
518851
Specifications ACTS08MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
Propagation Delay
Input to Output
TPHL
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
13
ns
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
TPLH
10, 11
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
LIMITS
+125oC,
-55oC
2
15
ns
9
+25oC
2
14
ns
10, 11
+125oC, -55oC
2
15
ns
NOTES:
1. All voltages referenced to device GND.
2. Measurements made with RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
CIN
CONDITIONS
NOTE
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
TEMP
o
MIN
TYP
MAX
UNITS
1
+25 C
-
TBD
-
pF
1
+125oC
-
TBD
-
pF
1
+25oC
-
-
10
pF
1
+125oC
-
-
10
pF
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
ICC
RAD LIMITS
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
VCC = 5.5V, VIN = VCC or GND
+25oC
-
100
µA
-
1.6
mA
Delta ICC
ICC
VCC - 5.5V, VIN = VCC or GND
1 Input = 3.4V
+25oC
Output Current (Source)
IOH
VCC = VIH = 4.5V, VIL = 0,
VOUT = VCC -0.4V
+25oC
-8
-
mA
Output Current (Sink)
IOL
VCC = VIH = 4.5V, VIL = 0,
VOUT = 0.4V
+25oC
8
-
mA
Output Voltage High
VOH
VCC = 5.5V, VIH = 2.75V,
VIL = 0.80V, IOH = -50µA
+25oC
VCC -0.1
-
V
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V, IOH = -50µA
+25oC
VCC -0.1
-
V
VCC = 5.5V, VIH = 2.75V,
VIL = 0.80V, IOH = 50µA
+25oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V, IOH = 50µA
+25oC
-
0.1
V
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±1
µA
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V (Note 2)
+25oC
-
-
V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
15
ns
Output Voltage Low
Input Leakage Current
Noise Immunity
Functional Test
Propagation Delay
Input to Output
VOL
IIN
FN
TPHL,
TPLH
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.
Spec Number
3
518851
Specifications ACTS08MS
TABLE 5. DELTA PARAMETERS (+25oC)
PARAMETER
SYMBOL
(NOTE 1)
DELTA LIMIT
UNITS
Supply Current
ICC
±1.0
µA
Output Current
IOL/IOH
±15
%
NOTE:
1. All delta calculations are referenced to 0 hour readings or pre-life readings.
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
Interim Test 1 (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test 2 (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test 3 (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
ICC, IOL/H
ICC, IOL/H
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
READ AND RECORD
Group D
Subgroups 1, 2, 3, 9, 10, 11
NOTE:
1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE GROUP
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
Group E Subgroup 2
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. BURN-IN TEST CONNECTIONS (+125oC < TA < 139oC)
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ±0.5V
VCC = 6V ±0.5V
50kHz
25kHz
3, 6, 8, 11
14
-
-
3, 6, 8, 11
1, 2, 4, 5, 9, 10, 12, 13, 14
-
-
14
1, 2, 4, 5, 9, 10, 12, 13
-
STATIC BURN-IN I (Note 1)
-
1, 2, 4, 5, 7, 9, 10,
12, 13
STATIC BURN-IN II (Note 1)
-
7
DYNAMIC BURN-IN TEST CONNECTIONS (Note 1)
-
7
3, 6, 8, 11
NOTE:
1. Each pin except VCC and GND will have a series resistor of 500Ω ±5%.
TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25oC, ±5oC)
FUNCTION
Irradiation Circuit (Note 1)
OPEN
GROUND
VCC = 5V ±0.5V
3, 6, 8, 11
7
1, 2, 4, 5, 9, 10, 11, 12, 13, 14
NOTE:
1. Each pin except VCC and GND will have a series resistor of 47kΩ ±5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
Spec Number
4
518851
Specifications ACTS08MS
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM)
100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Interim Electrical Test 2 (Note 1)
100% Nondestructive Bond Pull Method 2023
100% Dynamic Burn-In Method 1015, 240 Hours at +125oC
or 180 Hours at +135oC
100% Internal Visual Inspection Method 2010
100% Interim Electrical Test 3 (Note 1)
100% Temperature Cycling Method 1010 Condition C
(-65o to +150oC)
100% Final Electrical Test
100% Constant Acceleration
100% Radiographics Method 2012 (2 Views)
100% PIND Testing
100% External Visual Method 2009
100% External Visual Inspection
Group A (All Tests) Method 5005 (Class S)
100% Serialization
Group B (Optional) Method 5005 (Class S) (Note 2)
100% Initial Electrical Test
Group D (Optional) Method 5005 (Class S) (Note 2)
100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min
CSI and/or GSI (Optional) (Note 2)
100% Interim Electrical Test 1 (Note 1)
Data Package Generation (Note 3)
100% Fine and Gross Seal Method 1014
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
Propagation Delay Timing Diagram and Load Circuit
DUT
VIH
VS
TEST
POINT
RL
500Ω
CL
50pF
INPUT
VSS
TPLH
TPHL
VOH
VS
OUTPUT
AC VOLTAGE LEVELS
VOL
PARAMETER
ACTS
UNITS
VCC
4.50
V
VIH
3.00
V
VS
1.30
V
VIL
0
V
GND
0
V
Spec Number
5
518851
ACTS08MS
Die Characteristics
DIE ATTACH:
Material: Silver Glass or JM 7000 Polymer after 7/1/95
DIE DIMENSIONS:
88 mils x 88 mils
2.24mm x 2.24mm
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
METALLIZATION:
Type: AlSiCu
Metal 1 Thickness: 6.75kÅ (Min), 8.25kÅ (Max)
Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max)
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
ACTS08MS
B1
(2)
A1
(1)
VCC
(14)
B4
(13)
Y1 (3)
(12) A4
A2 (4)
(11) Y4
NC
NC
(10) B3
B2 (5)
(6)
(7)
(8)
(9)
Y2
GND
Y3
A3
Spec Number
6
518851
ACTS08MS
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
-A-
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
LEAD FINISH
c1
-D-
BASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
INCHES
(c)
SECTION A-A
D S
D
BASE
PLANE
S2
Q
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
ccc M C A - B S D S
eA/2
c
aaa M C A - B S D S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
MILLIMETERS
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
M
-
0.0015
-
0.038
2
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
N
14
14
8
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
Spec Number
7
518851
ACTS08MS
Ceramic Metal Seal Flatpack Packages (Flatpack)
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
e
A
INCHES
PIN NO. 1
ID AREA
-A-
D
-B-
S1
b
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
E1
0.004 M
H A-B S
0.036 M
D S
H A-B S
D S
C
Q
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
(c)
b1
M
M
-
0.390
-
9.91
3
E
0.235
0.260
5.97
6.60
-
E1
-
0.290
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
e
LEAD FINISH
BASE
METAL
D
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.270
0.370
6.86
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
(b)
0.050 BSC
14
14
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
8
518851
Similar pages