DATASHEET

CD4073BMS, CD4081BMS
CD4082BMS
CMOS AND Gate
October 2015
Features
Pinout
• High-Voltage Types (20V Rating)
CD4073BMS
TOP VIEW
• CD4073BMS Triple 3-Input AND Gate (No longer
available or supported)
• CD4081BMS Quad 2-Input AND Gate
A 1
14 VDD
• CD4082BMS Dual 4-Input AND Gate (No longer
available or supported)
B 2
13 GRTE
PO
UP H
S12
D 3
• Medium Speed Operation:
- tPLH, tPHL = 60ns (typ) at VDD = 10V
E 4
F 5
ER
NG
LO
K = D NO
EF 6
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
A
AV
E
BL
IL A
OR
11 I
10 L = G  H  I
9 J=ABC
8 C
VSS 7
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
D
CD4081BMS
TOP VIEW
• Standardized Symmetrical Output Characteristics
A 1
14 VDD
• 5V, 10V and 15V Parametric Ratings
B 2
13 H
J=AB 3
12 G
K=CD 4
11 M = G H
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4073BMS, CD4081BMS and CD4082BMS AND gates
provide the system designer with direct implementation of
the AND function and supplement the existing family of
CMOS gates.
C 5
10 L = E  F
D 6
9 F
VSS 7
8 E
CD4082BMS
TOP VIEW
The CD4073BMS, CD4081BMS and CD4082BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP
*H4Q
Frit Seal DIP
*H1B
Ceramic Flatpack
*H3W
*CD4073B, CD4081B
J=ABCD 1
†H4H
14 VDD
13 K = ED F  G  H
TE
OR
12PPH
SU
D 2
C 3
B 4
†CD4082B
A 5 AVA
R
GE
ON 6
LNC
NO
VSS 7
E
BL
IL A
OR 11 G
10 F
9 E
8 NC
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999, 2015
7-433
File Number
3324
CD4073BMS, CD4081BMS, CD4082BMS
Functional Diagram
VDD
14
A
B
C
D
1
9
2
4
6
5
F
11
I
12
H
13
G
10
E
J
8
3
K
L
7
VSS
CD4073BMS
VDD
14
1
2
3
5
6
4
8
9
10
12
13
11
A
B
C
D
E
F
G
H
J
K
L
M
7
VSS
CD4081BMS
VDD
14
D
C
B
A
2
3
1
4
5
9
E
10
F
11
G
12
H
13
7
VSS
CD4082BMS
7-434
J
K
Specifications CD4073BMS, CD4081BMS, CD4082BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input  10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm  0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
Input Leakage Current
SYMBOL
IDD
IIL
IIH
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
.5
A
o
2
+125 C
-
50
A
VDD = 18V, VIN = VDD or GND
3
-55oC
-
.5
A
VIN = VDD or GND
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
VDD = 18V
3
-55oC
-100
-
nA
VDD = 20
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
-
100
nA
-
50
mV
VIN = VDD or GND
VDD = 20
VDD = 18V
-55oC
3
oC,
+125oC,
-55oC
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
oC
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
o
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25 C
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10A
1
+25oC
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10A
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
Functional
F
o
VDD = 20V, VIN = VDD or GND
7
+25 C
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-435
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Transition Time
SYMBOL
TPHL
TPLH
TTHL
TTLH
CONDITIONS (NOTES 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
10, 11
VDD = 5V, VIN = VDD or GND
+25oC
9
+125
-55oC
+25oC
9
10, 11
oC,
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
250
ns
-
338
ns
-
200
ns
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
-55oC, +25oC
-
.25
A
-
7.5
A
+125
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
oC,
oC
+25oC
-
.5
A
+125oC
-
15
A
oC,
-
.5
A
-55
-55
+25oC
o
+125 C
-
30
A
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
0.64
-
mA
0.9
-
mA
1.6
-
mA
-55
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125oC
-55
Output Current (Sink)
Output Current (Source)
IOL15
IOH5A
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-
-0.64
mA
-
-1.15
mA
-
-2.0
mA
-
-0.9
mA
-
-2.6
mA
oC
+125oC
-55
Output Current (Source)
oC
+125
-55
Output Current (Source)
oC
oC
+125oC
o
-55 C
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
oC
-
-2.4
mA
-55oC
-
-4.2
mA
+125
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
7
-
V
Propagation Delay
TPHL
TPLH
1, 2, 3
+25oC
-
120
ns
1, 2, 3
oC
-
90
ns
VDD = 10V
VDD = 15V
7-436
+25
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Transition Time
TTHL
TTLH
Input Capacitance
CONDITIONS
VDD = 10V
VDD = 15V
CIN
Any Input
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
-
100
ns
o
1, 2, 3
+25 C
-
80
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
VTN
P Threshold Voltage
VTP
VTP
P Threshold Voltage
Delta
Functional
F
CONDITIONS
NOTES
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10A
TEMPERATURE
o
-
2.5
A
1, 4
+25
oC
-2.8
-0.2
V
oC
-
1
V
0.2
2.8
V
-
1
V
+25
VSS = 0V, IDD = 10A
1, 4
+25oC
1, 4
oC
+25
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
UNITS
+25 C
1, 4
VDD = 18V, VIN = VDD or GND
MAX
1, 4
VDD = 10V, ISS = -10A
VSS = 0V, IDD = 10A
MIN
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - SSI
IDD
0.1A
Output Current (Sink)
IOL5
 20% x Pre-Test Reading
IOH5A
 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
7-437
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
Group B
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V  -0.5V
50kHz
6, 9, 10
1, 5, 8, 11 - 13
3, 4, 10, 11
1, 2, 5, 6, 8, 9, 12,
13
1, 3
2 - 5, 9 - 12
25kHz
PART NUMBER CD4073BMS
Static Burn-In 1
Note 1
6, 9, 10
1 - 5, 7, 8, 11 - 13
14
Static Burn-In 2
Note 1
6, 9, 10
7
1 - 5, 8, 11 - 14
Dynamic BurnIn Note 1
-
7
14
6, 9, 10
7
1 - 5, 8, 11 - 14
Irradiation
Note 2
PART NUMBER CD4081BMS
Static Burn-In 1
Note 1
3, 4, 10, 11
1, 2, 5 - 9, 12, 13
14
Static Burn-In 2
Note 1
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9,
12 - 14
Dynamic BurnIn Note 1
-
7
14
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9,
12 - 14
Irradiation
Note 2
PART NUMBER CD4082BMS
Static Burn-In 1
Note 1
1, 6, 8, 13
2 - 5, 7, 9 - 12
14
Static Burn-In 2
Note 1
1, 6, 8, 13
7
2 - 5, 9 - 12, 14
Dynamic BurnIn Note 1
6, 8
7
14
1, 6, 8, 13
7
2 - 5, 9 - 12, 14
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V  0.5V
7-438
CD4073BMS, CD4081BMS, CD4082BMS
VDD
8 (5, 11)
1 (4, 12)
2 (3, 13)
p
*
p
n
*
p
p
n
*
p
p
p
n
n
p
VDD
9 (6, 10)
n
n
n
n
VSS
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)
A
1 (4, 12)
J
B
2 (3, 13)
9 (6, 10)
C
8 (5, 11)
FIGURE 2. LOGIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)
VDD
VDD
p
*
p
2 (5, 9, 12)
p
n
p
*
p
VSS
p
n
1 (6, 8, 13)
n
n
3 (4, 10, 11)
n
*
n
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 3. SCHEMATIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)
A
1 (6, 8, 13)
J
B
3 (4, 10, 11)
2 (5, 9, 12)
FIGURE 4. LOGIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)
7-439
CD4073BMS, CD4081BMS, CD4082BMS
p
3 (11)
VDD
*
p
n
p
p
2 (12)
*
p
p
p
n
n
n
n
n
n
VSS
p
4 (10)
5 (9)
VDD
*
VSS
p
n
VDD
p
*
p
n
n
*
n
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 5. SCHEMATIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)
D
2 (12)
C
3 (11)
J
B
1 (13)
4 (10)
A
5 (9)
FIGURE 6. LOGIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)
Typical Performance Characteristics
20
PROPAGATION DELAY TIME (TPHL, THLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT VOLTAGE (VO) (V)
SUPPLY VOLTAGE (VDD) = 15V
15
10V
10
5V
5
0
5
10
15
20
25
200
175
150
SUPPLY VOLTAGE (VDD) = 15V
125
100
10V
75
50
5V
25
0
INPUT VOLTAGE (VIN) (V)
AMBIENT TEMPERATURE (TA) = +25oC
10
20
30
40
50
60
70
80
90
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
FIGURE 7. TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS
7-440
100
CD4073BMS, CD4081BMS, CD4082BMS
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
15
5V
0
5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
-5
-10V
POWER DISSIPATION PER GATE (PD) (W)
TRANSITION TIME (tTHL, tTLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V
100
10V
5V
8
6
4
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
2
104
10
3
8
6
4
10V
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
10V
5V
2
8
6
4
2
102
8
6
4
CL = 50pF
2
CL = 15pF
10
20
-15
FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
200
0
0
-10
-15V
105
50
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
AMBIENT TEMPERATURE (TA) = +25oC
150
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
2
1
4 68
2
4 6 8
2
4 6 8
103
10
102
INPUT FREQUENCY (fI) (kHz)
2
4 6 8
104
FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONPER
GATE AS A FUNCTION OF FREQUENCY
7-441
CD4073BMS, CD4081BMS, CD4082BMS
Chip Dimensions and Pad Layouts
CD4081BMS
CD4082BMS
CD4073BMS
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ 14kÅ,
AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9001 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
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