DATASHEET

ACS541MS
Radiation Hardened Octal Buffer/
Line Driver Three-State
January 1996
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96710 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
OE1
1
20 VCC
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
A0
2
19 OE2
A1
3
18 Y0
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm /mg
A2
4
17 Y1
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
A3
5
16 Y2
A4
6
15 Y3
• Latch-Up Free Under Any Conditions
A5
7
14 Y4
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
A6
8
13 Y5
• Significant Power Reduction Compared to ALSTTL Logic
A7
9
12 Y6
GND 10
11 Y7
2
12
• Dose Rate Survivability . . . . . . . . . . . >10
RAD (Si)/s, 20ns Pulse
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
Description
The Intersil ACS541MS is a Radiation Hardened Octal Buffer/Line
Driver, with three-state outputs. The output enable pins OE1, OE2 control the Three-State outputs. If either enable is high the output will be in a
high impedance state. For data output both enables must be low.
The ACS541MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS541MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line package (D suffix).
OE1
1
20
VCC
A0
2
19
OE2
A1
3
18
Y0
A2
4
17
Y1
A3
5
16
Y2
A4
6
15
Y3
A5
7
14
Y4
A6
8
13
Y5
A7
9
12
Y6
10
11
Y7
GND
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671001VRC
-55oC to +125oC
MIL-PRF-38535 Class V
20 Lead SBDIP
5962F9671001VXC
-55oC to +125oC
MIL-PRF-38535 Class V
20 Lead Ceramic Flatpack
ACS541D/Sample
25oC
Sample
20 Lead SBDIP
ACS541K/Sample
25oC
Sample
20 Lead Ceramic Flatpack
ACS541HMSR
25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
518856
File Number 4085
Spec Number
ACS541MS
Functional Diagram
VCC
2
18
A0
OE1
OE2
Y0
1
GND
VCC
19
3
17
A1
Y1
GND
VCC
4
16
A2
Y2
GND
VCC
5
15
A3
Y3
GND
VCC
6
14
A4
Y4
GND
VCC
7
13
A5
Y5
GND
VCC
8
12
A6
Y6
GND
VCC
9
GND VCC
A7
11
Y7
10
20
GND
TRUTH TABLE
INPUTS
OUTPUTS
OE1
OE2
An
Yn
L
L
H
H
L
L
L
L
H
X
X
Z
X
H
X
Z
NOTE: L = Low Logic Level, H = High Logic Level, Z = High Impedance
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
2
518856
ACS541MS
Die Characteristics
DIE DIMENSIONS:
102 mils x 102 mils
2,600mm x 2,600mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105 A/cm2
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
Metallization Mask Layout
(18) YO
(19) OE2
(20) VCC
(1) OE1
(2) A0
(3) A1
ACS541MS
A2 (4)
(17) Y1
A3 (5)
(16) Y2
NC
NC
NC
NC
Y5 (13)
GND (10)
Y6 (12)
(14) Y4
Y7 (11)
A5 (7)
A7 (9)
(15) Y3
A6 (8)
A4 (6)
Spec Number
3
518856
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