DATASHEET

CD4017BMS, CD4022BMS
Data Sheet
CMOS Counter/Dividers
August 1998
File Number
3297
Features
• High Voltage Types (20V Rating)
CD4017BMS - Decade Counter with 10 Decoded Outputs
CD4022BMS - Octal Counter with 8 Decoded Outputs
CD4017BMS and CD4022BMS are 5-stage and 4-stage
Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT
signal. Schmitt trigger action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock input pulse rise and fall
times.
These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. A high RESET signal clears the counter to
its zero count. Use of the Johnson counter configuration permits
high speed operation, 2-input decode gating and spike-free
decoded outputs. Anti-lock gating is provided, thus assuring
proper counter sequence. The decoded output are normally low
and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A CARRYOUT signal completes one cycle every 10 clock input cycles in
the CD4017BMS or every 8 clock input cycles in the
CD4022BMS and is used to ripple-clock the succeeding device
in a multi-device counting chain.
The CD4017BMS and CD4022BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4017B Only
• Fully Static Operation
• Medium-Speed Operation 10MHz (Typ) at VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
Number 13A, “Standard Specifications for Description
of ‘B’ Series CMOS Devices”
Applications
• Decade Counter/Decimal Decode Display (CD4017BMS)
• Binary Counter/Decoder
• Frequency Division
• Counter Control/Timers
• Divide-by-N Counting
• For Further Application Information, See ICAN-6166
“COS/MOS MSI Counter and Register Design and
Applications”
Pinouts
CD4017BMS
TOP VIEW
*H4W †H4X
*H1F
†H1E
H6W
† CD4022B Only
Functional Diagrams
CD4017BMS
CLOCK
CLOCK INHIBIT
RESET
14
13
15
3
2
4
7
10
1
5
6
9
11
12
VCC = 16
VSS = 8
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7”
“8”
“9”
DECODED
DECIMAL
OUT
NC = NO
CONNECTION
14
13
15
2
1
3
7
11
4
5
10
12
CARRY OUT
VCC = 16
VSS = 8
1
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7”
16 VDD
1 2
15 RESET
0 3
14 CLOCK
2 4
13 CLOCK INHIBIT
6 5
12 CARRY OUT
7 6
11 9
3 7
10 4
VSS 8
9 8
CD4022BMS
TOP VIEW
CD4022BMS
CLOCK
CLOCK INHIBIT
RESET
5 1
DECODED
OUT
CARRY OUT
NC = NO
CONNECTION
1 1
16 VDD
0 2
15 RESET
2 3
14 CLOCK
5 4
13 CLOCK INHIBIT
6 5
12 CARRY OUT
NC 6
11 4
3 7
10 7
VSS 8
9 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4017BMS, CD4022BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance. . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . .
80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . .
70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
VOL15
VDD = 15V, No Load
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1, 2, 3
+25oC, +125oC, -55oC
-
50
mV
1, 2, 3
+25oC, +125oC, -55oC
14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
-2.8
-0.7
V
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
P Threshold Voltage
Functional
VPTH
F
VSS = 0V, IDD = 10µA
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented.
2. Go/No Go test with limits applied to inputs
2
3. For accuracy, voltage is measured differentially to VDD. Limit is
0.050V max.
CD4017BMS, CD4022BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock to Decode Out
SYMBOL
TPHL1
TPLH1
CONDITIONS (Note 1, 2)
VDD = 5V, VIN = VDD or GND
Propagation Delay
Clock to Carry Out
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
Propagation Delay
Reset to Out
TPHL3
TPLH3
VDD = 5V, VIN = VDD or GND
Transition Time
Maximum Clock Input Frequency
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
FCL
VDD = 5V, VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
-
650
ns
10, 11
+125oC, -55oC
-
878
ns
9
+25oC
-
600
ns
10, 11
+125oC, -55oC
-
810
ns
9
+25oC
-
530
ns
10, 11
+125oC, -55oC
-
716
ns
9
+25oC
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
9
+25oC
2.5
-
MHz
10, 11
+125oC, -55oC
1.85
-
MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
-55oC, +25oC
-
5
µA
+125oC
-
150
µA
-55oC, +25oC
-
10
µA
+125oC
-
300
µA
-55oC, +25oC
-
10
µA
+125oC
1, 2
1, 2
-
600
µA
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC, 55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC, 55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC, 55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC, 55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125oC
2.4
-
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC, 55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC, 55oC
7
-
V
3
CD4017BMS, CD4022BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
MAX
UNITS
Propagation Delay Clock
to Decode Out
TPHL1
TPLH1
VDD = 10V
1, 2, 3
+25oC
-
270
ns
VDD = 15V
1, 2, 3
+25oC
-
170
ns
Propagation Delay Clock
to Carry Out
TPHL2
TPLH2
VDD = 10V
1, 2, 3
+25oC
-
250
ns
VDD = 15V
1, 2, 3
+25oC
-
160
ns
Propagation Delay Reset
to out
Transition Time
Maximum Clock Input Frequency
SYMBOL
TEMPERATURE
MIN
TPHL3
TPLH3
VDD = 10V
1, 2, 3
-
230
ns
VDD = 15V
1, 2, 3
+25oC
-
170
ns
TTHL
TTLH
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
FCL
VDD = 10V
1, 2, 3
+25oC
5.0
-
MHz
VDD = 15V
1, 2, 3
+25oC
5.5
-
MHz
VDD = 5V
1, 2, 3
+25oC
-
230
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
70
ns
VDD = 5V
1, 2, 3
+25oC
-
260
ns
VDD = 10V
1, 2, 3
+25oC
-
110
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
VDD = 5V
1, 2, 3
+25oC
-
200
ns
VDD = 10V
1, 2, 3
+25oC
-
90
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
1, 2
+25oC
-
7.5
pF
TS
Minimum Reset Pulse
Width
TW
Input Capacitance
NOTES
+25oC
Minimum Setup Time
Clock Inhibit to Clock
Setup
Minimum Clock Pulse
Width
CONDITIONS
TW
CIN
Any Input
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
-
25
µA
N Threshold Voltage
VTN
VDD = 10V, ISS = -10µA
1, 4
+25oC
-2.8
-0.7
V
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
4
CD4017BMS, CD4022BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
CONFORMANCE GROUP
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
1, 7, 9
1, 7, 9, Deltas
IDD, IOL5, IOH5A
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group A
Group B
100% 5004
100% 5004
Group D
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
PART NUMBER CD4017BMS AND CD4002B
Static Burn-In 1
1 - 7, 9 - 12
8, 13, 15
Note 1
Static Burn-In 2
1 - 7, 9 - 12
8, 14
Note 1
Dynamic Burn8, 13, 15
In Note 1
Irradiation
1 - 7, 9 - 12
8
Note 2
NOTE:
VDD
9V ± -0.5V
50kHz
25kHz
14, 16
-
-
-
13, 15, 16
-
-
-
16
1 - 7, 9 - 12
14
-
13 - 16
-
-
-
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ±
0.5V
5
CD4017BMS, CD4022BMS
Logic Diagram
0
1
2
3
4
5
6
7
8
9
CARRY
OUT
3
2
4
7
10
1
5
6
9
11
12
D
Q1
D
Q2
D
Q3
D
Q4
D
Q5
C
Q1
C
Q2
C
Q3
C
Q4
C
Q5
R
R
R
R
R
*RESET
15
VDD
*CLOCK
14
13
*CLOCK INHIBIT
VSS
* All Inputs Protected by CMOS Protection Network
FIGURE 1. CD4017BMS
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
6
CD4017BMS, CD4022BMS
Logic Diagram
(Continued)
0
1
2
3
4
5
6
7
CARRY
OUT
2
1
3
7
11
4
5
10
12
D
Q1
D
Q2
D
Q3
D
Q4
C
Q1
C
Q2
C
Q3
C
Q4
R
R
R
R
*RESET
15
VDD
*CLOCK
14
13
* All Inputs Protected by CMOS Protection Network
*CLOCK
VSS
INHIBIT
FIGURE 2. CD4022BMS
Timing Diagram
CLOCK
CLOCK
RESET
CLOCK
INHIBIT
“0”
RESET
CLOCK
INHIBIT
“1”
“2”
“3”
“4”
“5”
0
0
1
“0”
1
2
“1”
0
0
1
0
1
2
“2”
3
“3”
4
5
“4”
6
“6”
“7”
“5”
2
2
3
3
4
4
5
5
7
“8”
“6”
8
“9”
CARRY
OUT
9
“7”
6
6
7
CARRY
OUT
FIGURE 3. CD4017BMS
7
FIGURE4. CD4022BMS
7
CD4017BMS, CD4022BMS
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
12.5
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-15V
-30
FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
50
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
8
5
2.5
5V
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-5
-10V
10V
7.5
FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
10
0
FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
TRANSITION TIME (tTHL, tTLH) (ns)
15
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-15V
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 8. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
700
600
500
SUPPLY VOLTAGE (VDD) = 5V
400
300
10V
200
100
15V
0
10
20
30
40
50
60
70
80
LOAD CAPACITANCE (CL) (pF)
90
100
FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (CLOCK TO
DECODE OUTPUT)
CD4017BMS, CD4022BMS
(Continued)
105
AMBIENT TEMPERATURE (TA) = +25oC
700
POWER DISSIPATION (PD) (µW)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
Typical Performance Characteristics
600
500
SUPPLY VOLTAGE (VDD) = 5V
400
300
10V
200
LOAD CAPACITANCE
CL = 50pF
CL = 15pF
104
SUPPLY VOLTAGE
(VDD) = 15V
10V
5V
102
AMBIENT TEMPERATURE (TA) = +25oC
INPUT tr = tf = 20ns
100
15V
0
10
20
30
40
50
60
70
80
LOAD CAPACITANCE (CL) (pF)
90
10V
103
10
1
100
102
10
103
104
105
CLOCK INPUT FREQUENCY (fCL) (kHz)
FIGURE 11. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
(CLOCK TO CARRY OUT)
FIGURE 12. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF CLOCK INPUT FREQUENCY
COUT FOR N ≥ 6
f = CLOCK ÷ N
CLOCK
CLOCK
CD4017BMS
OR
CD4022BMS
CLOCK
INHIBIT
TS
CLOCK
INHIBIT
0
1
2
...
N
RESET
TPHL
TPLH
DECODE
1-9
OUTPUT
DECODE
“0” OR
CARRY
OUTPUT
N DECODED O DECODED
OUTPUTS
OUTPUTS
TPRHL
ALTERNATE COUT
FOR N = 2 TO 10
f = CLOCK ÷ N
TPRLH
TPHL
Delays Measured Between 50% levels on All Waveforms
FIGURE 14. DIVIDE BY N COUNTER (N ≤ 10) WITH N DECODED
OUTPUTS
FIGURE 13. PROPAGATION DELAY, SETUP, AND RESET
REMOVAL TIME WAVEFORMS
C
R
C
R
C
R
CE CD4017BMS
CE CD4017BMS
CE CD4017BMS
Q0 Q1 . . . Q8 Q9
Q0 Q1 . . . Q8 Q9
Q0 Q1 . . . Q8 Q9
8 DECODED
OUTPUTS
9 DECODED
OUTPUTS
8 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGE
LAST STAGE
FIGURE 15. CASCADING THE CD4017BMS
When the Nth decoded output is reached (Nth clock pulse) the
S-R flip-flop (constructed from two NOR gates of the CD4001B)
generates a reset pulse which clears the CD4017BMS or
CD4022BMS to its zero count. At this time, if the Nth decoded
output is greater than or equal to 6 in the CD4017BMS or 5 in
the CD4022BMS, the COUT line goes high to clock the next
CD4017BMS or CD4022BMS counter section. The “0”
9
decoded output also goes high at this time. Coincidence of the
clock low and decoded “0” output low resets the S-R flip-flop to
enable the CD4017BMS or CD4022BMS. If the Nth decoded
output is less than 6 (CD4017BMS) or 5 (CD4022BMS), the
COUT line will not go high and, therefore, cannot be used. In
this case “0” decoded output may be used to perform the clocking function for the next counter.
CD4017BMS, CD4022BMS
Chip Dimensions and Pad Layouts
CD4017BMSH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
CD4022BMSH
METALLIZATION:
PASSIVATION:
BOND PADS:
Thickness: 11kÅ − 14kÅ,
10.4kÅ - 15.6kÅ, Silane
0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218
10
AL.
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