96628.pdf

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R183-97.
97-02-24
Monica L. Poelking
B
Changes in accordance with NOR 5962-R402-97.
97-07-29
Raymond Monnin
C
Make corrections to block diagrams in figure 2. Incorporate revisions A and B.
Update boilerplate to MIL-PRF-38535 requirements. Editorial changes
throughout. – LTG
03-12-11
Thomas M. Hess
D
Update radiation features in section 1.5 and paragraphs 4.4.4.1 – 4.4.4.5.
Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. LTG
10-06-23
Thomas M. Hess
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PMIC N/A
PREPARED BY
Marcia B. Kelleher
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DSCC FORM 2233
APR 97
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Monica L. Poelking
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
95-12-15
REVISION LEVEL
D
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED CMOS, RIPPLE CARRY BINARY
COUNTER/DIVIDER, MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
5962-96628
1 OF 25
5962-E339-10
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
96628
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
Y
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
4020B
Radiation hardened CMOS, 14 stage
ripple-carry binary counter/divider
02
4020BN
Radiation hardened CMOS, 14 stage
ripple-carry binary counter/divider with
neutron irradiated die
03
4024B
Radiation hardened CMOS, 7 stage
ripple-carry binary counter/divider
04
4024BN
Radiation hardened CMOS, 7 stage
ripple-carry binary counter/divider with
neutron irradiated die
05
4040B
Radiation hardened CMOS, 12 stage
ripple-carry binary counter/divider
06
4040BN
Radiation hardened CMOS, 12 stage
ripple-carry binary counter/divider with
neutron irradiated die
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
C
X
E
Y
Descriptive designator
CDIP2-T14
CDFP3-F14
CDIP2-T16
CDFP4-F16
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Terminals
Package style
14
14
16
16
Dual-in-line
Flat pack
Dual-in-line
Flat pack
SIZE
5962-96628
A
REVISION LEVEL
D
SHEET
2
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VDD) ......................................................................................... -0.5 V dc to +20 V dc
Input voltage range .................................................................................................... -0.5 V dc to VDD + 0.5 V dc
DC input current, any one input .................................................................................. 10 mA
Device dissipation per output transistor ...................................................................... 100 mW
Storage temperature range (TSTG) .............................................................................. -65C to +150C
Lead temperature (soldering, 10 seconds) ................................................................. +265C
Thermal resistance, junction-to-case (JC):
Cases C and E ........................................................................................................ 24C/W
Case X ..................................................................................................................... 30C/W
Case Y ..................................................................................................................... 29C/W
Thermal resistance, junction-to-ambient (JA):
Case C .................................................................................................................... 74C/W
Case X ..................................................................................................................... 116C/W
Case E ..................................................................................................................... 73C/W
Case Y ..................................................................................................................... 114C/W
Junction temperature (TJ) ........................................................................................... +175C
Maximum power dissipation (PD) at TA = +125C: 4/
Cases C and E ........................................................................................................ 0.68 W
Case X ..................................................................................................................... 0.43 W
Case Y ..................................................................................................................... 0.44 W
1.4 Recommended operating conditions.
Supply voltage range (VDD) .........................................................................................
Case operating temperature range (TC)......................................................................
Input voltage (VIN) .......................................................................................................
Output voltage (VOUT) .................................................................................................
3.0 V dc to +18 V dc
-55C to +125C
0 V to VDD
0 V to VDD
1.5 Radiation features.
Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) ...............................  1 x 105 rads (Si)
Single event phenomenon (SEP):
effective LET, no upsets (see 4.4.4.5) ....................................................................  75 MeV/(cm2/mg) 5/
effective LET, no latchup (see 4.4.4.5) ...................................................................  75 MeV/(cm2/mg) 5/
8
Dose rate upset (20 ns pulse) ....................................................................................  5 x 10 rads(Si)/s 5/
8
Dose rate latch-up .....................................................................................................  2 x 10 rads(Si)/s 5/
11
Dose rate survivability ...............................................................................................  5 x 10 rads(Si)/s 5/
14
2
Neutron irradiated ......................................................................................................  1 x 10 neutrons/cm 6/
1/
2/
3/
4/
5/
6/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise specified, all voltages are referenced to VSS.
The limits for the parameters specified herein shall apply over the full specified VDD range and case temperature range of
-55C to +125C unless otherwise noted.
If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is
based on JA) at the following rate:
Case C ....................................................................................................................... 13.5 mW/C
Case X ....................................................................................................................... 8.6 mW/C
Case E ....................................................................................................................... 13.7 mW/C
Case Y ....................................................................................................................... 8.8 mW/C
Guaranteed by design or process but not tested.
Device types 02, 04, and 06 only.
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REVISION LEVEL
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2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Block diagrams. The block diagrams shall be as specified on figure 2.
3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
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REVISION LEVEL
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3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 40 (see MIL-PRF-38535, appendix A).
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REVISION LEVEL
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TABLE IA. Electrical performance characteristics.
Test
Supply current
Symbol
IDD
Test conditions
-55C  TC  +125C
unless otherwise specified
IOL
VDD = 5 V
VIN = 0.0 V or VDD
All
1, 3 1/
5.0
2 1/
150
VDD = 10 V
VIN = 0.0 V or VDD
All
1, 3 1/
10
2 1/
300
VDD = 15 V
VIN = 0.0 V or VDD
All
1, 3 1/
10
2 1/
600
VDD = 20 V, VIN = 0.0 V or VDD
All
1
10
2
1000
All
1
25
VDD = 18 V, VIN = 0.0 V or VDD
All
3
10
VDD = 5 V
VO = 0.4 V
VIN = 0.0 V or VDD
All
1
0.53
2 1/
0.36
3 1/
0.64
1
1.4
2 1/
0.9
3 1/
1.6
1
3.5
2 1/
2.4
3 1/
4.2
VDD = 10 V
VO = 0.5 V
VIN = 0.0 V or VDD
All
VDD = 15 V
VO = 1.5 V
VIN = 0.0 V or VDD
High level output
current (source)
IOH
Units
Group A
subgroups
M, D, P, L, R 2/
Low level output
current (sink)
Limits
Device
type
All
VDD = 5 V
VO = 4.6 V
VIN = 0.0 V or VDD
All
All
VDD = 5 V
VO = 2.5 V
VIN = 0.0 V or VDD
VDD = 10 V
VO = 9.5 V
VIN = 0.0 V or VDD
All
VDD = 15 V
VO = 13.5 V
VIN = 0.0 V or VDD
All
Min
Max
A
mA
1
-0.53
2 1/
-0.36
3 1/
-0.64
1
-1.8
2 1/
-1.15
3 1/
-2.0
1
-1.4
2 1/
-0.9
3 1/
-1.6
1
-3.5
2 1/
-2.4
3 1/
-4.2
mA
See footnotes at end of table.
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TABLE IA. Electrical performance characteristics – Continued.
Test
Output voltage, high
Output voltage, low
Input voltage, low
Input voltage, high
Input leakage current,
low
Input leakage current,
high
N threshold voltage
Symbol
VOH
VOL
VIL
VIH
IIL
IIH
VNTH
Test conditions
-55C  TC  +125C
unless otherwise specified
Limits
Device
type
Group A
subgroups
All
1, 2, 3
4.95
VDD = 10 V, no load 1/
1, 2, 3
9.95
VDD = 15 V, no load 3/
1, 2, 3
14.95
VDD = 5 V, no load 1/
VDD = 5 V, no load 1/
All
Min
Units
Max
V
1, 2, 3
0.05
VDD = 10 V, no load 1/
1, 2, 3
0.05
VDD = 15 V, no load
1, 2, 3
0.05
1, 2, 3
1.5
VDD = 10 V
VOH > 9.0 V, VOL < 1.0 V 1/
1, 2, 3
3
VDD = 15 V
VOH > 13.5 V, VOL < 1.5 V
1, 2, 3
4
VDD = 5 V
VOH > 4.5 V, VOL < 0.5 V
All
VDD = 5 V
VOH > 4.5 V, VOL < 0.5 V
All
1, 2, 3
3.5
VDD = 10 V
VOH > 9.0 V, VOL < 1.0 V 1/
1, 2, 3
7
VDD = 15 V
VOH > 13.5 V, VOL < 1.5 V
1, 2, 3
11
1
-100
VIN = VDD or GND, VDD = 20 V
2
-1000
VIN = VDD or GND, VDD = 18 V
3
-100
VIN = VDD or GND, VDD = 20 V
All
VIN = VDD or GND, VDD = 20 V
All
nA
100
VIN = VDD or GND, VDD = 20 V
2
1000
VIN = VDD or GND, VDD = 18 V
3
100
M, D, P, L, R 2/
All
1
-0.7
-2.8
All
1
-0.2
-2.8
N threshold voltage,
delta
VNTH
VDD = 10 V, ISS = -10 A
M, D, P, L, R 2/
All
1
P threshold voltage
VPTH
VSS = 0.0 V, IDD = 10 A
All
1
0.7
2.8
All
1
0.2
2.8
M, D, P, L, R 2/
V
V
1
VDD = 10 V, ISS = -10 μA
V
V
1.0
P threshold voltage,
delta
VPTH
VSS = 0.0 V, IDD = 10 A
M, D, P, L, R 2/
All
1
1.0
Input capacitance
CIN 1/
Any input, See 4.4.1c
All
4
7.5
pF
See footnotes at end of table.
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TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Functional tests
Test conditions
-55C  TC  +125C
unless otherwise specified
VDD = 2.8 V, VIN = VDD or GND
Device
type
Group A
subgroups
All
7
VDD = 20 V, VIN = VDD or GND
7
VDD = 18 V, VIN = VDD or GND
tPHL1,
tPLH1
7
All
9
200
10, 11
270
VDD = 10 V, VIN = VDD or GND
9 1/
100
VDD = 15 V, VIN = VDD or GND
9 1/
80
9
360
10, 11
486
All
9
486
All
9 1/
160
9 1/
130
9
330
10, 11
446
All
9
446
All
9 1/
80
9 1/
60
9
280
10, 11
378
All
9
378
All
9 1/
120
9 1/
100
VDD = 5.0 V, VIN = VDD or GND
VDD = 5.0 V, VIN = VDD or GND
All
VDD = 5.0 V, VIN = VDD or GND
All
VDD = 10 V, VIN = VDD or GND
VDD = 15 V, VIN = VDD or GND
VDD = 5.0 V, VIN = VDD or GND
All
M, D, P, L, R 2/
VDD = 10 V, VIN = VDD or GND
VDD = 15 V, VIN = VDD or GND
Maximum clock input
frequency 4/
FCL
ns
All
M, D, P, L, R 2/
tPHL3
V
8B
VDD = 15 V, VIN = VDD or GND
Propagation delay time,
RESET to Q 4/
VOL <
VDD/2
All
VDD = 10 V, VIN = VDD or GND
tPHL2,
tPLH2
VOH >
VDD/2
7
M, D, P, L, R 2/
Propagation delay time,
Qn to Qn + 1 4/
Max
All
M, D, P, L, R 2/
Propagation delay
time,  to Q1 4/
Min
8A
VDD = 3.0 V, VIN = VDD or GND
tTLH,
tTHL
Units
All
M, D, P, L, R 2/
Transition time, Q1 4/
Limits
VDD = 5.0 V, VIN = VDD or GND
All
9
3.5
10, 11
2.2
VDD = 10 V, VIN = VDD or GND
9 1/
8.0
VDD = 15 V, VIN = VDD or GND
9 1/
12
ns
ns
ns
MHz
See footnotes at end of table.
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TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Reset removal time
1/ 4/
tREM
tW1
Minimum RESET
pulse width 1/ 4/
Minimum input pulse
width 1/ 4/
tW2
Device Group A
type
subgroups
Test conditions
-55C  TC  +125C
unless otherwise specified
VDD = 5.0 V
All
Limits
Min
Units
Max
9
350
VDD = 10 V
9
150
VDD = 15 V
9
100
9
200
VDD = 10 V
9
80
VDD = 15 V
9
60
9
140
VDD = 10 V
9
60
VDD = 15 V
9
40
VDD = 5.0 V
All
VDD = 5.0 V
All
ns
ns
ns
1/ These tests are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which affect these characteristics.
2/ RHA devices supplied to this drawing have been characterized through all levels M, D, P, L, and R of irradiation.
However, these devices are only tested at the "R" level. Pre and post irradiation values are identical unless otherwise
specified in table I. When performing post irradiation electrical measurements for any RHA level, TA = +25C.
3/ For accuracy, voltage is measured differentially to VDD. Limit is 0.050 V Max.
4/ CL = 50 pF, RL = 200k, input tr, tf < 20 ns.
TABLE IB. SEP test limits. 1/ 2/ 7/
Device
type
VDD = 3.0 V 3/
Bias for
latch-up test
VDD = 3.6 V
no latch-up
LET = 4/ 5/
2
[MeV/(mg/cm )]
Effective LET
no upsets
[MeV/(mg/cm2)]
All
LET  75 6/
 75
1/ For SEP test conditions, see 4.4.4.5 herein.
2/ Technology characterization and model verification supplemented by in-line data may be
used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity.
3/ Tested for upsets at worst case temperature, TA = +25C 10C.
4/ Tested at worst case temperature, TA = +125C 10C for latch-up.
2
5/ Tested to a LET of  75 MeV/(mg/cm ), with no latch-up (SEL).
2
6/ Tested to a LET of  75 MeV/(mg/cm ) with no single event upsets (SEU).
7/ Guaranteed by design or process but not tested.
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Device types
01 and 02
03 and 04
05 and 06
Case outlines
E and Y
C and X
E and Y
Terminal number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Terminal symbol
Q12
Q13
Q14
Q6
Q5
Q7
Q4
VSS
Q1

RESET
Q9
Q8
Q10
Q11
VDD

RESET
Q7
Q6
Q5
Q4
VSS
NC
Q3
NC
Q2
Q1
NC
VDD
-----
Q12
Q6
Q5
Q7
Q4
Q3
Q2
VSS
Q1

RESET
Q9
Q8
Q10
Q11
VDD
NC = No internal connection
FIGURE 1. Terminal connections.
STANDARD
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NOTE: Inputs protected by COS/MOS protection network.
FIGURE 2. Block diagrams.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
c. Subgroup 4 (CIN measurement) shall be measured only for the initial qualification and after process or design changes
which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of
1 MHz. Tests shall be sufficient to validate the limits defined in table IA herein.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
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TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-STD-883, method
5005, table I)
Subgroups
(in accordance with MIL-PRF-38535,
table III)
Device class M
Device class Q
Device class V
1,7,9
1,7,9
1,7,9
Final electrical parameters
(see 4.2)
1,2,3,7,8,9,10,11
1/
1,2,3,7,8,9,10,11
1/
1,2,3,7,8,9,10,11
2/ 3/
Group A test requirements
(see 4.4)
1,2,3,4,7,8,9,10,11
1,2,3,4,7,8,9,10,11
1,2,3,4,7,8,9,10,11
Group C end-point electrical
parameters (see 4.4)
1,2,3,7,8,9,10,11
1,2,3,7,8,9,10,11
1,2,3,7,8,9,10,11
3/
Group D end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
1,7,9
Group E end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
1,7,9
Interim electrical parameters
(see 4.2)
1/ PDA applies to subgroups 1 and 7.
2/ PDA applies to subgroups 1, 7, 9, and deltas.
3/ Delta limits, as specified in table IIB, shall be required where specified, and the delta limits shall be completed
with reference to the zero hour electrical parameters (see table IA).
TABLE IIB. Burn-in and operating life test, delta parameters (+25C).
Parameter
Symbol
Delta limits
Supply current
IDD
1.0 A
Output current (sink)
VDD = 5.0 V
IOL
20%
Output current (source)
VDD = 5.0 V, VOUT = 4.6 V
IOH
20%
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
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4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25C 5C,
after exposure, to the subgroups specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883,
method 1019, condition A, and as specified herein.
4.4.4.1.1 Accelerated annealing testing. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limits at 25C 5C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Neutron irradiation. Neutron irradiation for device 02, 04, and 06 shall be conducted in wafer form using a neutron
14
2
fluence of approximately 1 x 10 neutrons/cm .
4.4.4.3 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with method
1020 of MIL-STD-883 and as specified herein (see 1.4 herein). Tests shall be performed on devices, SEC, or approved test
structures at technology qualification and after any design or process changes which may affect the RHA capability of the
process.
4.4.4.4 Dose rate upset testing. When required by the customer, dose rate upset testing shall be performed in accordance
with method 1021 of MIL-STD-883 and herein.
a.
Transient dose rate upset testing shall be performed at initial qualification and after any design or process change
which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b.
Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535. Device parameters that influence upset immunity shall be
monitored at the wafer level in accordance with the wafer level hardness assurance plan and MIL-PRF-38535.
4.4.4.5 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive
(i.e. 0  angle  60). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be  100 errors or ≥ 107 ions/cm2.
c.
The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be  20 microns in silicon.
e.
The upset test temperature shall be +25C and the latchup test temperature is maximum rated operating temperature
10C.
f.
Bias conditions shall be defined by the manufacturer for latchup measurements.
g.
For SEP test limits, see table IB herein.
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4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied.
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latch-up (SEP).
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
96628
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A
dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
Circuit function
01
4020B
Radiation hardened CMOS, 14 stage
ripple-carry binary counter/divider
02
4020BN
Radiation hardened CMOS, 14 stage
ripple-carry binary counter/divider with
neutron irradiated die
03
4024B
Radiation hardened CMOS, 7 stage
ripple-carry binary counter/divider
04
4024BN
Radiation hardened CMOS, 7 stage
ripple-carry binary counter/divider with
neutron irradiated die
05
4040B
Radiation hardened CMOS, 12 stage
ripple-carry binary counter/divider
06
4040BN
Radiation hardened CMOS, 12 stage
ripple-carry binary counter/divider with
neutron irradiated die
A.1.2.3 Device class designator.
Device class
Q or V
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die's physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01, 02
03, 04
05, 06
A-1
A-2
A-3
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01, 02
03, 04
05, 06
A-1
A-2
A-3
A.1.2.4.3 Interface materials.
Die type
Figure number
01, 02
03, 04
05, 06
A-1
A-2
A-3
A.1.2.4.4 Assembly related information.
Die type
Figure number
01, 02
03, 04
05, 06
A-1
A-2
A-3
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified
in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figures A-1, A-2,
and A-3.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figures A-1, A-2, and A-3.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figures A-1, A-2,
and A-3
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figures A-1,
A-2, and A-3.
A.3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.4 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
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APPENDIX A
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A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table II herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614) 692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have
agreed to this drawing.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
NOTE:
Pad numbers reflect terminal numbers when placed in case outlines E and Y (see figure 1).
FIGURE A-1. Die bonding pad locations and electrical functions.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
Die physical dimensions.
Die size:
Die thickness:
2388 x 2743 microns
20 1 mils
Interface materials.
Top metallization:
Al
Thickness
Backside metallization:
11.0kÅ – 14.0kÅ
None
Glassivation.
Type:
Thickness:
Substrate:
PSG
10.4kÅ - 15.6kÅ
Single Crystal Silicon
Assembly related information.
Substrate potential:
Special assembly instructions:
Floating or tied to VDD
Bond pad #16 (VDD) first.
FIGURE A-1. Die bonding pad locations and electrical functions – Continued.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
NOTE:
Pad numbers reflect terminal numbers when placed in case outlines C and X (see figure 1).
FIGURE A-2. Die bonding pad locations and electrical functions.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
Die physical dimensions.
Die size:
Die thickness:
1702 x 2311 microns
20 1 mils
Interface materials.
Top metallization:
Al
Thickness
Backside metallization:
11.0kÅ – 14.0kÅ
None
Glassivation.
Type:
Thickness:
Substrate:
PSG
10.4kÅ - 15.6kÅ
Single Crystal Silicon
Assembly related information.
Substrate potential:
Special assembly instructions:
Floating or tied to VDD
Bond pad #14 (VDD) first.
FIGURE A-2. Die bonding pad locations and electrical functions – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96628
A
REVISION LEVEL
D
SHEET
23
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
NOTE:
Pad numbers reflect terminal numbers when placed in case outlines E and Y (see figure 1).
FIGURE A-3. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96628
A
REVISION LEVEL
D
SHEET
24
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96628
Die physical dimensions.
Die size:
Die thickness:
2388 x 2743 microns
20 1 mils
Interface materials.
Top metallization:
Al
Thickness
Backside metallization:
11.0kÅ – 14.0kÅ
None
Glassivation.
Type:
Thickness:
Substrate:
PSG
10.4kÅ - 15.6kÅ
Single Crystal Silicon
Assembly related information.
Substrate potential:
Special assembly instructions:
Floating or tied to VDD
Bond pad #16 (VDD) first.
FIGURE A-3. Die bonding pad locations and electrical functions – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96628
A
REVISION LEVEL
D
SHEET
25
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-06-23
Approved sources of supply for SMD 5962-96628 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962R9662801VEC
3/
CD4020BDMSR
5962R9662801VYC
3/
CD4020BKMSR
5962R9662801V9A
3/
CD4020BHSR
5962R9662802VEC
3/
CD4020BDNSR
5962R9662802VYC
3/
CD4020BKNSR
5962R9662802V9A
3/
CD4020BHNSR
5962R9662803VCC
34371
CD4024BDMSR
5962R9662803VXC
34371
CD4024BKMSR
5962R9662803V9A
34371
CD4024BHSR
5962R9662804VCC
3/
CD4024BDNSR
5962R9662804VXC
3/
CD4024BKNSR
5962R9662804V9A
3/
CD4024BHNSR
5962R9662805VEC
3/
CD4040BDMSR
5962R9662805VYC
3/
CD4040BKMSR
5962R9662805V9A
3/
CD4040BHSR
5962R9662806VEC
3/
CD4040BDNSR
5962R9662806VYC
3/
CD4040BKNSR
5962R9662806V9A
3/
CD4040BHNSR
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-6803
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.