DATASHEET

HCS160MS
Radiation Hardened
BCD Decade Synchronous Counter
September 1995
Features
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Pinouts
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm2/mg
Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 1012 RAD (Si)/s
Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
-Standard Outputs: 10 LSTTL Loads
-Bus Driver Outputs: 15 LSTTL Loads
Military Temperature Range: -55oC to +125oC
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
-VIL = 30% of VCC Max
-VIH = 70% of VCC Min
Input Current Levels Ii ≤ 5µA @ VOL, VOH
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
16 VCC
CP 2
15 TC
P0 3
14 Q0
P1 4
13 Q1
P2 5
12 Q2
P3 6
11 Q3
PE 7
10 TE
9 SPE
GND 8
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Description
The Intersil HCS160MS is a Radiation Hardened high speed
presettable BCD decade synchronous counter that features an
asynchronous reset and look-ahead carry logic. Counting and
parallel presetting are accomplished synchronously with the lowto-high transition of the clock. A low level on the synchronous
parallel enable input, SPE, disables counting and allows data at
the preset inputs, P0 - P3, to be loaded into the counter. The
counter is reset by a low on the master reset input, MR. Two count
enables, PE and TE are provided for n-bit cascading. TE also
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to
enable the next cascaded stage to count.
MR 1
MR
1
16
VCC
CP
2
15
TC
P0
3
14
Q0
P1
4
13
Q1
P2
5
12
Q2
P3
6
11
Q3
PE
7
10
TE
GND
8
9
SPE
The HCS160MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS160MS is supplied in a 16 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix.)
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS160DMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead SBDIP
HCS160KMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
+25oC
Sample
16 Lead SBDIP
HCS160K/Sample
+25oC
Sample
16 Lead Ceramic Flatpack
HCS160HMSR
+25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
183
DB NA
HCS160D/Sample
Spec Number
File Number
518834
2296.2
HCS160MS
Functional Block Diagram
P0
P1
3
P2
4
P3
5
6
SPE
MR
Q1
Q0 Q2 Q0 Q3
Q2 Q3 Q0 Q1
Q3 Q0 Q3 Q0
CP
MR
P
MR
D0
T0
P
MR
D1
Q0
T1
CP Q0
CP
P
MR
D2
T2
Q1
Q3 Q3
P
D3
T3
Q2
CP
Q3
CP Q0
PE
TE
GND
8
VCC
16
14
Q0
15
13
TC
12
Q1
11
Q0
Q1
TRUTH TABLE
INPUTS
OPERATING MODE
OUTPUTS
MR
CP
PE
TE
SPE
Pn
Qn
TC
Reset (Clear)
L
X
X
X
X
X
L
L
Parallel Load
H
X
X
l
l
L
L
H
X
X
l
h
H
(Note 1)
Count
H
h
h
h (Note 3)
X
Count
(Note 1)
Inhibit
H
X
l (Note 2)
X
h (Note 3)
X
qn
(Note 1)
H
X
X
l (Note 2)
h (Note 3)
X
qn
L
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
q = Lower case letterindicate the state of the referenced output prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
NOTES:
1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160)
2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation
3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation
Spec Number
184
518834
Specifications HCS160MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W
29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .100ns Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
750
µA
1
+25oC
4.8
-
mA
2, 3
+125oC, -55oC
4.0
-
mA
1
+25oC
-4.8
-
mA
2, 3
+125oC, -55oC
-4.0
-
mA
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-
±0.5
µA
2, 3
+125oC, -55oC
-
±5.0
µA
7, 8A, 8B
+25oC, +125oC, -55oC
-
-
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 2)
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
185
518834
Specifications HCS160MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
CP to QN
CP to TC
TE to TC
MR to QN, MR to TC
(NOTES 1, 2)
CONDITIONS
SYMBOL
TPHL,
TPLH
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
27
ns
10, 11
+125oC, -55oC
2
33
ns
9
+25oC
2
24
ns
10, 11
+125oC, -55oC
2
29
ns
9
+25oC
2
19
ns
10, 11
+125oC, -55oC
2
23
ns
9
+25oC
2
32
ns
10, 11
+125oC, -55oC
2
39
ns
VCC = 4.5V
TPHL,
TPLH
VCC = 4.5V
TPHL,
TPLH
VCC = 4.5V
TPHL
VCC = 4.5V
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
Output Transition
Time
Max Operating
Frequency
CIN
TTHL
TTLH
FMAX
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
38
pF
1
+125oC, -55oC
-
63
pF
1
+25oC
-
10
pF
1
+125oC, -55oC
-
10
pF
1
+25oC
-
15
ns
1
+125oC, -55oC
-
22
ns
1
+25oC
30
-
MHz
1
+125oC, -55oC
20
-
MHz
VCC = 5.0V, f = 1MHz
VCC = Open, f = 1MHz
VCC = 4.5V
VCC = 4.5V
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K LIMITS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
Quiescent Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.75
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25oC
4.0
-
mA
Spec Number
186
518834
Specifications HCS160MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
200K LIMITS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
TEMPERATURE
MIN
MAX
UNITS
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25oC
-4.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
+25oC
-
-0.1
V
Output Voltage High
VOH
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
+25oC
VCC
-0.1
-
V
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±5
µA
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 3.15V,
VIL =1.35V, (Note 3)
+25oC
-
-
-
CP to QN
TPHL,
TPLH
VCC = 4.5V
+25oC
2
29
ns
CP to TC
TPHL,
TPLH
VCC = 4.5V
+25oC
2
33
ns
TE to TC
TPHL,
TPLH
VCC = 4.5V
+25oC
2
23
ns
MR to QN, MR to TC
TPHL
VCC = 4.5V
+25oC
2
39
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
12µA
IOL/IOH
5
-15% of 0 Hour
PARAMETER
Spec Number
187
518834
Specifications HCS160MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL.H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL.H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL.H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/6005
1, 7, 9
Group A (Note 1)
Group B
Group D
READ AND RECORD
ICC, IOL/H, IOZL.H
Subgroups 1, 2, 3, 9, 10, 11
NOTE:
1. Alternate Group A testing in accordance with Method 5005 of Mil-Std-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE
GROUPS
Group E Subgroup 2
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 7, 9
Table 4 (Note 1)
NOTE:
1. Except FN test which will be performed 100% go/no-go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
1 - 10
-
16
-
-
8
-
1 - 7, 9, 10, 16
-
-
4, 6, 8
11 - 15
1, 3, 5, 7, 9, 10, 16
2
-
STATIC I BURN-IN
11 - 15
STATIC II BURN-IN
11 - 15
DYNAMIC BURN-IN
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
11 - 15
8
1 - 7, 9, 10, 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
188
518834
HCS160MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
189
518834
HCS160MS
AC Timing Diagrams
AC Load Circuit
VIH
DUT
INPUT
VS
TEST
POINT
VIL
CL
TPLH
RL
TPHL
VOH
VS
OUTPUT
CL = 50pF
VOL
RL = 500Ω
TTLH
VOH
TTHL
80%
20%
VOL
80%
OUTPUT
20%
AC VOLTAGE LEVELS
PARAMETER
HCS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
Spec Number
190
518834
HCS160MS
Die Characteristics
DIE DIMENSIONS:
104 x 86 mils
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
HCS160MS
CP
(2)
MR
(1)
VCC
(16)
(15) TC
P0 (3)
(14) Q0
P1 (4)
(13) Q1
P2 (5)
(12) Q2
P3 (6)
(11) Q3
PE (7)
(8)
GND
(9)
SPE
(10)
TE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
191
518834
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