DATASHEET

HCTS193MS
Radiation Hardened
Synchronous 4-Bit Up/Down Counter
September 1995
Features
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Pinouts
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm2/mg
Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)
Dose Rate Survivability: >1 x 1012 RAD (Si)/s
Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
Military Temperature Range: -55oC to +125oC
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii ≤ 5µA at VOL, VOH
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
1
16 VCC
2
15 P0
Q0
3
14 MR
CPD
4
13 TCD
CPU
5
12 TCU
Q2
6
11 PL
Q3
7
10 P2
GND
8
9 P3
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
Description
The Intersil HCTS193MS is a Radiation Hardened 4-bit binary
UP/DOWN synchronous counter.
Presetting the counter to the number on the preset data inputs
(P0 - P3) is accomplished by a low on the asynchronous parallel
load input (PL). The counter is incremented on the low to high
transition of the clock-up input (high on the clock-down),
decremented on the low to high transition of the clock-down input
(high on the clock-up). A high level on the MR input overrides any
other input to clear the counter to zero. The Terminal Count Up
goes low half a clock period before the zero count is reached and
returns high at the maximum count. The Terminal Count Down
mode goes low half a clock period before the maximum count
and returns high at the maximum count.
P1
Q1
16
VCC
2
15
P0
3
14
MR
CPD
4
13
TCD
CPU
5
12
TCU
Q2
6
11
PL
Q3
7
10
P2
GND
8
9
P3
P1
Q1
Q0
1
The HCTS193MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS193MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS193DMSR
-55oC
+125oC
Intersil Class S Equivalent
16 Lead SBDIP
HCTS193KMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCTS193D/Sample
+25oC
Sample
16 Lead SBDIP
HCTS193K/Sample
+25oC
Sample
16 Lead Ceramic Flatpack
HCTS193HMSR
+25oC
Die
Die
to
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
592
Spec Number
File Number
518620
3066.1
DB NA
PART NUMBER
HCTS193MS
Functional Diagram
P0
P1
15
P2
1
P3
10
9
14
MR
11
PL
5
CPU
PL R
P Q
PL R
P Q
PL R
P Q
PL R
P Q
FF0
FF1
FF2
FF3
CL Q
CL Q
CL Q
CL Q
12
TCU
13
TCD
4
CPD
8
GND
16
VCC
3
2
Q0
6
Q1
7
Q2
Q3
TRUTH TABLE
FUNCTION
CLOCK UP
Count Up
CLOCK DOWN
RESET
PARALLEL LOAD
H
L
H
L
H
Count Down
H
Reset
X
X
H
X
Load Preset Inputs
X
X
L
L
H = High Level, L = Low Level, X = Immaterial,
= Transition from low to high
Spec Number
593
518620
Specifications HCTS193MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W
29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . 500ns Max.
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
750
µA
1
+25oC
4.8
-
mA
2, 3
+125oC, -55oC
4.0
-
mA
1
+25oC
-4.8
-
mA
2, 3
+125oC, -55oC
-4.0
-
mA
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V,
IOL = -50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 2.75V,
IOL = -50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-
±0.5
µA
2, 3
+125oC, -55oC
-
±5.0
µA
7, 8A, 8B
+25oC, +125oC, -55oC
-
-
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
LIMITS
NOTES:
1. All voltages reference to device GND.
2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
594
518620
Specifications HCTS193MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
CPU to Qn
SYMBOL
TPLH
TPHL
CPD to Qn
TPLH
TPHL
PL to Qn
TPLH
TPHL
MR to Qn
(NOTES 1, 2)
CONDITIONS
TPHL
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
29
ns
10, 11
+125oC, -55oC
2
34
ns
9
+25oC
2
35
ns
10, 11
+125oC, -55oC
2
41
ns
9
+25oC
2
31
ns
10, 11
+125oC, -55oC
2
36
ns
9
+25oC
2
36
ns
10, 11
+125oC, -55oC
2
42
ns
9
+25oC
2
32
ns
10, 11
+125oC, -55oC
2
36
ns
9
+25oC
2
45
ns
10, 11
+125oC, -55oC
2
53
ns
9
+25oC
2
37
ns
10, 11
+125oC, -55oC
2
44
ns
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
CIN
CONDITIONS
VCC = 4.5V
Maximum Operating
Frequency (CPU,
CPD)
FMAX
VCC = 4.5V
Hold Time
Pn to PL
TH
Hold Time CPD to
CPU or CPU to CPD
TH
Pulse Width
CPU to CPD
TW
Pulse Width PL
TW
MIN
MAX
UNITS
1
+25oC
-
53
pF
1
+125oC, -55oC
-
75
pF
1
+25oC
-
10
pF
1
+125oC
-
10
pF
1
+25oC
-
15
ns
1
+125oC, -55oC
-
22
ns
1
+25oC
-
25
MHz
1
+125oC, -55oC
-
15
MHz
1
+25oC
15
-
ns
1
+125oC, -55oC
22
-
ns
1
+25oC
0
-
ns
1
+125oC, -55oC
0
-
ns
1
+25oC
16
-
ns
1
+125oC, -55oC
24
-
ns
1
+25oC
23
-
ns
1
+125oC, -55oC
35
-
ns
1
+25oC
16
-
ns
1
+125oC, -55oC
24
-
ns
VCC = 5.0V, f = 1MHz
TTHL
TTLH
TSU
TEMPERATURE
VCC = 5.0V, f = 1MHz
Output Transition
Time
Setup Time
Pn to PL
NOTES
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
Spec Number
595
518620
Specifications HCTS193MS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Pulse Width MR
SYMBOL
TW
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
20
-
ns
1
+125oC, 55oC
30
-
ns
1
+25oC
15
-
ns
1
+125oC, 55oC
22
-
ns
1
+25oC
5
-
ns
1
+125oC, 55oC
5
-
ns
VCC = 4.5V
Recovery Time
PL to CPU, CPD
TREC
Recovery Time
MR to CPU, CPD
TREC
VCC = 4.5V
VCC = 4.5V
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
TEMPERATURE
MIN
MAX
UNITS
Quiescent Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.75
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25oC
4.0
-
mA
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25oC
-4.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V, IOL = 50µA
+25oC
-
0.1
V
Output Voltage High
VOH
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V, IOL = -50µA
+25oC
VCC
-0.1
-
V
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±5
µA
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
(Note 3)
+25oC
-
-
-
TPLH
VCC = 4.5V
+25oC
2
34
ns
TPHL
VCC = 4.5V
+25oC
2
41
ns
TPLH
VCC = 4.5V
+25oC
2
36
ns
TPHL
VCC = 4.5V
+25oC
2
42
ns
TPLH
VCC = 4.5V
+25oC
2
36
ns
TPHL
VCC = 4.5V
+25oC
2
53
ns
TPHL
VCC = 4.5V
+25oC
2
44
ns
CPU to Qn
CPD to Qn
PL to Qn
MR to Qn
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
596
518620
Specifications HCTS193MS
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
PARAMETER
DELTA LIMIT
ICC
5
12µA
IOL/IOH
5
-15% of 0 Hour
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
Subgroup B-5
Subgroup B-6
Group D
READ AND RECORD
ICC, IOL/H
Subgroups 1, 2, 3, 9, 10, 11
NOTE: 1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
NOTE: 1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
16
-
-
-
1, 4, 5, 9 - 11, 14 - 16
-
-
2, 3, 6, 7, 12, 13
4, 11, 16
5
-
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
2, 3, 6, 7, 12, 13
1, 4, 5, 8 - 11, 14, 15
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
2, 3, 6, 7, 12, 13
8
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
1, 8 - 10, 14, 15
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
2, 3, 6, 7, 12, 13
8
1, 4, 5, 9 - 11, 14 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group
E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
597
518620
HCTS193MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
598
518620
HCTS193MS
AC Timing Diagrams
I/FMAX
INPUT LEVEL
CPU OR CPD
INPUT LEVEL
VS
VS
CPU OR CPD
VS
VS
VS
TPLH
TW
TPHL
TPHL
TPLH
VS
QN
VS
TCU OR TCD
VS
FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH
VS
FIGURE 2. CLOCK TO TERMINAL COUNT DELAYS
INPUT LEVEL
PN
TW
MR
TW
VS
PL
INPUT LEVEL
VS
VS
INPUT LEVEL
VS
VS
VS
TW
TREC
TREC
CPU
OR
CPD
INPUT
LEVEL
VS
TPLH
TPHL
QN
VS
TPHL
VS
VS
QN
VS
FIGURE 3. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
PN
INPUT LEVEL
VS
CPU OR CPD
FIGURE 4. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
INPUT
LEVEL
VS
TSU(H)
TSU(L)
TH
TH
VS
PL
INPUT
LEVEL
VS
TTLH
VOH
TTHL
80%
Q=p
Q=p
20%
VOL
80%
OUTPUT
20%
QN
FIGURE 5. SETUP AND HOLD TIMES DATA TO PARALLEL
LOAD (PL)
AC Timing Diagrams
FIGURE 6. OUTPUT TRANSITION TIME
AC Load Circuit
AC VOLTAGE LEVELS
PARAMETER
DUT
HCTS
UNITS
VCC
4.50
V
VIH
3.00
V
VS
1.30
V
VIL
0
V
GND
0
V
TEST
POINT
CL
RL
CL = 50pF
RL = 500Ω
Spec Number
599
518620
HCTS193MS
Die Characteristics
DIE DIMENSIONS:
104 x 86 mils
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
HCTS193MS
Q1
(2)
P1
(1)
VCC
(16)
(15) P0
Q0(3)
(14) MR
CPD(4)
(13) TCD
CPU(5)
(12) TCU
Q2(6)
(11) PL
Q3(7)
(8)
GND
(9)
P3
(10)
P2
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCTS193 is TA14451A.
Spec Number
600
518620
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