DATASHEET

CD4051BMS, CD4052BMS
CD4053BMS
CMOS Analog
Multiplexers/Demultiplexers*
December 1992
Features
Description
• Logic Level Conversion
CD4051BMS, CD4052BMS and CD4053BMS analog multiplexers/demultiplexers are digitally controlled analog
switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V peak-topeak can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be controlled; for VDD-VEE level differences above 13V, a VDDVSS of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from 13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
ranges, independent of the logic state of the control signals.
When a logic “1” is present at the inhibit input terminal all
channels are off.
• High-Voltage Types (20V Rating)
• CD4051BMS Signal 8-Channel
• CD4052BMS Differential 4-Channel
• CD4053BMS Triple 2-Channel
• Wide Range of Digital and Analog Signal Levels:
- Digital 3V to 20V
- Analog to 20Vp-p
• Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal
Input Range for VDD - VEE = 15V
• High OFF Resistance: Channel Leakage of ±100pA
(typ) at VDD - VEE = 18V
• Logic Level Conversion:
- Digital Addressing Signals of 3V to 20V (VDD - VSS
= 3V to 20V)
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);
See Introductory Text
• Matched Switch Characteristics: RON = 5Ω (typ) for
VDD - VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digital Control Input and Supply Conditions: 0.2µW (typ)
at VDD - VSS = VDD - VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
The CD4052BMS is a differential 4 channel multiplexer having two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels
to be turned on and connect the analog inputs to the outputs.
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of channels which are connected in a single pole double-throw configuration.
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
Braze Seal DIP
*H4X
• Break-Before-Making Switching Eliminates Channel
Overlap
Frit Seal DIP
H1E
Ceramic Flatpack
H6W
Applications
*CD4051B Only
†H4T
†CD4052B, CD4053 Only
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-937
File Number
3316
CD4051BMS, CD4052BMS, CD4053BMS
Pinouts
CD4051BM
TOP VIEW
CHANNELS
IN/OUT
CD4052BMS
TOP VIEW
4
1
16 VDD
6
2
15 2
COM OUT/IN 3
14 1
7
4
13 0
5
5
12 3
INH 6
CHANNELS
IN/OUT
0
1
16 VDD
2
2
15 2
COMMON “Y” OUT/IN 3
14 1
Y CHANNELS
IN/OUT
CHANNELS
IN/OUT
X CHANNELS
IN/OUT
3
4
13 COMMON “X” OUT/IN
1
5
12 0
11 A
INH 6
11 3
VEE 7
10 B
VEE 7
10 A
VSS 8
9 C
VSS 8
9 B
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
CD4053BMS
TOP VIEW
IN/OUT
by
1
16 VDD
bx
2
15 OUT/IN bx or by
cy
3
14 OUT/IN ax or ay
OUT/IN CX or CY
4
13 ay
IN/OUT CX
5
12 ax
IN/OUT
INH 6
11 A
VEE 7
10 B
VSS 8
9 C
Functional Diagrams
CHANNEL IN/OUT
16
VDD
7
6
5
4
3
2
1
0
4
2
5
1
12
15
14
13
TG
TG
*
A
11
TG
*
B
10
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
*
C
9
INH
6
TG
3
TG
COMMON
OUT/IN
TG
TG
*
TG
VDD
8
VSS
7
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
VEE
VSS
CD4051BMS
7-938
CD4051BMS, CD4052BMS, CD4053BMS
Functional Diagrams
(Continued)
X CHANNELS IN/OUT
3
2
1
0
11
15
14
12
TG
16
VDD
TG
TG
*
A
TG
10
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
*
B
9
INH
6
COMMON X
OUT/IN
13
TG
3
COMMON Y
OUT/IN
TG
TG
*
TG
8
VSS
7
1
5
2
4
0
1
2
3
Y CHANNELS IN/OUT
VEE
CD4052BMS
VDD
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
VSS
BINARY TO 1 OF 2
DECODERS WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
16
VDD
IN/OUT
cy
cx
by
bx
ay
ax
3
5
1
2
13
12
TG
14
*
A
B
OUT/IN
ax or ay
11
TG
*
TG
OUT/IN
bx or by
15
10
TG
*
C
TG
9
OUT/IN
cx or cy
4
*
INH
TG
6
8
VSS
7
VEE
CD4053BMS
7-939
Specifications CD4051BMS, CD4052BMS, CD4053BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
Input Leakage Current
SYMBOL
IDD
IIL
IIH
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
RON
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2
+125 C
-
1000
µA
VDD = 18V, VIN = VDD or GND
3
-55oC
-
10
µA
VIN = VDD or GND
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
VDD = 18V
3
-55oC
-100
-
nA
VDD = 20
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1
+25oC
-
1050
Ω
2
+125oC
-
1300
Ω
3
-55oC
-
800
Ω
1
+25oC
-
400
Ω
2
+125oC
-
550
Ω
3
-55oC
-
310
Ω
1
+25oC
-
240
Ω
2
+125oC
-
320
Ω
Ω
VIN = VDD or GND
VDD = 20
VDD = 18V
On-State Resistance
RL = 10K Returned to
VDD - VSS/2
LIMITS
GROUP A
SUBGROUPS
VDD = 5V
VIS = VSS to VDD
VDD = 10V
VIS = VSS to VDD
VDD = 15V
VIS = VSS to VDD
o
3
-55oC
-
220
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VDD = 5V = VIS thru 1k,
VEE = VSS
RL = 1k to VSS, |IIS| < 2µA
OFF Channels
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
VDD = 15V = VIS thru 1K
VEE = VSS
RL = 1K to VSS, |ISS|, <2µA
On All OFF Channels
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
1
+25oC
-0.1
-
µA
Functional
(Note 4)
F
Input Voltage Low
(Note 2)
VIL
Input Voltage High
(Note 2)
VIH
Input Voltage Low
(Note 2)
VIL
Input Voltage High
(Note 2)
VIH
Off Channel Leakage
Any Channel OFF
Or
All Channels Off
(Common Out/In)
IOZL
IOZH
VIN = VDD or GND
VOUT = 0V
VIN = VDD or GND
VOUT = VDD
VDD = 20V
VOH > VOL <
VDD/2 VDD/2
V
2
+125oC
-1.0
-
µA
VDD = 18V
3
-55oC
-0.1
-
µA
VDD = 20V
1
+25oC
-
0.1
µA
2
+125oC
-
1.0
µA
3
-55oC
-
0.1
µA
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-940
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
4. VDD = 2.8V/3.0V, RL = 200k to VDD
VDD = 20V/18V, RL = 10k to VDD
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (Notes 1, 2)
Propagation Delay
(Note 1)
Address to Signal Out
Channels On or Off
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning On)
TPZH
TPZL
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning Off)
TPHZ
TPLZ
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
720
ns
-
972
ns
9
+25oC
-
720
ns
10, 11
+125oC, -55oC
-
972
ns
9
+25oC
-
450
ns
-
608
ns
10, 11
+125oC,
-55oC
NOTES:
1. -55oC and +125oC limits guaranteed, 100% testing being implemented.
2. CL = 50pF, RL = 10KΩ, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55oC, +25oC
-
5
µA
+125oC
-
150
µA
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Input Voltage Low
Input Voltage High
Propagation Delay
Address to Signal Out
(Channels On or Off)
VIL
VIH
TPHL
TPLH
VDD = VIS = 10V, VEE = VSS
RL = 1K to VSS
|IIS|, 2µA On/Off Channel
Propagation Delay
Inhibit to Signal Out
(Channel Turning Off)
TPZH
TPZL
TPHZ
TPLZ
CIN
1, 2
-
10
µA
+125oC
-
300
µA
-
10
µA
+125oC
-
600
µA
+25oC, +125oC,
-
3
V
-55oC,
+25oC
-55oC
+25oC, +125oC,
-55oC
+7
-
V
1, 2, 3
+25oC
-
320
ns
1, 2, 3
+25oC
-
240
ns
1, 2, 3
+25
oC
-
450
ns
1, 2, 3
+25oC
-
320
ns
VDD = 15V
1, 2, 3
+25oC
-
240
ns
VDD = 5V
VEE = -10V
1, 2, 3
+25oC
-
400
ns
1, 2, 3
+25oC
-
210
ns
1, 2, 3
+25oC
-
160
ns
1, 2, 3
+25oC
-
300
ns
1, 2
+25oC
-
7.5
pF
VDD = 10V
VEE = VSS = 0V
VDD = 15V
VDD = 10V
VDD = 10V
VEE = VSS = 0V
VEE = VSS = 0V
VDD = 15V
VDD = 5V
VEE = -15V
Input Capacitance
1, 2
-55 C, +25 C
o
1, 2
VDD = 5V
VEE = -5V
Propagation Delay
Inhibit to Signal Out
(Channel Turning On)
1, 2
o
Any Address or Inhibit Input
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
7-941
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
-
25
µA
1, 4
+25oC
-2.8
-0.2
V
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Supply Current
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
∆VTP
Functional
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
Supply Current - MSI-2
ON Resistance
SYMBOL
DELTA LIMIT
± 1.0µA
IDD
RONDEL10
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
READ AND RECORD
IDD, IOL5, IOH5A, RONDEL10
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
PART NUMBER CD4051BMS
7-942
9V ± -0.5V
50kHz
25kHz
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
3
1, 2, 4 - 6, 7, 8,
9 - 15
16
Static Burn-In 2
Note 1
3
7, 8
1, 2, 4 - 6, 9 - 16
Dynamic BurnIn Note 1
-
4 - 6, 7, 8, 9, 12, 14
1, 2, 13, 15, 16
Irradiation
Note 2
3
7, 8
1, 2, 4 - 6, 9 - 16
9V ± -0.5V
50kHz
25kHz
3
11
10
3, 13
10
9
4, 14, 15
9 - 11
PART NUMBER CD4052BMS
Static Burn-In 1
Note 1
3, 13
1, 2, 4 - 6, 7, 8,
9 - 12, 14, 15
16
Static Burn-In 2
Note 1
3, 13
7, 8
1, 2, 4 - 6, 9 - 12,
14 - 16
Dynamic BurnIn Note 1
-
4 - 6, 7, 8, 12, 15
1, 2, 11, 14, 16
3, 13
7, 8
1, 2, 4 - 6, 9 - 12,
14 - 16
Irradiation
Note 2
PART NUMBER CD4053BMS
Static Burn-In 1
Note 1
4, 14, 15
1 - 3, 5 - 8, 9 - 13
16
Static Burn-In 2
Note 1
4, 14, 15
7, 8
1 - 3, 5, 6, 9 - 13,
16
Dynamic BurnIn Note 1
-
1, 5 - 8, 12
2, 3, 13, 16
4, 14, 15
7, 8
1 - 3, 5, 6, 9 - 13,
16
Irradiation
Note 2
NOTE:
1. Each pin except pin 7 VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except pin 7 VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Typical Performance Characteristics
SUPPLY VOLTAGE (VDD - VEE) = 10V
600
CHANNEL ON RESISTANCE (RON) (Ω)
CHANNEL ON RESISTANCE (RON) (Ω)
SUPPLY VOLTAGE (VDD - VEE) = 5V
AMBIENT TEMPERATURE
(TA) = +125oC
500
400
300
+25oC
200
-55oC
100
-3
-2
-1
0
1
2
3
4
AMBIENT TEMPERATURE
(TA) = +125oC
250
200
+25oC
150
-55oC
100
50
0
-10.0 -7.5
0
-4
300
-5.0
-2.5
0
2.5
5.0
7.5
10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
INPUT SIGNAL VOLTAGE (VIS) (V)
FIGURE 1. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES)
FIGURE 2. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES)
7-943
CD4051BMS, CD4052BMS, CD4053BMS
600
(Continued)
AMBIENT TEMPERATURE
(TA) = +25oC
CHANNEL ON RESISTANCE (RON) (Ω)
CHANNEL ON RESISTANCE (RON) (Ω)
Typical Performance Characteristics
SUPPLY VOLTAGE (VDD - VEE) = 5V
500
400
300
200
10V
100
15V
SUPPLY VOLTAGE (VDD - VEE) = 15V
300
250
200
AMBIENT TEMPERATURE
(TA) = +125oC
150
100
+25oC
50
-55oC
0
0
-10.0 -7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
-10.0 -7.5
INPUT SIGNAL VOLTAGE (VIS) (V)
105
POWER DISSIPATION/PACKAGE (PD) (µW)
OUTPUT SIGNAL VOLTAGE (VOS) (V)
LOAD RESISTANCE
(RL) = 100kΩ, 10kΩ
1kΩ
1500Ω
oC
= +25
100Ω
2
0
-2
-4
-6
-4
-2
0
2
4
INPUT SIGNAL VOLTAGE (VIS) (V)
AMBIENT TEMPERATURE (TA)
= +25oC
ALTERNATING “O” AND
“I” PATTERN
LOAD CAPICATANCE (CL)
= 50pF
103
VDD
10V
102
10V
5V
CD4029
B/D
A B
100Ω 10 9
100Ω
3 CL
13
1
5
12
2
4 CD4051 14
1
15
6
11
7
8
CL = 15pF
Ι
10
10
10.0
TEST CIRCUIT
VDD
B/D
f
VDD
13
14
15
CD4051
12
1
5
2
4 8 7 6
10V
10V
5V
CL = 15pF
103
104
102
SWITCHING FREQUENCY (f) (kHz)
10
CD4029
A B C
11 10 9
100Ω
102
105
VDD
f
7.5
3
Ι CL
100Ω
103
104
102
SWITCHING FREQUENCY (f) (kHz)
105
FIGURE 6. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4051BMS)
TEST CIRCUIT
SUPPLY VOLTAGE
(VDD) (15V)
1
5.0
SUPPLY VOLTAGE
(VDD) (15V)
1
POWER DISSIPATION/PACKAGE (PD) (µW)
POWER DISSIPATION/PACKAGE (PD) (µW)
103
AMBIENT TEMPERATURE (TA)
= +25oC
ALTERNATING “O” AND
“I” PATTERN
LOAD CAPICATANCE (CL)
= 50pF
104
6
FIGURE 5. TYPICAL ON CHARACTERISTICS FOR 1 OF 8
CHANNELS (CD4051BMS)
104
2.5
10
-6
105
0
FIGURE 4. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES)
6
4
-2.5
INPUT SIGNAL VOLTAGE (VIS) (V)
FIGURE 3. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLATGE (ALL TYPES)
SUPPLY VOLTAGE (VDD) = 5V
VSS = 0V VEE = -5V
AMBIENT TEMPERATURE (TA)
-5.0
AMBIENT TEMPERATURE (TA)
= +25oC
ALTERNATING “O” AND
“I” PATTERN
LOAD CAPICATANCE (CL)
= 50pF
104
103
FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4052BMS)
9
100
Ω
SUPPLY VOLTAGE
(VDD) (15V)
10V
5V
CL = 15pF
1
10
13
CD4051
10V
102
4 CL
12
3
5
100Ω
10
105
TEST CIRCUIT
VDD
f
Ι
2
10
1
11
15
6
7
14
8
103
104
102
SWITCHING FREQUENCY (f) (kHz)
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4053BMS)
7-944
105
CD4051BMS, CD4052BMS, CD4053BMS
VDD = +15V
VDD = +7.5V
16
VDD = +5V
VDD = +5V
16
16
5V
16
5V
7.5V
VSS = 0V
VSS = 0V
VSS = 0V
VEE = 0V
7
8
VSS = 0V
(a)
7
VEE = -7.5V
8
7
VEE = -10V
(b)
8
(c)
The ADDRESS (digital-control inputs) and INHIBIT logic levels are:
“0” = VSS and “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD
FIGURE 9. TYPICAL BIAS VOLTAGES
7-945
7
VEE = -5V
8
(d)
CD4051BMS, CD4052BMS, CD4053BMS
TRUTH TABLE
INPUT STATES
tf = 20ns
tr = 20ns
“ON” CHANNEL(S)
90%
CD4051BMS
INHIBIT
90%
50%
C
B
A
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
X
X
X
NONE
50%
10%
10%
TURN-ON
TIME
tPZL
90%
50%
10%
10%
tPLZ
TURN-OFF TIME
FIGURE 10. WAVEFORM, CHANNEL BEING TURNED ON, OFF
(RL = 1kΩ)
CD4052BMS
tr = 20ns
INHIBIT
B
A
0
0
0
0x, 0y
0
0
1
1x, 1y
0
1
0
2x, 2y
0
1
1
3x, 3y
1
x
x
NONE
tf = 20ns
90%
90%
50%
50%
10%
10%
90%
10%
CD4053BMS
TURN-ON
TIME
tPZH
TURN-OFF TIME
INHIBIT
A OR B OR C
0
0
ax or bx or cx
0
1
ay or by or cy
1
X
NONE
tPHZ
FIGURE 11. WAVEFORM, CHANNEL BEING TURNED OFF, ON
(RL = 1kΩ)
X = Don’t Care
VDD
OUTPUT
OUTPUT
1
VDD
2
15
3
14
4
13
5
VEE
16
6
RL
CL
CL
RL
VDD
VEE
VEE
12
VDD
11
7
10
8
9
VSS
VEE
CLOCK
IN
1
16
2
15
3
14
4
13
5
12
6
11
VDD
7
10
VSS
8
9
VDD
VSS
VSS
VSS
VSS
CD4051
CD4052
VDD
OUTPUT
VEE
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
RL
CL
VEE
VDD
VSS
CLOCK
IN
VSS
VSS
CD4053
FIGURE 12. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
7-946
CLOCK
IN
CD4051BMS, CD4052BMS, CD4053BMS
VDD
VDD
OUTPUT
OUTPUT
16
1
RL
50pF
VDD
VDD
VSS
CLOCK
IN
15
2
VEE
RL
50pF
1
16
2
15
3
14
3
14
4
13
4
13
5
12
5
12
6
11
6
11
7
10
7
10
8
9
8
9
VEE
VDD
VDD
VSS
VEE
CLOCK
IN
VEE
VSS
VSS
VSS
VSS
tPHL AND tPLH
tPHL AND tPLH
CD4051
CD4052
OUTPUT
RL
50pF
VEE
VDD
VDD
VSS
CLOCK
IN
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VDD
VEE
VSS
VSS
tPHL AND tPLH
CD4053
FIGURE 13. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
DIFFERENTIAL
SIGNALS
CD4052
CD4052
COMMUNICATIONS
LINK
DIFF
AMPLIFIER/
LINE DRIVER
DIFF
RECEIVER
DIFF
MULTIPLEXING
DEMULTIPLEXING
FIGURE 14. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052BMS
7-947
CD4051BMS, CD4052BMS, CD4053BMS
Chip Dimensions and Pad Layouts
CD4051BMSH
CD4052BMSH
CD4053BMSH
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch)
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
948
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