96651

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R013-98.
97-12-17
Raymond Monnin
B
Incorporate revision A. Update boilerplate to MIL-PRF-38535 requirements.
Editorial changes throughout. – LTG
04-02-02
Thomas M. Hess
C
Correct the unit for the IOZL and IOZH tests in table I. Editorial changes
throughout. - LTG
04-04-15
Thomas M. Hess
D
Update boilerplate to current MIL-PRF-38535 requirements. Correct the input
voltage range in paragraph 1.4 from +20.5 V maximum to VDD + 0.5 V
maximum. - CFS
06-11-08
Thomas M. Hess
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PMIC N/A
PREPARED BY
Rick O. Officer
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Monica L. Poelking
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED CMOS, ANALOG MULTIPLEXER/
DEMULTIPLEXER, MONOLITHIC SILICON
95-12-27
AMSC N/A
REVISION LEVEL
D
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-96651
27
5962-E065-07
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
96651
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
4051B
02
4052B
03
4053B
04
4051BN
05
4052BN
06
4053BN
Circuit function
Radiation hardened CMOS, single
8-channel multiplexer
Radiation hardened CMOS, differential
4-channel multiplexer
Radiation hardened CMOS, triple
2-channel multiplexer
Radiation hardened CMOS, single
8-channel multiplexer with neutron
irradiated die
Radiation hardened CMOS, differential
4-channel multiplexer with neutron
irradiated die
Radiation hardened CMOS, triple
2-channel multiplexer with neutron
irradiated die
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
E
X
Descriptive designator
CDIP2-T16
CDFP4-F16
Terminals
Package style
16
16
Dual-in-line package
Flat package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VDD)......................................................................................... -0.5 V dc to +20 V dc
Input voltage range (VIN)............................................................................................. -0.5 V dc to VDD + 0.5 V dc
DC input current, any one input .................................................................................. ±10 mA
Device dissipation per output transistor ...................................................................... 100 mW
Storage temperature range (TSTG) .............................................................................. -65°C to +150°C
Lead temperature (soldering, 10 seconds) ................................................................. +265°C
Thermal resistance, junction-to-case (θJC):
Case E..................................................................................................................... 24°C/W
Case X..................................................................................................................... 29°C/W
Thermal resistance, junction-to-ambient (θJA):
Case E..................................................................................................................... 73°C/W
Case X..................................................................................................................... 114°C/W
Junction temperature (TJ) ........................................................................................... +175°C
Maximum power dissipation at TA = +125°C (PD): 4/
Case E..................................................................................................................... 0.68 W
Case X..................................................................................................................... 0.44 W
1.4 Recommended operating conditions.
Supply voltage range (VDD).........................................................................................
Case operating temperature range (TC)......................................................................
Input voltage range (VIN).............................................................................................
Output voltage range (VOUT) .......................................................................................
Radiation features:
Total dose .............................................................................................................
Single event phenomenon (SEP) effective
linear energy threshold, no upsets or latchup (see 4.4.4.5)..................................
Dose rate upset (20 ns pulse) ................................................................................
Dose rate latch-up .................................................................................................
Dose rate survivability ...........................................................................................
Neutron irradiated ..................................................................................................
3.0 V dc to +18 V dc
-55°C to +125°C
0 V to VDD
0 V to VDD
1 x 105 Rads (Si)
> 75 MeV/(cm2/mg) 5/
> 5 x 108 Rads(Si)/s 5/
> 2 x 108 Rads(Si)/s 5/
> 5 x 1011 Rads(Si)/s 5/
> 1 x 1014 neutrons/cm2 6/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
__________
1/
2/
3/
4/
5/
6/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise specified, all voltages are referenced to VSS.
The limits for the parameters specified herein shall apply over the full specified VDD range and case temperature range of
-55°C to +125°C unless otherwise noted.
If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is
based on θJA) at the following rate:
Case E ....................................................................................................................... 13.7 mW/°C
Case X ....................................................................................................................... 8.8 mW/°C
Guaranteed by design or process but not tested.
Device types 04, 05, and 06 only.
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DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the
Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth tables. The truth tables shall be as specified on figure 2.
3.2.4 Radiation test connections. The radiation test connections shall be as specified in table III herein.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
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3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 39 (see MIL-PRF-38535, appendix A).
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TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device Group A
subgroups
type
Min
Supply current
IDD
VDD = 5 V
VIN = 0.0 V or VDD
All
VDD = 10 V
VIN = 0.0 V or VDD
All
VDD = 15 V
VIN = 0.0 V or VDD
All
VDD = 20 V, VIN = 0.0 V or VDD
All
Input voltage, high
VIL
VIH
Max
1, 3 1/
5.0
2 1/
150
1, 3 1/
10
2 1/
300
1, 3 1/
10
2 1/
600
1
10
2
1000
All
1
25
VDD = 18 V, VIN = 0.0 V or VDD
All
3
10
VDD = 5 V = VIS through 1 kΩ
VEE = VSS
RL = 1 kΩ to VSS
IIS < 2 µA, off channels
All
1, 2, 3
1.5
VDD = VIS = 10 V
VEE = VSS
RL = 1 kΩ to VSS
IIS < 2 µA, on/off channels
1, 2, 3
3
VDD = 15 V = VIS through 1 kΩ
VEE = VSS
RL = 1 kΩ to VSS
IIS < 2 µA, on all off channels
1, 2, 3
4
M, D, P, L, R 2/
Input voltage, low
Units
Limits
All
1, 2, 3
3.5
VDD = VIS = 10 V
VEE = VSS
RL = 1 kΩ to VSS
IIS < 2 µA, on/off channels
1, 2, 3
7
VDD = 15 V = VIS through 1 kΩ
VEE = VSS
RL = 1 kΩ to VSS
IIS < 2 µA, on all off channels
1, 2, 3
11
VDD = 5 V = VIS through 1 kΩ
VEE = VSS
RL = 1 kΩ to VSS
IIS < 2 µA, off channels
µA
V
V
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device
type
Group A
subgroups
Min
On-state resistance
RON
VIS = VSS to VDD, VDD = 5 V
All
RL = 10 kΩ, returned
Units
Limits
Max
1
1050
2
1300
3
800
1
400
2
550
3
310
1
240
2
320
3
220
Ω
to (VDD – VSS)/2
VIS = VSS to VDD, VDD = 10 V
All
VIS = VSS to VDD, VDD = 15 V
Input leakage current,
low
Input leakage current,
high
N threshold voltage
IIL
IIH
VNTH
All
VIN = VDD or GND, VDD = 20 V
All
1
-100
VIN = VDD or GND, VDD = 20 V
2
-1000
VIN = VDD or GND, VDD = 18 V
3
-100
VIN = VDD or GND, VDD = 20 V
nA
1
100
VIN = VDD or GND, VDD = 20 V
2
1000
VIN = VDD or GND, VDD = 18 V
3
100
All
VDD = 10 V, ISS = -10 µA
M, D, P, L, R 2/
All
1
-0.7
-2.8
All
1
-0.2
-2.8
N threshold voltage,
delta
∆VNTH
VDD = 10 V, ISS = -10 µA
M, D, P, L, R 2/
All
1
P threshold voltage
VPTH
VSS = 0.0 V, IDD = 10 µA
All
1
0.7
2.8
All
1
0.2
2.8
All
1
M, D, P, L, R 2/
P threshold voltage,
delta
∆VPTH
VSS = 0.0 V, IDD = 10 µA
M, D, P, L, R 2/
V
±1.0
±1.0
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device Group A
Subgroups
type
Min
Off channel leakage
current, any channel
off or all channels
off (common out/in)
IOZL
IOZH
Input capacitance
CIN 1/
Functional tests
1
-0.1
VIN = VDD or GND, VDD = 20 V
VOUT = 0 V
2
-1.0
VIN = VDD or GND, VDD = 18 V
VOUT = 0 V
3
-0.1
VIN = VDD or GND, VDD = 20 V
VOUT = 0 V
All
µA
0.1
VIN = VDD or GND, VDD = 20 V
VOUT = VDD
2
1.0
VIN = VDD or GND, VDD = 18 V
VOUT = VDD
3
0.1
7.5
pF
VOL <
VDD/2
V
ns
All
Any input, See 4.4.1c
All
4
VDD = 2.8 V, VIN = VDD or GND
All
7
VOH >
VDD/2
7
VDD = 18 V, VIN = VDD or GND
All
8A
M, D, P, L, R 2/
All
7
All
8B
All
7
VDD = 5.0 V, VIN = VDD or GND
VEE = VSS = 0 V
All
9
720
10, 11
972
M, D, P, L, R 2/
All
9
972
VDD = 10 V, VIN = VDD or GND
VEE = VSS = 0 V
All
9 1/
320
VDD = 15 V, VIN = VDD or GND
VEE = VSS = 0 V
9 1/
240
VDD = 5 V, VIN = VDD or GND
VEE = -5 V, VSS = 0 V
9 1/
450
VDD = 3.0 V, VIN = VDD or GND
M, D, P, L, R 2/
tPHL,
tPLH
Max
1
VIN = VDD or GND, VDD = 20 V
VOUT = VDD
VDD = 20 V, VIN = VDD or GND
Propagation delay
time, address to
signal out, channels
on or off 3/
Units
Limits
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device Group A
Subgroups
type
Min
Propagation delay
time, inhibit to signal
out, channel turning
on 3/
tPZH,
tPZL
tPHZ,
tPLZ
VDD = 5.0 V, VIN = VDD or GND
VEE = VSS = 0 V
Units
Limits
Max
9
720
10, 11
972
VDD = 10 V, VIN = VDD or GND
VEE = VSS = 0 V
9 1/
320
VDD = 15 V, VIN = VDD or GND
VEE = VSS = 0 V
9 1/
240
VDD = 5 V, VIN = VDD or GND
VEE = -5 V, VSS = 0 V
9 1/
400
9
450
10, 11
608
VDD = 10 V, VIN = VDD or GND
VEE = VSS = 0 V
9 1/
210
VDD = 15 V, VIN = VDD or GND
VEE = VSS = 0 V
9 1/
160
VDD = 5 V, VIN = VDD or GND
VEE = -5 V, VSS = 0 V
9 1/
300
All
VDD = 5.0 V, VIN = VDD or GND
VEE = VSS = 0 V
All
ns
ns
1/ These tests are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which affect these characteristics.
2/ Devices supplied to this drawing will meet all levels M, D, P, L, and R of irradiation. However, these devices are only tested
at the 'R' level. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
3/ CL = 50 pF, RL = 10kΩ, input tr, tf < 20 ns.
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Device types
01 and 04
Case outlines
E and X
Terminal number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CHANNELS IN/OUT 4
CHANNELS IN/OUT 6
COMMON OUT/IN
CHANNELS IN/OUT 7
CHANNELS IN/OUT 5
INHIBIT
VEE
VSS
C
B
A
CHANNELS IN/OUT 3
CHANNELS IN/OUT 0
CHANNELS IN/OUT 1
CHANNELS IN/OUT 2
VDD
Device types
02 and 05
Case outlines
E and X
Terminal number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Y CHANNELS IN/OUT 0
Y CHANNELS IN/OUT 2
Y COMMON OUT/IN
Y CHANNELS IN/OUT 3
Y CHANNELS IN/OUT 1
INHIBIT
VEE
VSS
B
A
X CHANNELS IN/OUT 3
X CHANNELS IN/OUT 0
X COMMON IN/OUT 0
X CHANNELS IN/OUT 1
X CHANNELS IN/OUT 2
VDD
FIGURE 1. Terminal connections.
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Device types
03 and 06
Case outlines
E and X
Terminal number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
by IN/OUT
bx IN/OUT
cy OUT/IN
CX or CY IN/OUT
CX IN/OUT
INHIBIT
VEE
VSS
C
B
A
ax IN/OUT
ay IN/OUT
ax or ay IN/OUT
bx or by IN/OUT
VDD
FIGURE 1. Terminal connections - Continued.
Device types 01 and 04
Input states
“ON” channel
INHIBIT
C
B
A
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
X
X
X
None
FIGURE 2. Truth tables.
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Device types 02 and 05
Input states
“ON” channel
INHIBIT
B
A
0
0
0
0x, 0y
0
0
1
1x, 1y
0
1
0
2x, 2y
0
1
1
3x, 3y
1
X
X
none
Device types 03 and 06
Input states
“ON” channel
INHIBIT
A or B or C
0
0
ax or bx or cx
0
1
ay or by or cy
1
X
none
X = Irrelevant
FIGURE 2. Truth tables – Continued.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B or as modified in the device manufacturer’s quality management (QM) plan.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c. Subgroup 4 (CIN measurement) shall be measured only for the initial qualification and after process or design changes
which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of
1 MHz. Tests shall be sufficient to validate the limits defined in table I herein.
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4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at
TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883,
method 1019 and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater
than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be the
pre-irradiation end-point electrical parameter limit at +25°C ±5°C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Neutron irradiation. Neutron irradiation for devices 04, 05, and 06 shall be conducted in wafer form using a neutron
fluence of approximately 1 x 1014 neutrons/cm2.
4.4.4.3 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with method
1020 of MIL-STD-883 and as specified herein (see 1.4 herein). Tests shall be performed on devices, SEC, or approved
test structures at technology qualification and after any design or process changes which may affect the RHA capability of
the process.
4.4.4.4 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with method 1021 of
MIL-STD-883 and herein (see 1.4 herein).
a.
Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b.
Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
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TABLE IIA. Electrical test requirements.
Subgroups
(in accordance with MIL-PRF-38535,
table III)
Subgroups
(in accordance with
MIL-STD-883, method
5005, table I)
Test requirements
Device class M
Device class Q
Interim electrical parameters
(see 4.2)
1,7,9
Final electrical parameters
(see 4.2)
1,2,3,7,8,9,10,11
1/
Group A test requirements
(see 4.4)
1,2,3,4,7,8,9,10,11
Device class V
1,7,9
1,7,9
1,2,3,7,8,9,10,11
1/
1,2,3,7,8,9,10,11
2/ 3/
1,2,3,4,7,8,9,10,11
1,2,3,4,7,8,9,10,11
Group C end-point electrical
parameters (see 4.4)
1,2,3,7,8,9,10,11
1,2,3,7,8,9,10,11
1,2,3,7,8,9,10,11
3/
Group D end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
1,7,9
Group E end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
1,7,9
1/ PDA applies to subgroups 1 and 7.
2/ PDA applies to subgroups 1, 7, 9, and deltas.
3/ Delta limits, as specified in table IIB, shall be required where specified, and the delta limits shall be completed
with reference to the zero hour electrical parameters (see table I).
TABLE IIB. Burn-in and operating life test Delta parameters (+25°C).
Parameter
Symbol
Delta Limits
Supply current
IDD
±1.0 µA
ON resistance
VDD = 10 V
RONDEL
±20%
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4.4.4.5 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.4 herein). SEP testing shall
be performed on a technology process on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by
the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup
characteristics. The recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ≥ 100 errors or ≥ 106 ions/cm2.
2
5
2
c. The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 microns in silicon.
e. The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f. Bias conditions shall be defined by the manufacturer for latchup measurements.
g. Test four devices with zero failures.
TABLE III. Irradiation test connections. 1/
Device types
Open
Ground
VDD = 10 V ±0.5 V
01 and 04
3
7, 8
1, 2, 4, 5, 6, 9, 10, 11, 12,
13, 14, 15, 16
Device types
Open
Ground
VDD = 10 V ±0.5 V
02 and 05
3, 13
7, 8
1, 2, 4, 5, 6, 9, 10, 11, 12,
14, 15, 16
Device types
Open
Ground
VDD = 10 V ±0.5 V
03 and 06
4, 14, 15
7, 8
1, 2, 3, 5, 6, 9, 10, 11, 12,
13, 16
1/ Each pin except VDD and GND will have a series resistor of 47KΩ ±5%, for irradiation testing.
4.5 Methods of inspection. Methods of inspection shall be as specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
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6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
96651
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash
(-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
4051B
02
4052B
03
4053B
04
4051BN
05
4052BN
06
4053BN
Circuit function
Radiation hardened CMOS, single
8-channel multiplexer
Radiation hardened CMOS, differential
4-channel multiplexer
Radiation hardened CMOS, triple
2-channel multiplexer
Radiation hardened CMOS, single
8-channel multiplexer with neutron
irradiated die
Radiation hardened CMOS, differential
4-channel multiplexer with neutron
irradiated die
Radiation hardened CMOS, triple
2-channel multiplexer with neutron
irradiated die
A.1.2.3 Device class designator.
Device class
Q or V
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01, 04
02, 05
03, 06
A-1
A-2
A-3
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01, 04
02, 05
03, 06
A-1
A-2
A-3
A.1.2.4.3 Interface materials.
Die type
Figure number
01, 04
02, 05
03, 06
A-1
A-2
A-3
A.1.2.4.4 Assembly related information.
Die type
Figure number
01, 04
02, 05
03, 06
A-1
A-2
A-3
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specifications, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883
- Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the
Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figures A-1, A-2,
and A-3.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figures A-1, A-2, and A-3.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figures A-1, A-2, and
A-3.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on
figures A-1, A-2, and A-3.
A.3.2.5 Truth tables. The truth tables shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.4 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
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APPENDIX A
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A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone
(614) 692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have
agreed to this drawing.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
Die physical dimensions.
Die size:
Die thickness:
2261 x 2591 microns.
20 ±1 mils.
Die bonding locations and electrical functions.
NOTE: Pad numbers reflect terminal numbers when placed in case outlines E, X (see figure 1).
FIGURE A-1
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
Interface materials.
Top metallization:
Al
11.0kÅ – 14.0kÅ
Backside metallization:
None
Glassivation.
Type:
Thickness:
PSG
10.4kÅ – 15.6kÅ
Substrate:
Single Crystal Silicon.
Assembly related information.
Substrate potential:
Floating or tied to VDD.
Special assembly instructions:
Bond pad #16 (VDD) first.
FIGURE A-1 – Continued.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
Die physical dimensions.
Die size:
Die thickness:
2159 x 2235 microns.
20 ±1 mils.
Die bonding locations and electrical functions.
NOTE: Pad numbers reflect terminal numbers when placed in case outlines E, X (see figure 1).
FIGURE A-2
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
Interface materials.
Top metallization:
Al
11.0kÅ – 14.0kÅ
Backside metallization:
None
Glassivation.
Type:
Thickness:
PSG
10.4kÅ – 15.6kÅ
Substrate:
Single Crystal Silicon.
Assembly related information.
Substrate potential:
Floating or tied to VDD.
Special assembly instructions:
Bond pad #16 (VDD) first.
FIGURE A-2 – Continued.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
Die physical dimensions.
Die size:
Die thickness:
2286 x 2108 microns.
20 ±1 mils.
Die bonding locations and electrical functions.
NOTE: Pad numbers reflect terminal numbers when placed in case outlines E, X (see figure 1).
FIGURE A-3
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96651
A
REVISION LEVEL
D
SHEET
26
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96651
Interface materials.
Top metallization:
Al
11.0kÅ – 14.0kÅ
Backside metallization:
None
Glassivation.
Type:
Thickness:
PSG
10.4kÅ – 15.6kÅ
Substrate:
Single Crystal Silicon.
Assembly related information.
Substrate potential:
Floating or tied to VDD.
Special assembly instructions:
Bond pad #16 (VDD) first.
FIGURE A-3 – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96651
A
REVISION LEVEL
D
SHEET
27
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 06-11-08
Approved sources of supply for SMD 5962-96651 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
5962R9665101VEC
5962R9665101VXC
5962R9665101V9A
5962R9665102VEC
5962R9665102VXC
5962R9665102V9A
5962R9665103VEC
5962R9665103VXC
5962R9665103V9A
5962R9665104VEC
5962R9665104VXC
5962R9665104V9A
5962R9665105VEC
5962R9665105VXC
5962R9665105V9A
5962R9665106VEC
5962R9665106VXC
5962R9665106V9A
Vendor
CAGE
number
34371
34371
34371
34371
34371
34371
34371
34371
34371
3/
34371
3/
3/
3/
3/
3/
3/
3/
Vendor
similar
PIN 2/
CD4051BDMSR
CD4051BKMSR
CD4051BHSR
CD4052BDMSR
CD4052BKMSR
CD4052BHSR
CD4053BDMSR
CD4053BKMSR
CD4053BHSR
CD4051BDNSR
CD4051BKNSR
CD4051BHNSR
CD4052BDNSR
CD4052BKNSR
CD4052BHNSR
CD4053BDNSR
CD4053BKNSR
CD4053BHNSR
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed
contact the vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance
requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
2401 Palm Bay Blvd
P O Box 883
Melbourne, FL 32902-0883
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.