DATASHEET

CD4555BMS
CD4556BMS
CMOS Dual Binary to 1 of 4
Decoder/Demultiplexers
December 1992
Features
Pinouts
CD4556BMS
TOP VIEW
• High Voltage Type (20V Rating)
• CD4555BMS: Outputs High on Select
• CD4556BMS: Outputs Low on Select
E
1
16 VDD
A
2
15 E
B
3
14 A
Q0
4
13 B
• 100% Tested for Quiescent Current at 20V
Q1
5
12 Q0
• Standardized, Symmetrical Output Characteristics
Q2
6
11 Q1
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
Q3
7
10 Q2
VSS
8
9 Q3
• Expandable with Multiple Packages
1/2 OF DUAL
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
E
1
16 VDD
• 5V, 10V and 15V Parametric Ratings
A
2
15 E
1/2 OF DUAL
CD4555BMS
TOP VIEW
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
1/2 OF DUAL
Applications
• Decoding
B
3
14 A
Q0
4
13 B
Q1
5
12 Q0
Q2
6
11 Q1
Q3
7
10 Q2
VSS
8
9 Q3
1/2 OF DUAL
• Code Conversion
• Demultiplexing (Using Enable Input as a Data Input
Functional Diagrams
• Memory Chip-Enable Selection
VDD
• Function Selection
Description
CD4555BMS and CD4556BMS are dual one-of-four decoders/demultiplexers. Each decoder has two select inputs (A
and B), an Enable input (E), and four mutually exclusive outputs. On the CD4555BMS the outputs are high on select; on
the CD4556BMS the outputs are low on select.
When the Enable input is high, the outputs of the
CD4555BMS remain low and the outputs of the
CD4556BMS remain high regardless of the state of the
select inputs A and B. The CD4555BMS and CD4556BMS
are similar to types MC14555 and MC14556, respectively.
A
B
E
4
5
6
7
A
B
E
14
13
15
12
11
10
9
VSS
VDD
A
B
E
A
B
E
*H46
†H4T
H1E
H6W
†CD4556B Only
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
8
CD4555BMS
The CD4555BMS and CD4556BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4555B Only
16
2
3
1
16
2
3
1
4
5
6
7
14
13
15
12
11
10
9
VSS
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
8
CD4556BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1249
File Number
3346
Specifications CD4555BMS, CD4556BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
VOL15
VOH15
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1, 2, 3
+25oC,
+125oC,
-55oC
-
50
mV
1, 2, 3
+25oC,
+125oC,
-55oC
14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
Output Current (Sink)
Output Current (Source)
IOL15
IOH5A
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
IOH15
VNTH
VPTH
F
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-1250
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4555BMS, CD4556BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
Propagation Delay
A or B Input to any Output
TPHL1
TPLH1
Propagation Delay
E to any Output
Transition Time
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
10, 11
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
440
ns
-
594
ns
-
400
ns
-
540
ns
-
200
ns
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
-55oC,
+25oC
MIN
MAX
UNITS
µA
-
5
+125oC
-
150
µA
-55oC, +25oC
-
10
µA
+125oC
-
300
µA
-
10
µA
+125oC
-
600
µA
+25oC, +125oC,
-
50
mV
-55oC,
+25oC
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VIL
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
1, 2
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
+25oC, +125oC,
-
3
V
7
-
V
-55oC
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
7-1251
1, 2
+25oC, +125oC,
-55oC
Specifications CD4555BMS, CD4556BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Propagation Delay
A or B Input to any Output
TPHL1
TPLH1
Propagation Delay
E to any Output
TPHL2
TPLH2
Transition Time
VDD = 10V
CIN
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
-
190
ns
o
VDD = 15V
1, 2, 3
+25 C
-
140
ns
VDD = 10V
1, 2, 3
+25oC
-
170
ns
1, 2, 3
+25
oC
-
130
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
oC
-
7.5
pF
VDD = 15V
TTHL
TTLH
Input Capacitance
CONDITIONS
Any Input
1, 2
+25
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
CONDITIONS
NOTES
VDD = 20V, VIN = VDD or GND
TEMPERATURE
1, 4
+25o
o
C
MIN
MAX
UNITS
-
25
µA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1, 4
+25 C
-2.8
-0.2
V
N Threshold Voltage
Delta
∆VTN
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
7-1252
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD4555BMS, CD4556BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Final Test
Group A
Group B
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
4 - 7, 9 - 12
2, 14
3, 13
PART NUMBER CD4555BMS & CD4556BMS
Static Burn-In 1
Note 1
4 - 7, 9 - 12
1 - 3, 8, 13 - 15
16
Static Burn-In 2
Note 1
4 - 7, 9 - 12
8
1 - 3, 13 - 16
Dynamic BurnIn Note 1
-
1, 8, 15
16
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagrams
4(12)
2(14)
4(12)
2(14)
Q0
A
Q0
A
*
5(11)
*
Q1
3(13)
1(15)
*
6(10)
B
Q2
*
E
Q1
3(13)
6(10)
B
5(11)
Q2
*
7(9)
1(15)
Q3
E
VDD
*
*ALL INPUTS PROTECTED BY CMOS
7(9)
Q3
VDD
*ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
PROTECTION NETWORK
VSS
FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
VSS
FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
7-1253
CD4555BMS, CD4556BMS
TRUTH TABLE
INPUTS ENABLE SELECT
OUTPUTS CD4555BMS
OUTPUTS CD4556BMS
E
B
A
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
Logic 1 ≡ High
Logic 0 ≡ Low
X = Don’t Care
30
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
0
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-15V
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1254
CD4555BMS, CD4556BMS
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
Typical Performance Characteristics
250
200
SUPPLY VOLTAGE (VDD) = 5V
150
10V
100
15V
50
0
20
250
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
15V
0
TRANSITION TIME (tTHL, tTLH) (ns)
200
ANY INPUT
150
E INPUT
50
10
15
100
10V
15V
50
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CPACITANCE
106
DYNAMIC POWER DISSIPATION (PD) (µW)
100
SUPPLY VOLTAGE (VDD) = 5V
150
20
FIGURE 9. TYPICAL PROPAGATION DELAY TIME vs SUPPLY
VOLTAGE
AMBIENT TEMPERATURE (TA) = +25oC
5
10
SUPPLY VOLTAGE (VDD) = 15V
LOAD CAPACITANCE (CL) = 50pF
103
VDD = 10V
CL = 50pF
102
VDD = 10V
CL = 15pF
10
VDD = 5V
CL = 50pF
1
10-1
80
200
SUPPLY VOLTAGE (VDD) = 5V
104
60
AMBIENT TEMPERATURE (TA) = +25oC
250
5
40
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (E INPUTS TO ANY OUTPUT)
300
0
20
LOAD CAPACITANCE (CL) (pF)
AMBIENT TEMPERATURE (TA) = +25oC
100
10V
50
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (A OR B INPUT TO ANY OUTPUT)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
2 4 68
2 4 68
1
2 4 68
10
102
2 4 68
103
2 4 68
104
INPUT FREQUENCY (f) (kHz)
FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY
7-1255
CD4555BMS, CD4556BMS
20ns
20ns
20ns
90%
50%
VDD
INPUT B
90%
50%
10%
VSS
10%
20ns
VDD
INPUT B
VSS
tPHL
tPLH
tPLH
tPHL
90%
50%
VDD
90%
50%
VDD
OUTPUT Q3
10%
VSS
10%
VSS
OUTPUT Q3
tTHL
tTLH
tTLH
tTHL
fI = 1MHz, 50% DUTY CYCLE
fI = 1MHz, 50% DUTY CYCLE
FIGURE 12. CD4555BMS B INPUT TO Q3 OUTPUT DYNAMIC
SIGNAL WAVEFORMS
20ns
FIGURE 13. CD4556BMS B INPUT TO Q3 OUTPUT DYNAMIC
SIGNAL WAVEFORMS
20ns
20ns
20ns
VDD
90%
VDD
90%
50%
INPUT E
10%
VSS
tPHL
10%
VSS
tPLH
tPLH
90%
50%
10%
tTHL
INPUT E
50%
tPHL
VDD
90%
VDD
OUTPUT Q3
50%
OUTPUT Q3
VSS
10%
VSS
tTLH
tTLH
tTHL
fI = 1MHz, 50% DUTY CYCLE
fI = 1MHz, 50% DUTY CYCLE
FIGURE 14. CD4555BMS E INPUT TO Q3 OUTPUT DYNAMIC
SIGNAL WAVEFORMS
FIGURE 15. CD4556BMS E INPUT TO Q3 OUTPUT DYNAMIC
SIGNAL WAVEFORMS
Applications
TRUTH TABLE
1/6 CD4555BMS
SELECT
INPUTS
SELECT INPUTS
A
A
Q0
Q1
B
DATA
B
Q2
E
Q3
Q0
OUTPUTS
B
A
Q0
Q1
Q2
Q3
0
0
DATA
0
0
0
Q2
0
1
0
DATA
0
0
Q3
1
0
0
0
DATA
0
1
1
0
0
0
DATA
Q1
OUTPUTS
1/6 CD4069BMS
FIGURE 16. 1 OF 4 LINE DATA DEMULTIPLEXER USING
CD4555BMS
7-1256
CD4555BMS, CD4556BMS
Applications (Continued)
CD4555BMS
TRUTH TABLE
Q0
A
A
Q1
DECODER INPUTS
Q2
B
A
0
1
2
3
4
5
6
7
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
Q4
1
0
0
0
0
0
0
1
0
0
0
Q5
1
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
Q2
Q3
E
Q3
OUTPUTS
A
Q0
Q1
B
Q2
Q6
Q3
E
C
Q OUTPUTS
C
Q1
B
B
INPUTS
Q0
Q7
1/6 CD4069BMS
OR EQUIV
FIGURE 17. 1 OF 8 DECODER USING CD4555BMS
CD4555BMS
A
A
Q0
Q1
B
B
DECODER INPUTS
Q2
E
Q3
A
Q0
Q1
B
Q2
E
C
A
Q3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
OUTPUTS
Q1
D
E
B
Q2
E
A
Q3
Q0
Q1
B
Q2
1/2 CD4556BMS
E
Q3
A
Q0
Q1
B
Q2
E
Q3
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
FIGURE 18. 1 OF 16 DECODER USING CD4555BMS AND CD4556BMS
7-1257
CD4555BMS, CD4556BMS
TRUTH TABLE
INPUTS
Q OUTPUTS
E
D
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X = Don’t Care
Chip Dimensions and Pad Layouts
CD4555BMSH
CD4556BMSH
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1258
CD4555BMS, CD4556BMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
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TEL: (32) 2.724.2111
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1259
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