DATASHEET

CD4043BMS
CD4044BMS
CMOS Quad 3 State R/S Latches
December 1992
Features
Pinout
• High Voltage Types (20V Rating)
CD4043BMS
TOP VIEW
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
Q4 1
16 VDD
Q1 2
15 R4
R1 3
14 S4
S1 4
13 NC
ENABLE 5
12 S3
• Standardized Symmetrical Output Characteristics
S2 6
11 R3
• 100% Tested for Quiescent Current at 20V
R2 7
10 Q3
VSS 8
9 Q2
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range;
- 100nA at 18V and 25oC
NC = NO CONNECTION
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Q4 1
16 VDD
NC 2
15 S4
Applications
S1 3
14 R4
CD4044BMS
TOP VIEW
R1 4
13 Q1
ENABLE 5
12 R3
R2 6
11 S3
S2 7
10 Q3
VSS 8
9 Q2
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
• General Digital Logic
• CD4043BMS for Positive Logic Systems
NC = NO CONNECTION
• CD4044BMS for Negative Logic Systems
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4043B Only
*H4T
†H4T
*H1C
†HIE
*H3X †H6W
†CD4044B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-876
File Number
3311
Specifications CD4043BMS, CD4044BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
Input Leakage Current
SYMBOL
IDD
IIL
IIH
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
2
µA
2
+125 C
-
200
µA
VDD = 18V, VIN = VDD or GND
3
-55oC
-
2
µA
VIN = VDD or GND
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
VDD = 18V
3
-55oC
-100
-
nA
VDD = 20
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
-
50
mV
VIN = VDD or GND
VDD = 20
VDD = 18V
o
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC,
+125oC,
-55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Functional
F
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
Tri-State Output
Leakage
IOZL
VIN = VDD or GND
VOUT = 0V
1
+25oC
-0.4
-
µA
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
2
+125oC
-12
-
µA
VDD = 18V
3
-55oC
-0.4
-
µA
VDD = 20V
1
+25oC
-
0.4
µA
2
+125oC
-
12
µA
3
-55oC
-
0.4
µA
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-877
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4043BMS, CD4044BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Set or Reset to Q
SYMBOL
TPHL
TPLH
GROUP A
SUBGROUPS TEMPERATURE
CONDITIONS
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
Propagation Delay
3 - State Enable to Q
TPHZ
TPZH
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
Propagation Delay
3 - State Enable to Q
TPLZ
TPZL
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
9
10, 11
9
10, 11
9
10, 11
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
300
ns
-
405
ns
-
230
ns
-
311
ns
-
180
ns
-
243
ns
-
200
ns
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
1, 2
o
o
-55 C, +25 C
Output Voltage
VOL
VDD = 5V, No Load
1, 2
UNITS
-
1
µA
-
30
µA
-
2
µA
-
60
µA
-
2
µA
+125oC
-
120
µA
+25oC, +125oC,
-
50
mV
+125
1, 2
MAX
-55oC, +25oC
oC
VDD = 15V, VIN = VDD or GND
MIN
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 10V, VOUT = 0.5V
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
1, 2
VDD =15V, VOUT = 13.5V
7-878
1, 2
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
Specifications CD4043BMS, CD4044BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Input Voltage Low
SYMBOL
VIL
CONDITIONS
VDD = 10V, VOH > 9V, VOL < 1V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+25oC, +125oC,
-
3
V
-55oC
Input Voltage High
VIH
Propagation Delay
Set or Reset to Q
TPLH
TPHL
Propagation Delay
3 State Enable to Q
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
+25oC, +125oC,
-55oC
7
-
V
1, 2, 3
+25oC
-
140
ns
1, 2, 3
o
+25 C
-
100
ns
VDD = 10V
1, 2, 4
+25
oC
-
110
ns
VDD = 15V
1, 2, 4
+25oC
-
80
ns
o
-
100
ns
o
VDD = 15V
TPHZ
TPZH
1, 2
Propagation Delay
3 State Enable to Q
TPLZ
TPZL
VDD = 10V
VDD = 15V
1, 2, 4
+25 C
-
70
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
TW
VDD = 5V
1, 2, 3
+25oC
-
160
ns
VDD = 10V
1, 2, 3
+25oC
-
80
ns
Minimum Set or Reset
Pulse Width
1, 2, 4
VDD = 15V
Input Capacitance
CIN
Any Input
+25 C
o
1, 2, 3
+25 C
-
40
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
∆VTP
Functional
F
CONDITIONS
NOTES
TEMPERATURE
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
VDD = 10V, ISS = -10µA
1, 4
+25oC
VDD = 10V, ISS = -10µA
1, 4
+25oC
VSS = 0V, IDD = 10µA
1, 4
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
MAX
UNITS
-
7.5
µA
-2.8
-0.2
V
-
±1
V
+25oC
0.2
2.8
V
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
± 0.2µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
7-879
MIN
Specifications CD4043BMS, CD4044BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
1, 7, 9
100% 5004
1, 7, 9, Deltas
IDD, IOL5, IOH5A
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group A
Group B
100% 5004
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
1, 2, 9, 12
4, 6, 12, 14
3, 7, 11, 15
1, 9, 10, 13
4, 6, 12, 14
3, 7, 11, 15
PART NUMBER CD4043BMS
Static Burn-In 1
Note 1
1, 2, 9, 10, 13
3 - 8, 11, 12, 14,
15
16
Static Burn-In 2
Note 1
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
Dynamic BurnIn Note 1
13
8
5, 16
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
Irradiation
Note 2
PART NUMBER CD4044BMS
Static Burn-In 1
Note 1
1, 2, 9, 10, 13
3 - 8, 11, 12, 14,
15
16
Static Burn-In 2
Note 1
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
Dynamic BurnIn Note 1
2
8
5, 16
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-880
Specifications CD4043BMS, CD4044BMS
Functional Diagram
VDD
VDD
16
16
S1
4
R1
3
S2
6
R2
7
S3
12
R3
11
S4
14
R4
ENABLE
15
LATCH
1
2
LATCH
2
9
LATCH
3
10
LATCH
4
1
5
13
R1
4
S1
3
R2
6
S2
7
R3
12
S3
11
R4
14
S4
15
Q1
Q2
Q3
Q4
ENABLE
NC
LATCH
1
13
Q1
LATCH
2
9
Q2
LATCH
3
10
Q3
LATCH
4
1
Q4
2
NC
5
8
8
VSS
VSS
CD4043BMS
CD4044BMS
Logic Diagram
EQUIVALENT
NOR LATCH
E
EQUIVALENT
NAND LATCH
VDD
S1
*
E
VDD
S1
*
4
3
Q1
Q1
2
13
R1
*
R1
3
*
E
E
*
5
VSS
4
E
E
*
5
E
E
VDD
E
VSS
E
VDD
*ALL INPUTS ARE PROTECTED
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
BY CMOS PROTECTION
NETWORK
VSS
VSS
CD4043BMS
CD4044BMS
TRUTH TABLE
CD4043BMS
CD4044BMS
S
R
E
Q
S
R
E
Q
X
X
O
OC*
X
X
O
OC*
O
O
1
NC**
1
1
1
NC**
1
O
1
1
O
1
1
1
O
1
1
O
1
O
1
O
1
1
1
∆
O
O
1
∆∆
* Open Circuit
* Open Circuit
** No Change
** No Change
∆ Dominated by S = 1 input
∆∆ Dominated by R = O input
7-881
CD4043BMS, CD4044BMS
30
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
TRANSITION TIME (tTHL, tTLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
20
-15
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
200
0
0
-10
-15V
AMBIENT TEMPERATURE (TA) = +25oC
50
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
150
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
175
150
SUPPLY VOLTAGE (VDD) = 5V
125
100
10V
75
50
15V
25
0
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
10
20
30
40
50
60
70
80
90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - SET, RESET, to Q, Q
7-882
CD4043BMS, CD4044BMS
POWER DISSIPATION PER DEVICE (PD) (µW)
Typical Performance Characteristics
106
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
105
104
SUPPLY VOLTAGE (VDD) = 15V
103
10V
102
10V
5V
10
CL =15pF
CL = 50pF
1
103
104
105
106
107
INPUT FREQUENCY (fI) (kHz)
FIGURE 7. TYPICAL POWER DISSIPATION vs FREQUENCY
VDD
1MΩ
VDD
OUTPUT
S
Q
LATCH
R
1MΩ
OUTPUT
S
Q
LATCH
R
1MΩ
1MΩ
VDD
CD4044BMS
CD4043BMS
FIGURE 8. SWITCH BOUNCE ELIMINATOR
TEST
IN
IN
A
tPHZ
VDD
VSS
VSS
tPLZ
VSS
VDD
VDD
VDD
1
16
2
15
3
4
ENABLE
14
tPZH
12
6
11
7
10
8
9
VSS
VSS
50%
50%
IN
tPZL
VSS
VDD
VDD
IN
Z = HIGH IMPEDANCE
1KΩ
A
VSS
POINT A
(IN = VDD, IN = VSS)
tPHZ
10%
POINT A
(IN = VSS, IN = VDD)
90%
tPZL
CL = 50pF
≈ 2/3 VDD
≈ 1/3 VDD
10%
tPLZ
VSS
FIGURE 9. ENABLE PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORM
7-883
VDD
90%
tPZH
13
5
VDD
ENABLE
≈ 2/3 VDD
≈ 1/3 VDD
CD4043BMS
1
BUS A
2
5
6
8
9
12
13
CD4001
3
4
10
11
1 OF 4
2
4
6
12
14
3
7
11
15
9
CD4043
10
1
LOAD A
5
ENABLE A
1
BUS B
CD4001
3
4
10
11
2
5
6
8
9
12
13
2
4
6
12
14
3
7
11
15
9
CD4043
10
1
LOAD B
5
3
2
5
4
ENABLE B
1
BUS C
CD4001
3
4
10
11
2
5
6
8
9
12
13
9
CD4043
10
1
LOAD C
5
ENABLE C
1
BUS D
2
5
6
8
9
12
13
CD4001
3
4
10
11
2
4
6
12
14
3
7
11
15
6
9
10
2
4
6
12
14
3
7
11
15
7
9
CD4043
10
1
LOAD D
5
ENABLE D
RESET
FIGURE 10. MULTIPLE BUS STORAGE
7-884
2/3 CD4009
OUTPUT
DATA
BUS
CD4043BMS
Chip Dimensions and Pad Layouts
CD4043BMSH
CD4044BMSH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
885
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Similar pages