CD4099BMS CMOS 8-Bit Addressable Latch December 1992 Features Pinout • High Voltage Type (20V Rating) CD4099BMS TOP VIEW • Serial Data Input • Active Parallel Output • Storage Register Capability Q7 1 16 VDD RESET 2 15 Q6 DATA 3 14 Q5 • Master Clear • Can Function as Demultiplexer WRITE DISABLE 4 13 Q4 • 100% Tested for Quiescent Current at 20V A0 5 12 Q3 • 5V, 10V and 15V Parametric Ratings A1 6 11 Q2 • Standardized Symmetrical Output Characteristics A2 7 10 Q1 VSS 8 9 Q0 • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Functional Diagram • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” WRITE DISABLE Applications DATA • Multi-Line Decoders A0 • A/D Converters A1 Description A2 4 9 3 10 11 5 8 6 DECODER 8 LATCHES 7 13 14 CD4099BMS 8-bit addressable latch is a serial input, parallel output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. 12 15 2 RESET 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VDD = 16 VSS = 8 A master RESET input is available, which resets all bits to a logic “0” level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1 of 8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic “0” level. The CD4099BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-494 File Number 3333 Specifications CD4099BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 - 10 µA +125oC - 1000 µA 3 -55oC - 10 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 1 -55oC VDD = 18V MAX 2 oC 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-495 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4099BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Data to Output SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Reset to Output TPHL3 VDD = 5V, VIN = VDD or GND Transition Time 9 10, 11 Propagation Delay Write Disable to Output Propagation Delay Address to Output GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 400 ns - 540 ns - 400 ns - 540 ns - 350 ns - 473 ns - 450 ns - 608 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC MIN MAX UNITS µA - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA µA -55oC, +25oC - 10 +125oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 7-496 Specifications CD4099BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Output Current (Source) IOH15 Input Voltage Low VIL CONDITIONS VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, - 3 V 1, 2 -55oC Input Voltage High VIH Propagation Delay Data to Output TPHL1 TPLH1 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V 1, 2 +25oC, +125oC, -55oC +7 - V 1, 2, 3 +25oC 1, 2, 3 150 ns - 100 ns o - 160 ns o +25 C Propagation Delay Write Disable to Output TPHL2 TPLH2 VDD = 10V VDD = 15V 1, 2, 3 +25 C - 120 ns Propagation Delay Reset to Output TPHL3 VDD = 10V 1, 2, 3 +25oC - 160 ns o - 130 ns o VDD = 15V Propagation Delay Address to Output Transition Time Minimum Hold time Data to Write Disable Minimum Data Setup Time Data to Write Disable Minimum Pulse Width Data 1, 2, 3 - o TPHL4 TPLH4 VDD = 10V TTHL TTLH TH TS 1, 2, 3 +25 C - 200 ns VDD = 15V 1, 2, 3 +25oC - 150 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 150 MHz VDD = 10V 1, 2, 3 +25oC - 75 MHz VDD = 15V 1, 2, 3 +25oC - 50 MHz 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 50 ns VDD = 15V 1, 2, 3 +25oC - 35 ns VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns VDD = 5V 1, 2, 3 +25oC - 400 ns VDD = 10V 1, 2, 3 +25oC - 200 ns 1, 2, 3 +25oC - 125 ns 1, 2, 3 +25oC - 150 ns VDD = 10V 1, 2, 3 +25oC - 75 ns VDD = 15V 1, 2, 3 +25oC - 50 ns 1, 2 +25oC - 7.5 pF VDD = 15V VDD = 5V VDD = 5V VDD = 15V Minimum Pulse Width Address TW VDD = 15V Minimum Pulse Width Reset Input Capacitance TW CIN +25 C 1, 2, 3 VDD = 10V TW +25 C VDD = 5V Any inputs NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD VNTH CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC 7-497 MIN MAX UNITS - 25 µA -2.8 -0.2 V Specifications CD4099BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL NOTES TEMPERATURE MIN MAX UNITS VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns N Threshold Voltage Delta ∆VTN P Threshold Voltage P Threshold Voltage Delta Functional F CONDITIONS VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-498 Specifications CD4099BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1, 9-15 2-8 16 Static Burn-In 2 Note 1 1, 9-15 8 2-7, 16 Dynamic BurnIn Note 1 - 5-8 16 1, 9-15 8 2-7, 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 1, 9-15 2, 4 3 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram A0 5* A0 A1 A0 A2 A0 A1 6* A0 7* A2 A0 DATA A2 4* D WD R LATCH 1 10 D WD R LATCH 2 11 A0 D WD R LATCH 3 12 D WD R LATCH 4 13 D WD R LATCH 5 14 D WD R LATCH 6 15 D WD R LATCH 7 1 A1 A2 D A0 WRITE DISABLE 9 A1 A2 A2 3* LATCH 0 A1 A1 A1 A2 D WD R A1 A2 WD A0 A1 RESET 2* A2 R A0 A1 A2 A0 R A1 A2 ADDRESS WD p DATA Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VDD n VSS = 8 VDD = 16 p n VSS *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 7-499 CD4099BMS MODE SELECTION 70% 30% A0 UNADDRESSED LATCH WD R 0 0 Follows Data Holds Previous State 0 1 Follows Data Reset to “0” 1 0 1 1 70% 30% A1 ADDRESSED LATCH A2 (Active High 8-Channel Demultiplexer) 70% WD tW Holds Previous State Reset to “0” WD = Write Disable Reset to “0” R = Reset FIGURE 2. DEFINITION OF WRITE DISABLE ON TIME tW 8 A0, A1, A2 WRITE DISABLE 4 tW DATA tH 7 tS 6 RESET tW 5 tP 2 Q0 tP 9 Q7 tP 1 tP tP Q7 tP 3 tP FIGURE 3. MASTER TIMING DIAGRAM 6 A1 7 A2 A3 4 DATA IN 3 A0 Q0 A1 Q1 A2 Q2 WD DATA CD4099BMS 5 A0 Q3 Q4 Q5 Q6 Q7 R 9 10 11 12 13 14 15 1 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7 DO 8 2 CD4099BMS Q0 D Q1 DATA VDD 6 7 * *1/6 CD4069 4 3 A0 Q0 A1 Q1 A2 WD DATA CD4099BMS 5 Q2 Q3 Q4 Q5 Q6 Q7 R 9 10 11 12 13 14 15 1 DO 9 DO 10 A0 A1 A2 A3 Y 1/4 CD4016 IN/OUT 0 1 2 0 S0 WD R DO 11 S5 CD4099BMS D DO 14 S1 S2 1 DO 12 DO 13 3 X IN/OUT 2 DO 15 DO 16 2 VDD FIGURE 4. 1 OF 16 DECODER/DEMULTIPLEXER WD R WD WD Q15 3 FIGURE 5. MULTIPLE SELECTION DECODING - 4 x 4 CROSSPOINT SWITCH 7-500 CD4099BMS VDD VDD t2 5 4 7 AST 470pF (t1 < t2) 8 9 12 6 CD4047 C R 1 2 14 2 OSC 13 OUT R-C 1 CLOCK 10 15 16 R 7 WD CD4099BMS R DATA Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 CD4520 Q1A 3 Q2A 3 330Ω 100 kΩ 4 3 t1 8 9 10 * 9 START CONVERSION 9 Q3A 4 5 5 6 7 A0 A1 A2 10 11 12 13 14 15 1 LSB 1 2 * 3 12 CD4099BMS 11 * 13 OUTPUTS 5 6 * TO DISPLAY VDD 4 7 6 4 10kΩ + 3 CA3130 - 2 MSB 1 5 * CD4001 ** HYCOMP HC210SLD-2R 1 100 kΩ OR EQUIVALENT OUT 8 16 2 3 4 5 6 7 8 R2R LADDER NETWORK** 10kΩ 9 56pF 10 11 12 13 ANALOG IN FIGURE 6. A/D CONVERTER AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 FIGURE 7. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-501 CD4099BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V TRANSITION TIME (tTHL, tTLH) (ns) PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 200 150 10V 50 15V 10 20 30 40 50 60 70 80 90 200 100 100 POWER DISSIPATION PER GATE (PD) (µW) 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 12. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE LOAD CAPACITANCE (CL ) = 15pF CL = 50pF 4 2 4 2 5V 50 AMBIENT TEMPERATURE (TA) = +25oC 105 6 103 10V 0 0 FIGURE 11. TYPICAL PROPAGATION DELAY TIME (DATA TO Qn) vs LOAD CAPACITANCE 6 4 2 SUPPLY VOLTAGE (VDD) = 5V 150 LOAD CAPACITANCE (CL) (pF) 104 6 -15 FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 300 0 SUPPLY VOLTAGE (VDD) = 15V 10V 6 4 2 10V 5V 102 6 4 2 101 100 6 4 2 2 4 68 100 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 100 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 250 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 (Continued) 2 4 68 2 4 68 2 4 68 101 102 103 ADDRESS CYCLE TIME (µs) 104 2 4 68 105 FIGURE 13. TYPICAL DYNAMIC POWER DISSIPATION vs ADDRESS CYCLE TIME 7-502 CD4099BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 File Number 503