DATASHEET

HCS373MS
Radiation Hardened
Octal Transparent Latch, Three-State
September 1995
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)
OE
1
Q0
2
19 Q7
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
D0
3
18 D7
20 VCC
D1
4
17 D6
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
Q1
5
16 Q6
• Latch-Up Free Under Any Conditions
Q2
6
15 Q5
• Military Temperature Range: -55oC to +125oC
D2
7
14 D5
D3
8
13 D4
Q3
9
12 Q4
GND 10
11 LE
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
Description
The Intersil HCS373MS is a Radiation Hardened octal transparent three-state latch with an active-low output enable. The
HCS373MS utilizes advanced CMOS/SOS technology. The outputs are transparent to the inputs when the Latch Enable (LE) is
HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
OE
1
20
VCC
Q0
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
LE
GND
The HCS373MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS373DMSR
-55oC to +125oC
Intersil Class S Equivalent
20 Lead SBDIP
HCS373KMSR
-55oC to +125oC
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
+25oC
Sample
20 Lead SBDIP
HCS373K/Sample
+25oC
Sample
20 Lead Ceramic Flatpack
HCS373HMSR
+25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
346
DB NA
HCS373D/Sample
Spec Number
File Number
518845
2135.2
HCS373MS
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
D
LATCH
OE
D
Q
Q
(2, 5, 6, 9, 12,
15, 16, 19)
LE
COMMON CONTROLS
LE
(11)
OE
(1)
TRUTH TABLE
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
I
L
L
L
h
H
H
X
X
Z
H = High Level, L = Low Level
X = Immaterial,
Z = High Impedance
I = Low voltage level prior to the high-to-low latch enable transition
h = High voltage level prior to the high-to-low latch enable transition
Spec Number
347
518845
Specifications HCS373MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
72oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .100ns Max
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Output Three-State
Leakage
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
750
µA
1
+25oC
7.2
-
mA
2, 3
+125oC, -55oC
6.0
-
mA
1
+25oC
-7.2
-
mA
2, 3
+125oC, -55oC
-6.0
-
mA
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-
±0.5
µA
2, 3
+125oC, -55oC
-
±5.0
µA
1
+25oC
-
±1.0
µA
2, 3
+125oC, -55oC
±50
µA
7, 8A, 8B
+25oC, +125oC, -55oC
-
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
IOZ
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
VCC = 5.5V, VO = 0V or
VCC
VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 2)
LIMITS
-
NOTES:
1. All voltages reference to device GND.
2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
348
518845
Specifications HCS373MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
Data to Qn
LE to Qn
TPLH,
TPHL
TPLH,
TPHL
Enable to Output
TPZL
TPZH
Disable to Output
TPLZ,
TPHZ
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
20
ns
10, 11
+125oC, -55oC
2
24
ns
VCC = 4.5V
VCC = 4.5V
LIMITS
o
9
+25 C
2
24
ns
10, 11
+125oC, -55oC
2
29
ns
VCC = 4.5V
o
9
+25 C
2
25
ns
10, 11
+125oC, -55oC
2
31
ns
VCC = 4.5V
o
9
+25 C
2
20
ns
10, 11
+125oC, -55oC
2
24
ns
VCC = 4.5V
o
9
+25 C
2
25
ns
10, 11
+125oC, -55oC
2
30
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power Dissipation
Input Capacitance
Output Transition Time
Setup Time Data to LE
Hold Time Data to LE
Pulse Width LE
SYMBOL
CPD
CIN
TTHL
TTLH
TSU
TH
TW
(NOTE 1)
CONDITIONS
VCC = 5.0V, f = 1MHz
VCC = 5.0V, f = 1MHz
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
TEMPERATURE
MIN
MAX
UNITS
+25oC
-
57
pF
+125oC, -55oC
-
60
pF
+25oC
-
10
pF
+125oC, -55oC
-
10
pF
+25oC
-
12
ns
+125oC, -55oC
-
18
ns
+25oC
10
-
ns
+125oC, -55oC
15
-
ns
+25oC
5
-
ns
+125oC, -55oC
5
-
ns
+25oC
16
-
ns
+125oC, -55oC
24
-
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
349
518845
Specifications HCS373MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
(NOTES 1, 2)
CONDITIONS
SYMBOL
ICC
200K RAD
LIMITS
TEMPERATURE
MIN
MAX
UNITS
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.75
mA
6.0
-
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25oC
Output Current (Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25oC
-6.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V and 5.5V, VIH = 0.70(VCC)
VIL = 0.30(VCC), IOL = 50µA
+25oC
-
0.1
V
Output Voltage High
VOH
VCC = 4.5V and 5.5V, VIH = 0.70(VCC)
VIL = 0.30(VCC), IOH = -50µA
+25oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±5
µA
-
±50
µA
Input Leakage Current
IIN
Three-State Output
Leakage Current
IOZ
Applied Voltage = 0V or VCC,
VCC = 5.5V
+25oC
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
+25oC
-
-
-
Data to Qn
TPLH,
TPHL
VCC = 4.5V
+25oC
2
24
ns
LE to Qn
TPLH,
TPHL
VCC = 4.5V
+25oC
2
29
ns
Enable to Output
TPZL
VCC = 4.5V
+25oC
2
31
ns
VCC = 4.5V
+25oC
2
24
ns
VCC = 4.5V
+25oC
2
30
ns
TPZH
Disable to Output
TPLZ,
TPHZ
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
12µA
IOL/IOH
5
-15% of 0 Hour
IOZL/IOZH
5
±200nA
PARAMETER
Spec Number
350
518845
Specifications HCS373MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
Group D
READ AND RECORD
ICC, IOL/H
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
NOTES:
1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
1/2 VCC = 3V ± 0.5V
GROUND
VCC = 6V ± 0.5V
50kHz
25kHz
-
20
-
-
-
1, 3, 4, 7, 8, 11, 13,
14, 17, 18, 20
-
-
2, 5, 6, 9, 12, 15, 16,
19
20
11
3, 4, 7, 8, 13,
14, 17, 18
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
2, 5, 6, 9, 12, 15, 16,
19
1, 3, 4, 7, 8, 10, 11,
13, 14, 17, 18
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
2, 5, 6, 9, 12, 15, 16,
19
10
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
1, 10
NOTES:
1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 680Ω ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
2, 5, 6, 9, 12, 15, 16, 19
10
1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group
E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
351
518845
HCS373MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
352
518845
HCS373MS
AC Timing Diagrams
INPUT
LEVEL
LE
VS
VS
VS
TW
INPUT
LEVEL
DATA
VS
DATA
VS
VS
VS
VS
VS
TSU(L)
TH(H)
TPLH
TPHL
TH(L)
TSU(H)
TPHL
TPLH
Qn
VS
VS
LE
FIGURE 1. LATCH ENABLE PROPAGATION DELAYS
VS
VS
FIGURE 2. LATCH ENABLE PREREQUISITE TIMES (DATA
SET-UP AND HOLD)
AC VOLTAGE LEVELS
PARAMETER
VOH
TTLH
TTHL
80%
VOL
20%
80%
20%
OUTPUT
HCS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
FIGURE 3. OUTPUT TRANSITION TIMES
AC Load Circuit
DUT
TEST
POINT
CL
RL
CL = 50pF
RL = 500Ω
Spec Number
353
518845
HCS373MS
Three-State Low Timing Diagram
Three-State Load Circuit
VCC
VIH
VS
OE
INPUT
RL
VIL
TPZL
TEST
POINT
DUT
TPLZ
VOZ
CL
VT
CL = 50pF
VW
OUTPUT
RL = 500Ω
VOL
THREE-STATE LOW VOLTAGE LEVELS
PARAMETER
HCS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VT
2.25
V
VW
0.90
V
GND
0
V
VIL
0
V
Three-State High Timing Diagram
Three-State Load Circuit
DUT
VIH
OE
VS
TEST
POINT
INPUT
VIL
CL
RL
TPHZ
TPZH
VOH
VW
CL = 50pF
VT
OUTPUT
RL = 500Ω
VOZ
THREE-STATE HIGH VOLTAGE LEVELS
PARAMETER
HCS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VT
2.25
V
VW
3.60
V
GND
0
V
VIL
0
V
Spec Number
354
518845
HCS373MS
Die Characteristics
DIE DIMENSIONS:
2747 x 2693µm
METALLIZATION:
Type: SiAl
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS373MS
Q0
(2)
D0
(3)
OE
(1)
Q7
(19)
VCC
(20)
(18) D7
D1 (4)
(17) D6
Q1 (5)
(16) Q6
Q2 (6)
(15) Q5
(14) D5
D2 (7)
(8)
D3
(9)
Q3
(10)
GND
(11)
LE
(12)
Q4
(13)
D4
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCS373 is TA14303A.
Spec Number
355
518845
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