DATASHEET

CD40109BMS
CMOS Quad Low-to-High Voltage Level Shifter
December 1992
Features
Description
• High Voltage Type (20V Rating)
CD40109BMS contains four low-to-high voltage level shifting
circuits. Each circuit will shift a low voltage digital logic input
signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS
to a higher voltage output signal (E, F, G, H) with logical
1 = VDD and logical 0 = VSS.
• Independence of Power Supply Sequence Considerations
- VCC can Exceed VDD
- Input Signals can Exceed Both VCC and VDD
• Up and Down Level Shifting Capability
• Three-State Outputs with Separate Enable Controls
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VCC = 5V, VDD = 10V
- 2V at VCC = 10V, VDD = 15V
• Standardized Symmetrical Output Characteristics
The CD40109BMS, unlike other low-to-high level shifting
circuits, does not require the presence of the high voltage
supply (VDD) before the application of either the low voltage
supply (VCC) or the input signals. There are no restrictions
on the sequence of application of VDD, VCC, or the input
signals. In addition, with one exception there are no
restrictions on the relative magnitudes of the supply voltages
or input signals within the device maximum ratings, provided
that the input signal swings between VSS and at least
0.7VCC; VCC may exceed VDD, and input signals may
exceed VCC and VDD. When operated in the mode
VCC > VDD, the CD40109BMS will operate as a high-to-low
level shifter.
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
The CD40109BMS also features individual three-state output capability. A low level on any of the separately enabled
three-state output controls produces a high impedance state
in the corresponding output.
Applications
The CD40109BMS is supplied in these 16-lead outline
packages:
• High or Low Level Shifting with Three-State Outputs
for Unidirectional or Bidirectional Bussing
• Isolation of Logic Subsystems Using Separate Power
Supplies from Supply Sequencing, Supply Loss and
Supply Regulation Considerations
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
Functional Diagram
Pinout
1 OF 4 UNITS
CD40109BMS
TOP VIEW
VCC
VCC 1
ENABLE A 2
15 ENABLE D
A
A 3
14 D
E 4
13 H
F 5
12 NC
B 6
11 G
ENABLE B 7
10 C
VSS 8
VDD
16 VDD
ENABLE A
LEVEL
SHIFTER
E
LEVEL
SHIFTER
9 ENABLE C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-36
File Number
3196
Specifications CD40109BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
SYMBOL
IDD
IIL
TEMPERATURE
MIN
MAX
1
+25oC
-
2
µA
2
+125oC
-
200
µA
VDD = 18V, VIN = VDD or GND
3
-55oC
-
2
µA
VIN = VDD or GND
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
-
50
mV
VDD = 20V, VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
LIMITS
GROUP A
SUBGROUPS
CONDITIONS (NOTE 1)
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
UNITS
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
-2.8
-0.7
V
0.7
2.8
V
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1
+25oC
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
Functional
F
Input Voltage Low
(Note 2)
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
1, 2, 3
Input Voltage High
(Note 2)
VIH
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
1, 2, 3
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V, VCC = 10V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V, VCC = 10V
Tri-State Output
Leakage
IOZL
VIN = VDD or GND
VOUT = 0V
IOZH
VIN = VDD or GND
VOUT = VDD
V
-55oC
+25oC,
Tri-State Output
Leakage
VOH > VOL <
VDD/2 VDD/2
+125oC, -55oC
-
1.5
V
+25oC, +125oC, -55oC
3.5
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
3
V
1, 2, 3
+25oC, +125oC, -55oC
7
-
V
1
+25oC
-0.4
-
µA
2
+125oC
-12
-
µA
VDD = 18V
3
-55oC
-0.4
-
µA
VDD = 20V
1
+25oC
-
0.4
µA
2
+125oC
-
12
µA
3
-55oC
-
0.4
µA
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-37
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD40109BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
GROUP A
SUBGROUPS TEMPERATURE
SYMBOL
CONDITIONS
Propagation Delay
Data In to Out
Shift Mode L-H
TPHL1
VDD = 10V, VIN = VCC or GND
VCC = 5V (Notes 1, 2)
Propagation Delay
Data In to Out
Shift Mode L-H
TPLH1
Propagation Delay
Data In to Out
Shift Mode H-L
TPHL2
Propagation Delay
Data In to Out
Shift Mode H-L
TPLH2
Transition Time
Shift Mode L-H
TTHL1
TTLH1
VDD = 10V, VIN = VCC or GND
VCC = 5V (Notes 1, 2)
VDD = 5V, VIN = VCC or GND
VCC = 10V (Notes 1, 2)
VDD = 5V, VIN = VCC or GND
VCC = 10V (Notes 1, 2)
VDD = 10V, VIN = VDD or GND
VCC = 5V (Notes 1, 2)
Transition Time
Shift Mode H-L
TTHL2
TTLH2
VDD = 5V, VIN = VDD or GND
VCC = 10V (Notes 1, 2)
Propagation Delay
3-State Shift Mode L-H
TPHZ1
VDD = 10V, VIN = VCC or GND
VCC = 5V (Notes 2, 3)
Propagation Delay
3-State Shift Mode H-L
TPHZ2
Propagation Delay
3-State Shift Mode L-H
TPLZ1
Propagation Delay
3-State Shift Mode H-L
TPLZ2
Propagation Delay
3-State Shift Mode L-H
TPZH1
Propagation Delay
3-State Shift Mode H-L
TPZH2
Propagation Delay
3-State Shift Mode L-H
TPZL1
Propagation Delay
3-State Shift Mode H-L
TPZL2
VDD = 5V, VIN = VCC or GND
VCC = 10V (Notes 2, 3)
VDD = 10V, VIN = VCC or GND
VCC = 5V (Notes 2, 3)
VDD = 5V, VIN = VCC or GND
VCC = 10V (Notes 2, 3)
VDD = 10V, VIN = VCC or GND
VCC = 5V (Notes 2, 3)
VDD = 5V, VIN = VCC or GND
VCC = 10V (Notes 2, 3)
VDD = 10V, VIN = VCC or GND
VCC = 5V (Notes 2, 3)
VDD = 5V, VIN = VCC or GND
VCC = 10V (Notes 2, 3)
9
+25oC
o
o
LIMITS
MIN
MAX
UNITS
-
600
ns
10, 11
+125 C, -55 C
-
810
ns
9
+25oC
-
260
ns
10, 11
+125oC, -55oC
-
351
ns
9
+25oC
-
500
ns
o
o
10, 11
+125 C, -55 C
-
675
ns
9
+25oC
-
460
ns
10, 11
+125oC, -55oC
-
621
ns
9
+25oC
-
100
ns
10, 11
+125oC, -55oC
-
135
ns
o
9
+25 C
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
9
+25oC
-
120
ns
o
o
10, 11
+125 C, -55 C
-
162
ns
9
+25oC
-
400
ns
o
o
10, 11
+125 C, -55 C
-
540
ns
9
+25oC
-
740
ns
10, 11
+125oC, -55oC
-
999
ns
o
9
+25 C
-
500
ns
10, 11
+125oC, -55oC
-
675
ns
9
+25oC
-
640
ns
o
o
10, 11
+125 C, -55 C
-
864
ns
9
+25oC
-
600
ns
o
o
10, 11
+125 C, -55 C
-
810
ns
9
+25oC
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
o
9
+25 C
-
400
ns
10, 11
+125oC, -55oC
-
540
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
1, 2
-55oC,
+25oC
+125oC
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
MAX
UNITS
-
1
µA
-
30
µA
-
2
µA
-
60
µA
-
2
µA
+125oC
-
120
µA
+25oC, +125oC,
-
50
mV
-55oC,
+25oC
-55oC
7-38
MIN
Specifications CD40109BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
NOTES
TEMPERATURE
MIN
MAX
UNITS
Output Voltage
PARAMETER
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
SYMBOL
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VIL
Input Voltage High
VIH
Propagation Delay
Data In to Data Out
Shift Mode L-H
TPHL1
Propagation Delay
Data In to Out
Shift Mode L-H
TPLH1
Propagation Delay
Data In to Out
Shift Mode H-L
TPHL2
Propagation Delay
Data In to Out
Shift Mode H-L
TPLH2
Transition Time
Shift Mode L-H
TTHL1
TTLH1
Transition Time
Shift Mode H-L
Propagation Delay
3-State Shift Mode L-H
Propagation Delay
3-State Shift Mode H-L
Propagation Delay
3-State Shift Mode L-H
TTHL2
TTLH2
TPHZ1
CONDITIONS
VDD = 10V, VOUT = 0.5V
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
1, 2
VDD =15V, VOUT = 13.5V
1, 2
TPLZ1
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
+25oC, +125oC,
-
1.5
V
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
1, 2
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
1, 2
+25oC, +125oC,
-55oC
3.5
-
V
1, 2, 3
+25oC
-
440
ns
VDD = 15V, VCC = 10V
1, 2, 3
+25oC
-
360
ns
VDD = 15V, VCC = 5V
1, 2, 3
+25oC
-
240
ns
VDD = 15V, VCC = 10V
1, 2, 3
+25oC
-
140
ns
VDD = 5V, VCC = 15V
1, 2, 3
+25oC
-
500
ns
VDD = 10V, VCC = 15V
1, 2, 3
+25oC
-
240
ns
VDD = 5V, VCC = 15V
1, 2, 3
+25oC
-
460
ns
VDD = 10V, VCC = 15V
1, 2, 3
+25oC
-
160
ns
VDD = 15V, VCC = 5V
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
80
ns
VDD = 5V, VCC = 15V
1, 2, 3
+25oC
-
200
ns
VDD = 10V, VCC = 15V
1, 2, 3
+25oC
-
100
ns
1, 2, 4
+25oC
-
150
ns
1, 2, 4
+25oC
-
70
ns
VDD = 5V, VCC = 5V
1, 2, 4
+25oC
-
400
ns
VDD = 10V, VCC = 15V
1, 2, 4
+25oC
-
80
ns
1, 2, 4
+25oC
-
600
ns
1, 2, 4
+25oC
-
500
ns
VDD = 15V, VCC = 5V
VDD = 15V, VCC = 10V
VDD = 15V, VCC = 5V
VDD = 15V, VCC = 10V
TPHZ2
+125oC
VDD = 15V, VCC = 5V
VDD = 15V, VCC = 10V
7-39
-55oC
Specifications CD40109BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Propagation Delay
3-State Shift Mode H-L
SYMBOL
TPLZ2
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
VDD = 5V, VCC = 15V
1, 2, 4
+25oC
-
500
ns
1, 2, 4
+25oC
-
260
ns
1, 2, 4
+25oC
-
460
ns
VDD = 15V, VCC = 10V
1, 2, 4
+25oC
-
360
ns
VDD = 5V, VCC = 15V
1, 2, 4
+25oC
-
600
ns
1, 2, 4
+25oC
-
260
ns
1, 2, 4
+25oC
-
160
ns
VDD = 15V, VCC = 10V
1, 2, 4
+25oC
-
80
ns
VDD = 5V, VCC = 15V
1, 2, 4
+25oC
-
400
ns
VDD = 10V, VCC = 15V
1, 2, 4
+25oC
-
80
ns
VDD = 10V, VCC = 15V
Propagation Delay
3-State Shift Mode L-H
TPZH1
Propagation Delay
3-State Shift Mode H-L
TPZH2
VDD = 15V, VCC = 5V
VDD = 10V, VCC = 15V
Propagation Delay
3-State Shift Mode L-H
TPZL1
Propagation Delay
3-State Shift Mode H-L
TPZL2
VDD = 15V, VCC = 5V
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
-
7.5
µA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1, 4
+25oC
-2.8
-0.2
V
N Threshold Voltage
Delta
∆VTN
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VTP
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
± 0.2µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
7-40
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD40109BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
1, 7, 9
100% 5004
1, 7, 9, Deltas
IDD, IOL5, IOH5A
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group A
Group B
100% 5004
READ AND RECORD
Group D
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
9V ± -0.5V
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1 (Note 1)
4, 5, 11-13
2, 3, 6-10, 14, 15
1, 16
Static Burn-In 2 (Note 1)
4, 5, 11-13
8
16
1-3, 4, 7, 9, 10,
14, 15
Dynamic Burn-In (Note 4)
12
8
16
1, 4, 5, 11, 13
4, 5, 11-13
8
1-3, 6, 7, 9, 10,
14-16
Irradiation (Note 2)
50kHz
25kHz
3, 6, 10, 14
(Note 3)
2, 7, 9, 15
(Note 3)
NOTES:
1. Each pin except Pin 1, VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except Pin 1, VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
3. Pin voltage is VDD/2
4. Each pin except Pin 1, VDD and GND will have a series resistor of 4.75K ±5%, VDD = 18V ±0.5V.
Logic Diagram
VCC
*
A
3 (6, 10, 14)
VDD
VDD
TRUTH TABLE
LEVEL
SHIFTER
INPUTS
E
4 (5, 11, 13)
*
ENABLE A
2 (7, 9, 15)
LEVEL
SHIFTER
VSS
VDD
VCC = 1
VDD = 16
VSS = 8
*
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. 1 OF 4 UNITS
7-41
OUTPUTS
A, B, C, D
ENABLE
A, B, C, D
E, F, G, H
0
1
0
1
1
1
X
0
Z
Logic 0 = Low(VSS)
X = Don’t care
Z = High impedance
Logic 1 = VCC at Inputs and VDD at Outputs
CD40109BMS
30
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-10
-15V
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
-15
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
350
HIGH-TO-LOW PROPAGATION
DELAY TIME (tPHL) (ns)
TRANSITION TIME (tTHL, tTLH) (ns)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
50
VCC = 5V, VDD = 10V
300
250
VCC = 5V, VDD = 15V
200
VCC = 10V, VDD = 15V
150
100
50
0
0
20
0
0
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
10
40
70
80
20
30
50
60
LOAD CAPACITANCE (CL) (pF)
90
100
FIGURE 7. TYPICAL HIGH-TO-LOW PROPAGATION DELAY
TIME AS A FUNCTION OF LOAD CAPACITANCE
7-42
CD40109BMS
(Continued)
INPUT SWITCHING VOLTAGE (VSWITCH) (V)
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
LOW-TO-HIGH PROPAGATION
DELAY TIME (tPLH) (ns)
175
150
VCC = 5V, VDD = 10V
125
VCC = 5V, VDD = 15V
100
VCC = 10V, VDD = 15V
75
50
25
0
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (TA) = +25oC
VCC
10
VIN
8
VDD
VOUT
VSS
6
50%
VCC = 15V
ENABLE = VCC
4
VCC = 10V
2
VCC = 5V
0
2.5
100
*VSWITCH
VSS
5
DISSIPATION PER LEVEL SHIFTER (PD) (µW)
SUPPLY VOLTAGE (VDD) (V)
25
20
RECOMMENDED
OPERATING
BOUNDARY
10
5
0
0
5
105 8
20
AMBIENT TEMPERATURE (TA) = +25oC
6
4
2
104
VCC = 5V, VDD = 15V
8
6
4
VCC = 5V, VDD = 10V
VCC = 10V, VDD = 15V
2
103 8
6
4
VCC = 5V, VDD = 10V
2
102
8
6
4
LOAD CAPACITANCE CL = 50pF
CL = 15pF
2
10
10
15
20
25
SUPPLY VOLTAGE (VCC) (V)
2
1
FIGURE 10. HIGH LEVEL SUPPLY VOLTAGE vs LOW LEVEL
SUPPLY VOLTAGE
17.5
FIGURE 9. TYPICAL INPUT SWITCHING AS A FUNCTION OF
HIGH LEVEL SUPPLY VOLTAGE
AMBIENT TEMPERATURE (TA) = +25oC
15
VSWITCH = INPUT VOLTAGE AT
WHICH OUTPUT LEVEL IS 50%
OF VDD - VSS
7.5
10
12.5
15
SUPPLY VOLTAGE (VDD) (V)
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL LOW-TO-HIGH PROPAGATION DELAY
TIME AS A FUNCTION OF LOAD CAPACITANCE
*
4 68
2
10
4 68
2
4 68
2
4 68
102
103
104
INPUT FREQUENCY (fi) (kHz)
2
4 68
105
FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT FREQUENCY
Test Circuit and Waveform
TEST VOLTAGE
VCC
VDD
1
A
INPUT
(SEE
TABLE)
AT A
tPHZ
VCC
VSS
tPLZ
VSS
VDD
tPZL
VSS
VDD
tPZH
VCC
VSS
16
2
15
3
14
4
CHAR
PULSE
GENERATOR
1K
B
AT B
13
5
12
6
11
7
10
8
9
RS (SEE
CL TABLE)
50pF
VCC
ENABLE 50%
INPUT
50%
VSS
tPLZ
OUTPUT
OUTPUT
OUTPUT
VSS
10%
90%
tPHZ
FIGURE 12. OUTPUT ENABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS
7-43
tPZL
VDD
90%
VOL
VOH
10%
VSS
tPZH
CD40109BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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44
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