DATASHEET

HS-6617RH
TM
Data Sheet
August 2000
File Number
Radiation Hardened 2K x 8 CMOS PROM
Features
The Intersil HS-6617RH is a radiation hardened 16K CMOS
PROM, organized in a 2K word by 8-bit format. The chip is
manufactured using a radiation hardened CMOS process,
and is designed to be functionally equivalent to the
HM-6617. Synchronous circuit design techniques combine
with CMOS processing to give this device high speed
performance with very low power dissipation.
• Electrically Screened to SMD # 5962-95708
3033.4
• QML Qualified per MIL-PRF-38535 Requirements
• Total Dose . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
• Latch-Up Free. . . . . . . . . . . . . . . . . . . . >1 x 1012 rad(Si)/s
• Field Programmable
On chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structure, such as the
HS-80C85RH or HS-80C86RH. The output enable control
(G) simplifies microprocessor system interfacing by allowing
output data bus control, in addition to, the chip enable
control. Synchronous operation of the HS-6617RH is ideal
for high speed pipe-lined architecture systems and also in
synchronous logic replacement functions.
• Functionally Equivalent to HM-6617
Applications for the HS-6617RH CMOS PROM include low
power microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and
synchronous logic replacement.
• On Chip Address Latches
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• Military Temperature Range . . . . . . . . . . . -55oC to 125oC
• Pin Compatible with Intel 2716
• Low Standby Power . . . . . . . . . . . . . . . . . . . 1.1mW (Max)
• Low Operating Power . . . . . . . . . . . . 137.5mW/MHz (Max)
• Fast Access Time . . . . . . . . . . . . . . . . . . . . . . 100ns (Max)
• TTL Compatible Inputs/Outputs
• Synchronous Operation
• Three-State Outputs
• Nicrome Fuse Links
• Easy Microprocessor Interfacing
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95708. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.htm
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(oC)
5962R9570801QJC
HS1-6617RH-8
-55 to 125
5962R9570801QXC
HS9-6617RH-Q
-55 to 125
5962R9570801VJC
HS1-6617RH-Q
-55 to 125
5962R9570801VXC
HS9-6617RH-Q
-55 to 125
HS1-6617RH/PROTO
HS1-6617RH/PROTO
-55 to 125
HS9-6617RH/PROTO
HS9-6617RH/PROTO
-55 to 125
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HS-6617RH
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
(SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
A7
1
24 VDD
A7
1
24
VDD
A6
2
23 A8
A6
2
23
A8
A5
3
4
5
22
21
20
A5
3
22 A9
A4
4
21 P
A4
A3
A3
5
20 G
A2
6
19 A10
A2
A1
6
7
19
18
7
18 E
A0
Q0
8
9
17
A1
16
A9
P
G
A10
E
Q7
Q6
A0
8
17 Q7
Q0
9
10
11
15
14
Q5
Q4
16 Q6
Q1
Q2
GND
12
13
Q3
Q1 10
15 Q5
Q2 11
14 Q4
GND 12
13 Q3
PIN
DESCRIPTION
A
Address Input
Q
Data Output
E
Chip Enable
G
Output Enable
P
Program Enable (P Hardwired to VDD, except during programming)
Functional Diagram
MSB
A10
A9
A8
A7
A6
A5
A4
7
A
LATCHED
GATED
ADDRESS
ROW
DECODER
REGISTER
7
A
128 x 128
MATRIX
128
1 OF 8
LSB
E
E
16 16
16
16
16
16
16
GATE COLUMN
8
P
16
8
DECODER
Q0 - Q7
PROGRAMMING, & DATA
E
OUTPUT CONTROL
E
A
G
E
A
4
4
LATCHED ADDRESS
REGISTER
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF G
P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING
MSB
LSB
A3
A2
A1
TRUTH TABLE
2
E
G
MODE
0
0
Enabled
0
1
Output Disabled
1
X
Disabled
A0
ALL LINES POSITIVE LOGIC:
ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH
OUTPUT ACTIVE
HS-6617RH
Timing Waveform
TAVQV
3.0V
1.5V
1.5V
VALID
ADDRESS
VALID
ADDRESSES
0V
ADDRESSES
TELEL
TAVEL
TELAX
TELEH
3.0V
1.5V
1.5V
1.5V
1.5V
E
0V
TEHEL
TELQV
G
TEHQZ
TGLQV
3.0V
1.5V
1.5V
0V
TGLQX
TGHQZ
TELQX
DATA
OUTPUT
Q0 - Q7
VALID
DATA
TS
FIGURE 1. READ CYCLE
Burn-In Circuits
HS-6617RH 24 LEAD SBDIP AND FLATPACK
HS-6617RH 24 LEAD SBDIP AND FLATPACK
C1
C1
VDD
A7
VDD
A6
VDD
A5
VDD
A4
VDD
A3
VDD
A2
VDD
VDD
1
2
23
3
22
4
21
5
20
6
A1
19
7
A0
Q0
Y
24
Q1
18
8
17
9
16
10
Q2
GND
15
11
14
12
13
VDD
VDD
F10
A7
VDD
F9
A6
A9
VDD
F8
A5
P
VDD
F7
A4
G
VDD
F6
A3
A10
VDD
F5
A2
E
VDD
A8
Q7
F4
F3
A1
A0
Q6
Q0
Q5
Q1
Y
Y
Q4
Q2
Q3
GND
1
24
2
23
3
22
4
21
5
20
6
7
19
18
8
17
9
16
10
15
11
14
12
13
VDD
A8
F12
P
VDD
G
F1
A10
F13
E
F0
Q7
Q6
Q5
Q4
Q3
NOTES:
NOTES:
5. VDD = 6.0V ± 0.5V
1. VDD = 6.0V ± 0.5V
2. C1 = 0.01µF (Min)
6. VIH = 4.5V± 10%
3. All Resistors = 47kΩ ± 5%
7. VIL = 0.8V (Max)
4. Y = 2.7V ± 10%
8. C1 = 0.01µF (Min)
9. All Resistors = 47kΩ ± 5%
10. F0 = 100KHz ± 10%, 40 - 60% duty cycle
11. F1 = F0/2 . . . F13 = F12/2
12. Y = 2.7V ± 10%
3
F11
A9
DYNAMIC CONFIGURATION
STATIC CONFIGURATION
VDD
Y
HS-6617RH
Irradiation Circuit
HS-6617RH 24 LEAD FLATPACK
VDD
1
24
2
23
3
22
4
21
NC
5
20
NC
6
19
NC
7
18
8
17
LOAD
LOAD
9
16
LOAD
LOAD
10
15
LOAD
LOAD
11
14
LOAD
12
13
LOAD
TOGGLE (NOTE 15)
VDD
47KΩ
LOAD =
47KΩ
VSS
NOTES:
13. Power Supply: VDD = 5.5V
14. All Registors = 47kΩ
15. Pin 18 is toggled from VSS to VDD then back to VSS and held at VSS during irradiation.
4
HS-6617RH
Die Characteristics
DIE DIMENSIONS:
ASSEMBLY RELATED INFORMATION:
164mils x 250mils x 19mils ±1mils
Substrate Potential:
INTERFACE MATERIALS:
VDD
ADDITIONAL INFORMATION:
Glassivation:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
Worst Case Current Density:
1 x 105 A/cm2
Top Metallization:
Type: Silicon-Aluminum
Thickness: 13kÅ ± 2kÅ
Metallization Mask Layout
(21) P
(22) A9
(23) A8
(24)VDD
(1) A7
(2) A6
(3)A5
(4) A4
(5) A3
HS-6617RH
(20) G
A2 (6)
(19) A10
A1 (7)
(18) E
Q7 (17)
Q6 (16)
Q5 (15)
Q4 (14)
Q3 (13)
GND (12)
Q2 (11)
Q1 (10)
Q0 (9)
A0 (8)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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