DATASHEET

HS-6664RH-T
TM
Data Sheet
July 1999
Radiation Hardened 8K x 8 CMOS PROM
Features
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
• QML Class T, Per MIL-PRF-38535
The Intersil HS-6664RH-T is a radiation hardened 64K
CMOS PROM, organized in an 8K word by 8-bit format. The
chip is manufactured using a radiation hardened CMOS
process, and utilizes synchronous circuit design techniques
to achieve high speed performance with very low power
dissipation.
On-chip address latches are provided, allowing easy
interfacing with microprocessors that use a multiplexed
address/data bus structure. The output enable control (G)
simplifies system interfacing by allowing output data bus
control in addition to the chip enable control (E). All bits are
manufactured storing a logical “0” and can be selectively
programmed for a logical “1” at any bit location.
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- No Latch-Up, SEU LET >100MeV/mg/cm 2
• Transient Output Upset >5 x 108 RAD (Si)/s
• Fast Access Time - 35ns (Typical)
• Single 5V Power Supply, Synchronous Operation
• Single Pulse 10V Field Programmable NiCr Fuses
• On-Chip Address Latches, Three-State Outputs
• Low Standby Current <500µA (Pre-Rad)
• Low Operating Current <15mA/MHz
Pinouts
HS1-6664RH-T (SBDIP), CDIP2-T28
TOP VIEW
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-666s4RH-T
are contained in SMD 5962-95626. For more information,
visit our website at: www.intersil.com/
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/
NC 1
28 VDD
A12 2
27 P †
A7 3
26 NC
A6 4
25 A8
A5 5
24 A9
A4 6
23 A11
A3 7
22 G
A2 8
21 A10
A1 9
20 E
A0 10
19 DQ7
DQ0 11
18 DQ6
DQ1 12
17 DQ5
DQ2 13
16 DQ4
GND 14
15 DQ3
HS9-6664RH-T (FLATPACK), CDFP3-F28
TOP VIEW
Ordering Information
ORDERING
INFORMATION
FN4609.1
PART
NUMBER
TEMP.
RANGE
(oC)
5962R9562601TXC
HS1-6664RH-T
-55 to 125
HS1-6664RH/Proto
HS1-6664RH/Proto
-55 to 125
5962R9562601TYC
HS9-6664RH-T
-55 to 125
HS9-6664RH/Proto
HS9-6664RH/Proto
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
NC
1
28
VDD
A12
2
27
P†
A7
3
26
NC
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
G
A2
8
21
A10
A1
9
20
A0
10
19
E
DQ7
DQ0
11
18
DQ6
DQ1
12
17
DQ5
DQ2
13
16
DQ4
GND
14
15
DQ3
† P must be hardwired at all times to VDD , except during programming.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
HS-6664RH-T
Functional Diagram
MSB
A2
A3
A4
A5
A6
A7
A8
LSB
A
LATCHED
ADDRESS
REGISTER
8
256
GATED ROW
DECODER
A
256 X 256
MATRIX
1 OF 8
8
E
E
32
32
32
†P
32
32
32
32
GATED COLUMN DECODER
PROGRAMMING, AND DATA
OUTPUT CONTROL
8
E
E
32
A
A
5
Q0 - Q7
8
5
G
E
LATCHED ADDRESS
REGISTER
† P must be hardwired at all times to V DD ,
except during programming.
MSB
LSB
A0
A1
A10
A9
A11
A12
TRUTH TABLE
E
G
MODE
0
0
Enabled
0
1
Output Disabled
1
X
Disabled
Timing Waveform
TAVQV
3.0V
1.5V
1.5V
VALID
ADDRESS
VALID
ADDRESSES
0V
ADDRESSES
TELEL
TAVEL
TELAX
TELEH
3.0V
1.5V
1.5V
1.5V
1.5V
E
0V
TEHEL
TELQV
G
TEHQZ
TGLQV
3.0V
1.5V
1.5V
0V
TGLQX
TGHQZ
TELQX
DATA
OUTPUT
Q0 - Q7
VALID
DATA
FIGURE 1. READ CYCLE
2
TS
HS-6664RH-T
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
(6883µm x 7798µm x 483µm ±25.4µm)
Type: Silox (SiO2)
271 x 307 x 19mils ±1mil
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
METALLIZATION:
< 2.0e5 A/cm 2
MI: 6kÅ ± 1kÅ
Si/AI/Cu
2kÅ ± 500Å TiW
M2: 10kÅ ± 2kÅ Si/AI/Cu
TRANSISTOR COUNT:
110, 874, (27,719 Gates)
SUBSTRATE POTENTIAL:
PROCESS:
VDD
AVLSI
BACKSIDE FINISH:
Silicon
Metallization Mask Layout
VSS
VDD
(23) A11
(24) A9
(25) A8
(26) NC
(22) G
A10 (21)
E (20)
DQ7 (19)
DQ6 (18)
DQ5 (17)
(27) P
(28) VDD
DQ4 (16)
DQ3 (15)
GND (14)
(3) A7
(4) A6
(2) A12
DQ2 (13)
DQ1 (12)
(5) A5
DQ0 (11)
(6) A4
A0 (10)
A1 (9)
A2 (8)
VDD
VSS
(7) A3
HS-6664RH-T
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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