DATASHEET

ACS14MS
Data Sheet
Radiation Hardened Hex Inverting Schmitt
Trigger
The Radiation Hardened ACS14MS is a Hex Inverting
Schmitt Trigger. This device simply inverts the level present
on each input. The Schmitt Trigger input stage provides
400mV (Min) of hysteresis and permits input signals with
longer rise times. All inputs are buffered and the outputs are
designed for balanced propagation delay and transition
times.
The ACS14MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
November 1998
File Number
4544
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD (Si)
- SEU Immunity . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels . . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Hysteresis Voltage . . . . . . . . . . . . . . . . . . . . 400mV (Min)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 14ns (Max)
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS14MS are
contained in SMD 5962-98623. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MKT. NUMBER
5962F9862301VCC
ACS14DMSR-03
ACS14D/SAMPLE-03
ACS14D/SAMPLE-03
5962F9862301VXC
ACS14KMSR-03
ACS14K/SAMPLE-03
5962F9862301V9A
TEMP. RANGE (oC)
PACKAGE
DESIGNATOR
-55 to 125
14 Ld SBDIP
CDIP2-T14
25
14 Ld SBDIP
CDIP2-T14
-55 to 125
14 Ld Flatpack
CDFP4-F14
ACS14K/SAMPLE-03
25
14 Ld Flatpack
CDFP4-F14
ACS14HMSR-03
25
Die
N/A
Pinouts
ACS14MS
(SBDIP)
TOP VIEW
A1 1
ACS14MS
(FLATPACK)
TOP VIEW
14 VCC
A1
1
14
VCC
Y1
2
13
A6
A2
3
12
Y6
Y2
4
11
A5
Y1 2
13 A6
A2 3
12 Y6
Y2 4
11 A5
A3
5
10
Y5
A3 5
10 Y5
Y3
6
9
A4
Y3 6
9 A4
GND
7
8
Y4
GND 7
8 Y4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS14MS
Die Characteristics
DIE DIMENSIONS:
PASSIVATION
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ± 25µm (20.6 mils ± 1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ± 0.15µm
SPECIAL INSTRUCTIONS:
METALLIZATION: AL
Bond VCC First
Metal 1 Thickness: 0.7µm ± 0.1µm
Metal 2 Thickness: 1.0µm ± 0.1µm
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 105 A/cm2
Transistor Count: 130
SUBSTRATE POTENTIAL:
Unbiased Insulator
Metallization Mask Layout
ACS14MS
Y1
(2)
A1
(1)
VCC
(14)
A6
(13)
A2 (3)
(12) Y6
Y2 (4)
(11) A5
NC
NC
(10) Y5
A3 (5)
(6)
Y3
(7)
GND
(8)
Y4
(9)
A4
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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