DATASHEET

HS-82C54RH
TM
Data Sheet
Radiation Hardened CMOS Programmable
Interval Timer
The Intersil HS-82C54RH is a high performance, radiation
hardened CMOS version of the industry standard 8254 and
is manufactured using a hardened field, self-aligned silicon
gate CMOS process. It has three independently
programmable and functional 16-bit counters, each capable
of handling clock input frequencies of up to 5MHz. Six
programmable timer modes allow the HS-82C54RH to be
used as an event counter, elapsed time indicator, a
programmable one-shot, or for any other timing application.
The high performance, radiation hardness, and industry
standard configuration of the HS-82C54RH make it
compatible with the HS-80C86RH radiation hardened
microprocessor.
August 2000
File Number
3043.2
Features
• Electrically Screened to SMD # 5962-95713
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . . >108 rad(Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µA
- IDDOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
• Pin Compatible with NMOS 8254 and the Intersil 82C54
• High Speed, “No Wait State” Operation with 5MHz
HS-80C86RH
Static CMOS circuit design insures low operating power. The
Intersil hardened field CMOS process results in performance
equal to or greater than existing radiation resistant products
at a fraction of the power.
• Three Independent 16-Bit Counters
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• Status Read Back Command
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95713. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
• Single 5V Supply
• Six Programmable Counter Modes
• Binary or BCD Counting
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Military Temperature Range . . . . . . . . . . . -55oC to 125oC
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(oC)
5962R9571301QJC
HS1-82C54RH-8
-55 to 125
5962R9571301QXC
HS9-82C54RH-8
-55 to 125
5962R9571301VJC
HS1-82C54RH-Q
-55 to 125
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HS-82C54RH
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T24
TOP VIEW
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F24
TOP VIEW
24 VDD
D7
1
D6 2
23 WR
D6
2
D5 3
22 RD
D5
3
D4
4
D4 4
21 CS
5
D3 5
20 A1
D2 6
19 A0
D3
D2
D1
D0
8
CLK 0
OUT 0
9
D7 1
18 CLK 2
D1 7
17 OUT 2
D0 8
CLK 0 9
16 GATE 2
OUT 0 10
15 CLK 1
GATE 0
GND
6
7
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
WR
RD
CS
A1
A0
CLK 2
OUT 2
GATE 2
CLK 1
GATE 1
OUT1
14 GATE 1
GATE 0 11
13 OUT 1
GND 12
Pin Descriptions
SYMBOL
PIN
NUMBER
TYPE
D7-D0
1-8
I/O
CLK 0
9
I
CLOCK 0: Clock input of Counter 0.
OUT 0
10
O
OUT 0: Output of Counter 0.
GATE 0
11
I
GATE 0: Gate input of Counter 0.
GND
12
OUT 1
13
O
OUT 1: Output of Counter 1.
GATE 1
14
I
GATE 1: Gate input of Counter 1.
CLK 1
15
I
CLOCK 1: Clock input of Counter 1.
GATE 2
16
I
GATE 2: Gate input of Counter 2.
OUT 2
17
O
OUT 2: Output of Counter 2.
CLK 2
18
I
CLOCK 2: Clock input of Counter 2.
A0, A1
19-20
I
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
DESCRIPTION
DATA: Bi-directional three state data bus lines, connected to system data bus.
GROUND: Power supply connection.
A1
A0
Selects
0
0
Counter 0
0
1
Counter 1
1
0
Counter 2
1
1
Control Word Register
CS
21
I
CHIP SELECT: A low on this input enables the HS-82C54RH to respond to RD and WR signals. RD
and WR are ignored otherwise.
RD
22
I
READ: This input is low during CPU read operations.
WR
23
I
WRITE: This input is low during CPU write operations.
VDD
24
VDD: The +5V power supply pin. A 0.1µF capacitor between pins 12 and 24 is recommended for
decoupling.
2
HS-82C54RH
Functional Diagram
INTERNAL BUS
(8)
DATA
BUS
BUFFER
RD
READ/
WRITE
LOGIC
WR
A0
A1
CLK 0
GATE 0
OUT 0
COUNTER
0
INTERNAL BUS
D7-D0
CONTROL
WORD
REGISTER
STATUS
REGISTER
CLK 1
GATE 1
OUT 1
COUNTER
1
STATUS
LATCH
CRM
CE
CONTROL
LOGIC
CS
CONTROL
WORD
REGISTER
CRL
CLK 2
GATE 2
OUT 2
COUNTER
2
GATE N
CLK N
OUT N
OLM
OLL
AC Testing Input, Output Waveform
AC Test Circuits
V1
INPUT
R1
TEST
POINT
OUTPUT FROM
DEVICE UNDER TEST
NOTE: Includes stray and jig capacitance.
VOH
1.5V
1.5V
VOL
NOTE: AC Testing: All input signals must switch between VIL -0.4V
and VIH +0.4V. Input rise and fall times are driven at 1ns/V.
TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
R2
C1
1
1.7V
510
OPEN
150pF
3
VIH +0.4V
VIL -0.4V
C1 (NOTE)
R2
INPUT
HS-82C54RH
Waveforms
A0-1
A0-1
TWHAX
TAVWL
CS
TAVRL
TRHAX
CS
TSLWL
TSLRL
DATA
BUS
TRLRH
VALID
TDVWH
RD
TRHDZ
TWHDX
WR
TRLDV
DATA
BUS
VALID
TWLWH
FIGURE 1. WRITE
FIGURE 2. READ
TCHCL
CLK
TCL1CL2
TCLCL
TCLCH
TCH1CH2
TGHGL
TGVCH
TRHRL
TWHWL
OUTPUT 0
TCHGX
FIGURE 3. RECOVERY
4
TCHGX
GATE G
TGLGH
RD, WR
TGVCH
TGLOV
FIGURE 4. CLOCK AND GATE
TCLOV
HS-82C54RH
Burn-In Circuits
STATIC CONFIGURATION FOR BOTH
FLATPACK AND SBDIP PACKAGE
DYNAMIC CONFIGURATION FOR BOTH
FLATPACK AND SBDIP PACKAGE
VDD
F0
OPEN
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
13
12
VDD
F0
OPEN
F3
1
24
F4
2
23
F0
F5
3
22
F0
F6
4
21
F7
5
20
F8
6
19
F9
7
18
F10
8
17
F1
9
16
10
15
11
14
12
13
LOAD
F11
OPEN
NOTES:
1. VDD = 6.5V ±5%
2. TA = 125oC Minimum
3. Resistors = 10kΩ
4. IDD < 100µA
5. AC: F0 is compliment of F0
F0 is a 50% duty cycle pulse burst
F0 is left high after pulse burst
6.
7.
8.
9.
10.
11.
12.
13.
VDD = 6.5V ±5% (Burn-In)
VDD = 6.0V ±5% (Life Test)
TA = 125oC Minimum
IDD < 20mA
Resistors = 10kΩ, except for loads = 2.7kΩ
-0.3V ≤ VIL ≤ 0.8V
VDD -1.0V ≤ VIH ≤ VDD +0.5V
AC: F0 is compliment of F0
F0 = 100kHz ±10%, 50% Duty Cycle
F1 = F0/2, F2 = F1/2 . . . F10 = F9/2
Irradiation Circuits
HS-82C54RH
N/C
NOTES:
14. VDD = 5.5V ±10%, TA = 25oC
15. Group E Testing is performed in Sidebrazed DIP
16. Group E Sample Size is 2 die/wafer
5
LOAD
VDD
2.7kΩ
LOAD
LOAD
2.7kΩ
NOTES:
5.5V
F2
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
5.5V
N/C
N/C
HS-82C54RH
Functional Description
General
Read/Write Logic
The HS-82C54RH is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The Read/Write Logic accepts inputs from the system bus
and generates control signals for the other functional blocks
of the HS-82C54RH. A1 and A0 select one of the three
counters or the Control Word Register to be read
from/written into. A “low” on the RD input tells the
HS-82C54RH that the CPU is reading one of the counters. A
“low” on the WR input tells the HS-82C54RH that the CPU is
writing either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless the
HS-82C54RH has been selected by holding CS low.
The HS-82C54RH solves one of the most common problems
in any microcomputer system, the generation of accurate
time delays under software control. Instead of setting up
timing loops in software, the programmer configures the
HS-82C54RH to match his requirements and programs one
of the counters for the desired delay. After the desired delay,
the HS-82C54RH will interrupt the CPU. Software overhead
is minimal and variable length delays can easily be
accommodated.
Some of the other timer functions common to microcomputers which can be implemented with the
HS-82C54RH are:
Control Word Register
The Control Word Register (Figure 6) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the HS-82C54RH, the data is stored in the
Control Word Register and is interpreted as a Control Word
used to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
• Real time clock
• Event counter
Counter 0, Counter 1, Counter 2
• Digital one-shot
These three functional clocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a single counter is shown in Figure 7. The
counters are fully independent. Each Counter may operate
in a different Mode.
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
• Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to
interface the HS-82C54RH to the system bus (see Figure 5).
RD
WR
A0
A1
(8)
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
COUNTER
0
INTERNAL BUS
D7-D0
COUNTER
1
CLK 0
GATE 0
OUT 0
CLK 1
GATE 1
OUT 1
COUNTER
2
CLK 2
GATE 2
OUT 2
FIGURE 5. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTION
6
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
COUNTER
0
CLK 0
GATE 0
OUT 0
COUNTER
1
CLK 1
GATE 1
OUT 1
COUNTER
2
CLK 2
GATE 2
OUT 2
CS
CS
CONTROL
WORD
REGISTER
RD
WR
A0
A1
(8)
INTERNAL BUS
D7-D0
CONTROL
WORD
REGISTER
FIGURE 6. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS
HS-82C54RH
HS-82C54RH System Interface
INTERNAL BUS
CONTROL
WORD
REGISTER
The HS-82C54RH is treated by the system software as an
array of peripheral I/O ports; three are Counters and the
fourth is a Control Word Register for MODE programming.
STATUS
LATCH
STATUS
REGISTER
CRM
CRL
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder, such as a
Intersil HD-6440 for larger systems.
ADDRESS BUS (16)
CE
CONTROL
LOGIC
A1
A0
CONTROL BUS
I/OR I/OW
GATE N
CLK N
OUT N
OLM
DATA BUS (8)
OLL
8
A1
FIGURE 7. COUNTER INTERNAL BLOCK DIAGRAM
The Status Register, shown in the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back Command.)
The actual counter is labeled CE for “Counting Element”. It is
a 16-bit presettable synchronous down counter.
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”, subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally
referred to as one unit and called just OL. These latches
normally “follow” the CE, but if a suitable Counter Latch
Command is sent to the HS-82C54RH, the OL latches the
present count until read by the CPU and then returns to
“following” the CE. One latch at a time is enabled by the
counter’s Control Logic to drive the internal bus. This is how
the 16-bit Counter communicates over the 8-bit internal bus.
Note that the CE itself cannot be read; whenever you read
the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL
(for “Count Register”). Both are normally referred to as one
unit and called just CR. When a new count is written to the
Counter, the count is stored in the CR and later transferred
to the CE. The Control Logic allows one register at a time to
be loaded from the internal bus. Both bytes are transferred to
the CE simultaneously. CRM and CRL are cleared when the
Counter is programmed for one byte counts (either most
significant byte only or least significant byte only) the other
byte will be zero. Note that the CE cannot be written into;
whenever a count is written, it is written into the CR.
The Control Logic is also shown in the diagram. CLKn,
GATEn, and OUTn are all connected to the outside world
through the Control Logic.
7
A0
CS
COUNTER
0
D0-D7
HS-82C54RH
COUNTER
1
RD
WR
COUNTER
2
OUT GATE CLK
OUT GATE CLK
OUT GATE CLK
FIGURE 8. HS-82C54RH SYSTEM INTERFACE
Operational Description
General
After power-up, the state of the HS-82C54RH is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used. Unused Counters need not be programmed.
Programming The HS-82C54RH
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word
specifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
Write Operations
The programming procedure for the HS-82C54RH is very
flexible. Only two conventions need to be remembered:
1. For each Counter, the Control Word must be written
before the initial count is written.
2. The initial count must follow the count format specified in
the Control Word (least significant byte only, most
HS-82C54RH
significant byte only, or least significant byte and then
most significant byte).
Since the Control Word Register and the three Counter
shave separate addresses (selected by the A1, A0 inputs),
and each Control Word specifies the Counter it applies to
(SC0, SC1 bits), no special instruction sequence is required.
Any programming sequence that follows the conventions
above is acceptable.
Control Word Format
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC2
RW1
RW0
M2
M1
M0
BCD
SC - SELECT COUNTER:
M - MODE:
SC1
SC0
0
0
Select Counter 0
M2
M1
M0
0
0
0
Mode 0
0
1
1
0
Select Counter 1
0
0
1
Mode 1
Select Counter 2
X
1
0
Mode 2
1
1
Read-Back Command (See Read
Operations)
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
RW - READ/WRITE
RW1
RW0
0
0
Counter Latch Command (See Read
Operations)
0
1
Read/Write least significant byte only.
0
Binary Counter 16-bits
1
0
Read/Write most significant byte only.
1
Binary Coded Decimal (BCD) Counter (4 Decades)
1
1
Read/Write least significant byte first, then
most significant byte.
BCD - BINARY CODED DECIMAL:
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
FIGURE 9. CONTROL WORD FORMAT
A1
A0
A1
A0
Control Word - Counter 0
1
1
Control Word - Counter 2
1
1
LSB of count - Counter 0
0
0
Control Word - Counter 1
1
1
MSB of count - Counter 0
0
0
Control Word - Counter 0
1
1
Control Word - Counter 1
1
1
LSB of count - Counter 2
1
0
LSB of count - Counter 1
0
1
MSB of count - Counter 2
1
0
MSB of count - Counter 1
0
1
LSB of count - Counter 1
0
1
Control Word - Counter 2
1
1
MSB of count - Counter 1
0
1
LSB of count - Counter 2
1
0
LSB of count - Counter 0
0
0
MSB of count - Counter 2
1
0
MSB of count - Counter 0
0
0
A1
A0
A1
A0
Control Word - Counter 0
1
1
Control Word - Counter 1
1
1
Control Word - Counter 1
1
1
Control Word - Counter 0
1
1
Control Word - Counter 2
1
1
LSB of count - Counter 1
0
1
LSB of count - Counter 2
1
0
Control Word - Counter 2
1
1
LSB of count - Counter 1
0
1
LSB of count - Counter 0
0
0
LSB of count - Counter 0
0
0
MSB of count - Counter 1
0
1
MSB of count - Counter 0
0
0
LSB of count - Counter 2
1
0
MSB of count - Counter 1
0
1
MSB of count - Counter 0
0
0
MSB of count - Counter 2
1
0
MSB of count - Counter 2
1
0
NOTE: In all four examples, all counters are programmed to Read/Write two-byte counts. These are only four of many possible programming
sequences.
FIGURE 10. A FEW POSSIBLE PROGRAMMING SEQUENCES
8
HS-82C54RH
A new initial count may be written to a Counter at any time
without affecting the Counter’s programmed Mode in
anyway. Counting will be affected as described in the Mode
definitions. The new count must follow the programmed
count format.
Counters “on the fly” without affecting counting in progress.
Multiple Counter Latch Commands may be used to latch
more than one Counter. Each latched Counter’s OL holds its
count until read. Counter Latch Commands do not affect the
programmed Mode of the Counter in any way.
If a Counter is programmed to read/write two-byte counts,
the following precaution applies: A program must not
transfer control between writing the first and second byte to
another routine which also writes into that same Counter.
Otherwise, the Counter will be loaded with an incorrect
count.
If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at the
time the first Counter Latch Command was issued.
Read Operations
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
HS-82C54RH.
There are three possible methods for reading the Counters.
The first is through the Read-Back Command, which is
explained later. The second is a simple read operation of the
Counter, which is selected with the A1, A0 inputs. The only
requirement is that the CLK input of the selected Counter
must be inhibited by using either the GATE input or external
logic. Otherwise, the count may be in process of changing
when it is read, giving an undefined result.
With either method, the count must be read according to the
programmed format; specifically, if the Counter is
programmed for two byte counts, two bytes must be read.
The two bytes do not have to be read one right after the
other; read or write or programming operations of other
Counters may be inserted between them.
Another feature of the HS-82C54RH is that reads and writes
of the same Counter may be interleaved; for example, if the
Counter is programmed for two byte counts, the following
sequence is valid.
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.
Counter Latch Command
The other method for reading the Counters involves a
special software command called the “Counter Latch
Command”. Like a Control Word, this command is written to
the Control Word Register, which is selected when A1, A0 =
11. Also, like a Control Word, the SC0, SC1 bits select one
of the three Counters, but two other bits, D5 and D4,
distinguish this command from a Control Word.
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC0
0
0
X
X
X
X
SC1, SC0 - specify counter to be latched
SC1
SC1
Counter
0
0
0
0
0
1
1
1
2
1
1
Read-Back Command
D5, D4 = 00 designates Counter Latch Command
X = Don’t Care
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
FIGURE 11. COUNTER LATCH COMMAND FORMAT
The selected Counter’s Output Latch (OL) latches the count
when the Counter Latch Command is received. This count is
held in the latch until it is read by the CPU (or until the
Counter is reprogrammed). The count is then unlatched
automatically and the OL returns to “following” the Counting
Element (CE). This allows reading the contents of the
9
If a Counter is programmed to read or write two-byte counts,
the following precaution applies: A program MUST NOT
transfer control between reading the first and second byte to
another routine which also reads from that same Counter.
Otherwise, an incorrect count will be read.
Read-Back Command
The Read-Back Command allows the user to check the
count value, programmed Mode, and current state of the
OUT pin and Null Count flag of the selected Counter(s).
The command is written into the Control Word Register and
has the format shown in Figure 12. The command applies to
the Counters selected by setting their corresponding bits D3,
D2, D1 = 1.
A0, A1 = 11; CS = 0; RD = 1; WR = 0
D7
D6
D5
D4
1
1
COUNT
STATUS
D5:
D4:
D3:
D2:
D1:
D0:
D3
D2
D1
CNT 2 CNT 1 CNT 0
D0
0
0 = Latch count of selected Counters(s)
0 = Latch status of selected Counters(s)
1 = Select Counter 2
1 = Select Counter 1
1 = Select Counter 0
Reserved for future expansion; Must be 0
FIGURE 12. READ-BACK COMMAND FORMAT
The Read-Back Command may be used to latch multiple
Counter Output Latches (OL) by setting the COUNT bit D5 =
0 and selecting the desired Counter(s). This single
command is functionally equivalent to several Counter Latch
HS-82C54RH
Commands, one for each Counter latched. Each Counter’s
latched count is held until it is read (or the Counter is
reprogrammed). That Counter is automatically unlatched
when read, but other Counters remain latched until they are
read. If multiple count Read-Back Commands are issued to
the same Counter without reading the count, all but the first
are ignored; i.e., the count which will be read is the count at
the time the first Read-Back Command was issued.
will not reflect the new count just written. The operation of
Null Count is shown in Figure 14.
The Read-Back Command may also be used to latch status
information of selected Counter(s) by setting STATUS bit
D4 = 0. Status must be latched to be read; status of a
Counter is accessed by a read from that Counter.
NOTES:
The Counter status format is shown in Figure 13. Bits D5
through D0 contain the Counter’s programmed Mode exactly
as written in the last Mode Control Word. OUTPUT bit D7
contains the current state of the OUT pin. This allows the
user to monitor the Counter’s output via software, possibly
eliminating some hardware from a system.
D7
D6
D5
D4
D3
D2
D1
D0
OUT
PUT
NULL
COUNT
RW1
RW0
M2
M1
M0
BCD
D7 1 = Out Pin is 1
0 = Out pin is 0
D6 1 = Null count
0 = Count available for reading
D5-D0 = Counter programmed mode (See Figure 5)
FIGURE 13. STATUS BYTE
NULL COUNT bit D6 indicates when the last count written to
the Counter Register (CR) has been loaded into the
Counting Element (CE). The exact time this happens
depends on the Mode of the Counter and is described in the
Mode Definitions, but until the count is loaded into the
Counting Element (CE), it can’t be read from the Counter. If
the count is latched or read before this time, the count value
THIS ACTION:
CAUSES:
A. Write to the Control Word Register: (Note 17)
Null Count = 1
B. Write to the Count Register (CR): (Note 18)
Null Count = 1
C. New count is loaded into CE (CR → CE):
Null Count = 0
17. Only the Counter specified by the Control Word will have its Null
Count set to 1. Null Count bits of other Counters are unaffected.
18. If the Counter is programmed for two-byte counts (least
significant byte then most significant byte) Null Count goes to 1
when the second byte is written.
FIGURE 14. NULL COUNT OPERATION
If multiple status latch operations of the Counter(s) are
performed without reading the status, all but the first are
ignored; i.e., the status that will be read is the status of the
Counter at the time the first status Read-Back Command
was issued.
Both count and status of the selected Counter(s) may be
latched simultaneously by setting both COUNT and STATUS
bits D5, D4 = 0. This is functionally the same as issuing two
separate Read-Back Commands at once, and the above
discussions apply here also. Specifically, if multiple count
and/or status Read-Back Commands are issued to the same
Counter(s) without any intervening reads, all but the first are
ignored. This is illustrated in Figure 15.
If both count and status of a Counter are latched, the first
read operation of that Counter will return latched status,
regardless of which was latched first. The next one or two
reads (depending on whether the Counter is programmed for
one or two byte counts) return latched count. Subsequent
reads return unlatched count.
COMMAND
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
1
0
0
0
0
1
0
Read back count and status of
Counter 0
Count and status latched for Counter 0
1
1
1
0
0
1
0
0
Read-back status of Counter 1
Status latched for Counter 1
1
1
1
0
1
1
0
0
Read-back status of Counters 2, 1
Status latched for Counter 2, but not
Counter 1
1
1
0
1
1
0
0
0
Read-back count of Counter 2
Count latched for Counter 2
1
1
0
0
0
1
0
0
Read-back count and status of Counter 1
Count latched for Counter 1, but not status
1
1
1
0
0
1
0
0
Read-back status of Counter 1
Command ignored, status already latched
for Counter 1
FIGURE 15. READ-BACK COMMAND EXAMPLE
10
RESULT
HS-82C54RH
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
CS
RD
WR
A1
A0
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write into Counter 1
0
1
0
1
0
Write into Counter 2
0
1
0
1
1
Write Control Word
0
0
1
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter 1
0
0
1
1
0
Read from Counter 2
0
0
1
1
1
No-Operation (Three-State)
CLK
1
X
X
X
X
No-Operation (Three-State)
GATE
0
1
1
X
X
No-Operation (Three-State)
If an initial count is written while GATE = 0, it will still
beloaded on the next CLK pulse. When GATE goes high,
OUT will go high N CLK pulses later; no CLK pulse is
needed to load the Counter as this has already been done.
CW = 10
LSB = 4
WR
OUT
FIGURE 16. READ/WRITE OPERATIONS SUMMARY
N
N
N
N
Mode Definitions
The following are defined for use in describing the operation
of the HS-82C54RH.
CW = 12
0
4
0
3
0
2
0
1
0
0
FF
FF
FF
FE
0
3
0
2
0
2
0
2
0
1
0
0
FF
FF
0
2
0
1
0
0
FF
FF
LSB = 3
WR
CLK
CLK PULSE:
GATE
A rising edge, then a falling edge, in that order, of a
Counter’s CLK input.
OUT
N
TRIGGER:
A rising edge of a Counter’s Gate input.
N
CW = 10
N
N
LSB = 2
LSB = 3
WR
COUNTER LOADING:
CLK
The transfer of a count from the CR to the CE (See
“Functional Description”)
Mode 0: Interrupt on Terminal Count
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is
written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte disables counting. OUT is set low
immediately (no clock pulse required).
2. Writing the second byte allows the new count to be loaded
on next CLK pulse.
GATE
OUT
N
NOTES:
N
N
N
0
3
0
2
0
1
19. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
20. The Counter is always selected (CS always low).
21. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
22. LSB stands for “Least significant byte” of count.
23. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
24. N stands for an undefined count.
25. Vertical lines show transitions between count values.
FIGURE 17. MODE 0
Mode 1: Hardware Retriggerable One-Shot
OUT will be initially high. OUT will go low on the CLK pulse
following a trigger to begin the one-shot pulse, and will
remain low until the Counter reaches zero. OUT will then go
high and remain high until the CLK pulse after the next
trigger.
After writing the Control Word and initial count, the Counter
is armed. A trigger results in loading the Counter and setting
11
HS-82C54RH
OUT low on the next CLK pulse, thus starting the one-shot
pulse N CLK cycles in duration. The one-shot is
retriggerable, hence OUT will remain low for N CLK pulses
after any trigger. The one-shot pulse can be repeated
without rewriting the same count into the Counter. GATE has
no effect on OUT.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the
Counter is retriggered. In that case, the Counter is loaded
with the new count and the one-shot pulse continues until
the new count expires.
CW = 12
CLK
GATE
OUT
N
CW = 12
N
N
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low during an output pulse, OUT is set high
immediately. A trigger reloads the Counter with the initial
count on the next CLK pulse; OUT goes low N CLK pulses
after the trigger. Thus the GATE input can be used to
synchronize the Counter.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. OUT goes low N CLK
pulses after the initial count is written. This allows the
Counter to be synchronized by software also.
LSB = 3
WR
N
OUT goes low for one CLK pulse. OUT then goes high
again, the Counter reloads the initial count and the process
is repeated. Mode 2 is periodic; the same sequence is
repeated indefinitely. For an initial count of N, the sequence
repeats every N CLK cycles.
N
0
3
0
2
0
1
0
0
FF
FF
0
3
0
2
LSB = 3
WR
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current period,
the Counter will be loaded with the new count on the next
CLK pulse and counting will continue from the new count.
Otherwise, the new count will be loaded at the end of the
current counting cycle.
CLK
CW = 14 LSB = 3
GATE
WR
OUT
CLK
N
N
CW = 12
N
N
N
LSB = 2
0
3
0
2
0
1
0
3
0
2
0
1
0
0
GATE
OUT
LSB = 4
WR
N
N
N
N
0
3
0
2
0
1
0
3
0
2
0
1
0
3
0
3
0
2
0
2
0
3
0
2
0
1
0
3
0
1
0
5
0
4
0
3
CLK
CW = 12 LSB = 3
WR
GATE
CLK
OUT
N
N
N
N
N
0
2
0
1
0
0
FF
FF
FF
FE
0
4
0
3
GATE
OUT
NOTES:
26. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
27. The Counter is always selected (CS always low).
28. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
29. LSB stands for “Least significant byte” of count.
30. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
31. N stands for an undefined count.
32. Vertical lines show transitions between count values.
FIGURE 18. MODE 1
Mode 2: Rate Generator
This Mode functions like a divide-by-N counter. It is typically
used to generate a Real Time Clock interrupt. OUT will
initially be high. When the initial count has decremented to 1,
12
N
N
N
N
CW = 14 LSB = 4
LSB = 5
WR
CLK
GATE
OUT
N
N
N
N
0
4
0
3
0
2
NOTES:
33. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
34. The Counter is always selected (CS always low).
35. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
36. LSB stands for “Least significant byte” of count.
HS-82C54RH
37. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
38. N stands for an undefined count.
39. Vertical lines show transitions between count values.
FIGURE 19. MODE 2
Mode 3: Square Wave Mode
Mode 3 is typically used for Baud rate generation. Mode 3 is
similar to Mode 2 except for the duty cycle of OUT. OUT will
initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count. Mode 3 is periodic;
the sequence above is repeated indefinitely. An initial count
of N results in a square wave with a period of N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low while OUT is low, OUT is set high
immediately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus
the GATE input can be used to synchronize the
Counter.After writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This allows
the Counter to be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current halfcycle of the square wave, the Counter will be loaded with the
new count on the next CLK pulse and counting will continue
from the new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
Mode 3 is implemented as follows:
EVEN COUNTS: OUT is initially high. The initial count is
loaded on one CLK pulse and then is decremented by two
on succeeding CLK pulses. When the count expires, OUT
changes value and the Counter is reloaded with the initial
count. The above process is repeated indefinitely.
ODD COUNTS: OUT is initially high. The initial count is
loaded on one CLK pulse, decremented by one on the next
CLK pulse, and then decremented by two on succeeding
CLK pulses. When the count expires, OUT goes low and the
Counter is reloaded with the initial count. The count is
decremented by three on the next CLK pulse, and then by
two on succeeding CLK pulses.When the count expires,
OUT goes high again and the Counter is reloaded with the
initial count. The above process is repeated indefinitely. So
for odd counts, OUT will be high for (N + 1)/2 counts and low
for (N-1)/2 counts.
13
Mode 4: Software Triggered Mode
OUT will be initially high. When the initial count expires, OUT
will go low for one CLK pulse then go high again.The
counting sequence is “Triggered” by writing the initial count.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. This CLK pulse does not
decrement the count, so for an initial count of N, OUT does
not strobe low until N + 1 CLK pulses after the initial count is
written.
If a new count is written during counting, it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte has no effect on counting.
2. Writing the second byte allows the new count to be loaded
on the next CLK pulse.
This allows the sequence to be “retriggered” by software.
OUT strobes low N + 1 CLK pulses after the new count of N
is written.
Mode 5: Hardware Triggered Strobe
(Retriggerable)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will
go low for one CLK pulse and then go high again.
After writing the Control Word and initial count, the Counter
will not be loaded until the CLK pulse after a trigger. This
CLK pulse does not decrement the count, so for an initial
count of N, OUT does not strobe low until N + 1 CLK pulses
after trigger.
A trigger results in the Counter being loaded with the initial
count on the next CLK pulse. This allows the counting
sequence to be regretted. OUT strobes low N + 1 CLK
pulses after any new trigger. GATE has no effect on the state
of OUT.
If a new count is written during counting, the current
counting sequence will not be affected. If a trigger occurs
after the new count is written but before the current count
expires, the Counter will be loaded with the new count on the
next CLK pulse and counting will continue from there.
HS-82C54RH
CW = 16 LSB = 4
CW = 18 LSB = 3
WR
WR
CLK
CLK
GATE
GATE
OUT
OUT
N
N
N
N
0
4
0
2
0
4
0
2
0
4
0
2
0
4
0
2
0
4
0
2
N
CW = 16 LSB = 5
N
N
N
0
3
0
2
0
1
0
0
FE
FF
FF FF
FE FD
0
3
0
3
0
3
0
2
0
1
0
0
FF
FF
0
2
0
1
0
0
FF
FF
CW = 18 LSB = 3
WR
WR
CLK
CLK
GATE
GATE
OUT
OUT
N
N
N
N
0
5
0
4
0
2
0
5
0
2
0
5
0
4
0
2
0
5
0
2
N
CW = 16 LSB = 4
WR
CLK
CLK
GATE
GATE
OUT
OUT
N
N
N
N
N
CW = 18 LSB = 3
WR
N
N
0
4
0
2
0
4
0
2
0
2
0
2
0
4
0
2
0
4
0
2
N
N
N
N
LSB = 2
0
3
0
2
0
1
NOTES:
NOTES:
40. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
41. The Counter is always selected (CS always low).
42. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
43. LSB stands for “Least significant byte” of count.
44. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
45. N stands for an undefined count.
46. Vertical lines show transitions between count values.
FIGURE 20. MODE 3
47. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
48. The Counter is always selected (CS always low).
49. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
50. LSB stands for “Least significant byte” of count.
51. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
52. N stands for an undefined count.
53. Vertical lines show transitions between count values.
FIGURE 21. MODE 4
14
HS-82C54RH
Operation Common to All Modes
CW = 1A LSB = 3
WR
Programming
CLK
When a Control Word is written to a Counter, all Control
Logic is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
GATE
OUT
Gate
N
N
N
N
N
0
3
0
2
0
1
0
0
FF 0
FF 3
N
N
0
3
0
2
0
3
0
2
CW = 1A LSB = 3
WR
CLK
GATE
OUT
N
N
N
N
CW = 1A LSB = 3
0
1
0
0
FF
FF
LSB = 5
The GATE input is always sampled on the rising edge of CLK.
In Modes 0, 2, 3 and 4 the GATE input is level sensitive, and
logic level is sampled on the rising edge of CLK. In modes 1, 2,
3 and 5 the GATE input is rising-edge sensitive. In these
Modes, a rising edge of Gate (trigger) sets an edge-sensitive
flip-flop in the Counter. This flip-flop is then sampled on the next
rising edge of CLK. The flip-flop is reset immediately after it is
sampled. In this way, a trigger will be detected no matter when it
occurs - a high logic level does not have to be maintained until
the next rising edge of CLK. Note that in Modes 2 and 3, the
GATE input is both edge-and level-sensitive.
WR
Counter
CLK
New counts are loaded and Counters are decremented on
the falling edge of CLK.
GATE
OUT
N
N
N
N
N
0
3
0
2
0
1
0
0
FF FF
FF FE
0
5
0
4
NOTES:
54. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
55. The Counter is always selected (CS always low).
56. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
57. LSB stands for “Least significant byte” of count.
58. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
59. N stands for an undefined count.
60. Vertical lines show transitions between count values.
FIGURE 22. MODE 5
The largest possible initial count is 0; this is equivalent to 216
for binary counting and 104 for BCD counting.
The Counter does not stop when it reaches zero. In Modes
0, 1, 4 and 5 the Counter “wraps around” to the highest
count, either FFFF hex for binary counting or 9999 for BCD
counting, and continues counting. Modes 2 and 3 are
periodic; the Counter reloads itself with the initial count and
continues counting from there.
MINIMUM AND MAXIMUM INITIAL COUNTS
MODE
MIN COUNT
MAX COUNT
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
5
1
0
NOTE: 0 is equivalent to 216 for binary counting and 104 for BCD
counting.
GATE PIN OPERATIONS SUMMARY
SIGNAL STATUS MODES
0
LOW OR GOING LOW
RISING
Disables counting
1
-
1) Initiates counting
2) Resets output after next clock
HIGH
Enables counting
-
2
1) Disables counting
2) Sets output immediately high
Initiates counting
Enables counting
3
1) Disables counting
2) Sets output immediately high
Initiates counting
Enables counting
4
1) Disables counting
5
-
15
Initiates counting
Enables counting
-
HS-82C54RH
Die Characteristics
DIE DIMENSIONS:
Substrate:
4700µm x 5510µm x 485µm ±25.4µm
Radiation Hardened Silicon Gate,
Dielectric Isolation
INTERFACE MATERIALS:
Backside Finish:
Glassivation:
Silicon
Type: SiO2
Thickness: 8kÅ ±1kÅ
ASSEMBLY RELATED INFORMATION:
Top Metallization:
Substrate Potential:
Type: Al/Si
Thickness: 11kÅ ±2kÅ
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
7.9 x 104 A/cm2
Metallization Mask Layout
(22) RD
(23) WR
(24) VDD
(1) D7
(2) D6
(3) D5
HS-82C54RH
(21) CS
D4 (4)
(20) A1
D3 (5)
(19) A0
D2 (6)
D1 (7)
(18) CLK 2
(17) OUT 2
D0 (8)
(16) GATE 2
16
CLK 1 (15)
GATE 1 (14)
OUT 1 (13)
VSS (12)
GATE 0 (11)
OUT 0 (10)
CLK 0 (9)
HS-82C54RH
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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17
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