DATASHEET

DATASHEET
Radiation Hardened Low Dropout Adjustable Negative
Voltage Regulator
ISL72991RH
Features
The radiation hardened ISL72991RH is a low dropout
adjustable negative regulator with an output voltage range of
-2.25V to -26V. The device features a 1A output current
capability, an adjustable current limit pin (ILIM) and a
shutdown pin (SD) for easy on/off control.
• Electrically screened to DLA SMD # 5962-02503
The device incorporates unique circuitry that enables precision
performance over the -55°C to +125°C temperature range and
post-irradiation. Specifications over the full temperature range
include an internal reference voltage of -1.25V +40mV/-50mV
(max), line regulation of ±25mV (max) and load regulation of
±15mV (max). The reference voltage is the ADJ to GND voltage.
• Nominal output voltage range . . . . . . . . . . . . . -2.25V to -26V
Constructed with the Intersil dielectrically isolated Rad Hard
Silicon Gate (RSG) BiCMOS process, these devices are immune
to single event latch-up and have been specifically designed to
provide highly reliable performance in harsh radiation
environments.
• Minimum load current. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
Applications
• Post switching power supplies
• QML qualified per MIL-PRF-38535 requirements
• Latch-up immune DI process
• Wide input voltage range . . . . . . . . . . . . . . . . . . . . -3V to -30V
• Line regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25mV (max)
• Load regulation . . . . . . . . . . . . . . . . ±12mV (typ); ±15mV (max)
• Dropout voltage (100mA) . . . . . . . . . . . 0.2V (typ); 0.3V (max)
• Dropout voltage (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . 1V (max)
• TTL input-level shutdown (SD); Low = on
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Radiation environment
- SEL/SEB LETTH (VS = -30V) . . . . . . . . . 86.4 MeV•cm2/mg
- Total dose, high dose rate . . . . . . . . . . . . . . . . . 300krad(Si)
Related Literature
• DC/DC converters
• Motor controllers
• TID, “Low Dose Rate Testing of the Intersil ISL72991RH
Negative Low Dropout Regulator”
• SEE, “Single Effects Testing of the ISL72991RH Adjustable
Voltage Regulator”
• UG012, ISL72991RHEVAL2Z Evaluation Board User Guide
-1.245
790
VOUT
VOUT
ISL72991RH
R1
R2
ADJ
COUT
RCL
CIN
800
780
ISCL (RCL = 3.7kΩ)
770
-1.247
CC
R1
R2
-1.246
-1.248
-1.249
-75
FIGURE 1. TYPICAL APPLICATION
May 7, 2015
FN9054.4
1
ISCL (mA)
VIN
ILIM
SD
GND
VREF (V)
VIN
-1.244
760
VREF
(VIN = -7V, IOUT = 1A)
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
750
125
FIGURE 2. VREF AND ISCL vs TEMPERATURE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2001, 2004, 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL72991RH
Ordering Information
ORDERING SMD NUMBER
(Note 2)
PART NUMBER
(Note 1)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962F0250301VXC
ISL72991RHVF
-55 to +125
28 Ld Flatpack
K28.A
5962F0250301QXC
ISL72991RHQF
-55 to +125
28 Ld Flatpack
K28.A
5962F0250301V9A
ISL72991RHVX
-55 to +125
DIE
ISL72991RHF/PROTO
ISL72991RHF/PROTO
-55 to +125
28 Ld Flatpack
ISL72991RHX/SAMPLE
ISL72991RHX/SAMPLE
-55 to +125
DIE
ISL72991RHEVAL2Z
Evaluation Board
K28.A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
Pin Configuration
ISL72991RH
(28 LD FLATPACK)
TOP VIEW
VIN
1
28
VIN
VIN
2
27
VIN
NC
3
26
NC
NC
4
25
NC
NC
5
24
NC
NC
6
23
NC
NC
7
22
NC
NC
8
21
NC
NC
9
20
NC
NC
10
19
NC
GND
11
18
ADJ
ILIM
12
17
SD
VOUT
13
16
VOUT
VOUT
14
15
VOUT
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT CIRCUIT
1, 2, 27, 28
VIN
Circuit 2
Regulator Bias and Input Connection.
All 4 pins must be tied together.
DESCRIPTION
12
ILIM
Circuit 2
Current Limiting Set Input
13, 14, 15, 16
VOUT
Circuit 2
Regulator Output Connection.
All 4 pins must be tied together.
17
SD
Circuit 1
Shut Down Input, active high.
18
ADJ
Circuit 2
Output Voltage Adjust Input
11
GND
3, 4, 5, 6, 7, 8, 9, 10, 19, 20,
21, 22, 23, 24, 25, 26
NC
Ground Connection
No Internal connections. Can be connected to ground or
thermal plane.
GND
CAPACITIVELY
COUPLED
ESD CLAMP
GND
CIRCUIT 1
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2
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 2
May 7, 2015
FN9054.4
ISL72991RH
Functional Block Diagram
VIN
VOUT
-1.25V
+
VIN
I
-
ADJ
2.4k
ILIM
+
-1
SD
AI
IIN
I
GND
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
Typical Application
VIN
UNREGULATED VIN
(-3V to -30V)
VIN
ILIM
SD
GND
ISL72991RH
R1
ADJ
R1
R2
CC
COUT
RCL
CIN
R2
ON/OFF
REGULATED
VOUT
VOUT
(-2.25V to -26V)
VOUT
- VDC TO -VDC VOLTAGE REGULATION CIRCUIT
FIGURE 4. TYPICAL APPLICATION
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ISL72991RH
Absolute Maximum Ratings
Thermal Information
Minimum Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -35V
Minimum Supply Voltage (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30V
Minimum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA
Output Short-circuit Duration. Thermal Protection. . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (HBM) (Tested per MIL-PRF-883 3015.7) . . . . . 3kV
Machine Model (MM) (Tested per EIA/JESD22-A115-A) . . . . . . . . . 300V
Charged Device Model (CDM) (Tested per JESD22-C101D) . . . . . . . 1kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
28 Ld Flatpack (Notes 3, 4). . . . . . . . . . . . .
60
5
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3V to -30V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the package underside.
5. The minimum supply limit specified is for operation in a heavy ion environment at an LET = 86.4MeV*cm2/mg.
Electrical Specifications
VO ≤ VIN -1.5V, IO = 100mA, CO = 47µF, SD = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
across the operating temperature range, -55°C to +125°C.
PARAMETER
VREF
DESCRIPTION
Reference Voltage (ADJ to GND)
TEST CONDITIONS
IO = 3mA to 1A
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-1.279
-1.25
-1.231
V
-1.210
V
-2.25
V
-1.300
VOmin
Minimum Output Voltage
VIN = -3V, IO = 3mA to 100mA
VOmax
Maximum Output Voltage
VIN = -30V, IO = 3mA to 100mA
-26
Output Voltage Load Regulation
VIN = -7V, VO = -5V IO = 3mA to 1A
-12
12
mV
-15
15
mV
-25
25
mV
0.2
V
0.3
V
1
V
5
µA
VLDR
VLNR
Output Voltage Line Regulation
VO ≤ VIN -1V to VIN = -30V, IO = 100mA
VDOL
0.1A Drop Out Voltage
dVO ≤ 50mV, IO = 0.1A
V
VDOH
1A Drop Out Voltage (Pulse Tested)
dVO ≤ 50mV, IO = 1A
IADJ
Adjust Current
VO ≤ VIN -1V to VIN = -30V, IO = 500mA
IQDO
Drop Out Quiescent Current
VO - VIN = 0.2V, IO = 500mA
25
mA
VO - VIN = 0.3V, IO = 500mA
25
mA
VO = ON
0.8
V
VSD
SD Input Voltage
VO = OFF
ISD
SD Input Current
1.7
2.4
V
VSD = 0.8V
50
µA
VSD = 2.4V
100
µA
150
µA
0.9
A
ISCL
Output Short-circuit Current Limit
VIN = - 7V, VO = 0V, RCL = 3.7kΩ
IGND
GND Quiescent Current
-3V≤ VIN ≤ -30V, IO < 1A
PSRR
Power Supply Rejection Ratio
Frequency = 1MHz
0.6
0.75
6
mA
-49
dB
OTPROT
Thermal Protection
150
°C
OTHYS
Thermal Hysteresis
20
°C
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ISL72991RH
Post Radiation Electrical Specifications
VO ≤ VIN -1.5V, IO = 100mA, CO = 47µF, SD = 0V, TA = +25°C, across a total ionizing
dose of 300krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
VREF
Reference Voltage
IO = 3mA to 1A
VOmin
Minimum Output Voltage
VIN = -3V, IO = 3mA to 100mA
VOmax
Maximum Output Voltage
VIN = -30V, IO = 3mA to 100mA
-26
VLDR
Output Voltage Load Regulation
VIN = -7V, VO = -5V IO = 3mA to 1A
-12
VLNR
Output Voltage Line Regulation
VO ≤ VIN -1V to VIN = -30V, IO = 100mA
-25
VDOL
0.1A Drop Out Voltage
dVO ≤ 50mV, IO = 0.1A
VDOH
1A Drop Out Voltage (Pulse Tested)
dVO ≤ 50mV, IO = 1A
-1.279
TYP
MAX
(Note 6)
UNITS
-1.231
V
-2.25
V
V
12
mV
25
mV
0.2
V
1
V
IADJ
Adjust Current
VO ≤ VIN -1V to VIN = -30V, IO = 500mA
5
µA
IQDO
Dropout Quiescent Current
VO - VIN = 0.3V, IO = 500mA
25
mA
VSD
SD Input Voltage
VO = ON
0.8
V
ISD
SD Input Current
VSD = 0.8V
50
µA
VSD = 2.4V
100
µA
0.9
A
VO = OFF
ICL
Output Short-circuit Current Limit
VIN = - 7V, VO = 0V, RCL = 3.7kΩ
2.4
0.6
V
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL72991RH
Total Dose Radiation Characteristics This data is typical mean test data post total dose radiation exposure at a high dose rate
(HDR) of 50 to 300rad(Si)/s to 300krads. This data is intended to show typical parameter shifts due to total dose rate radiation. These are not limits nor
are they guaranteed.
0.1A DROP-OUT VOLTAGE CHANGE, (mV)
REFERENCE VOLTAGE (mV)
10
5
0
-5
-10
-30
0
50
100
150
200
250
300
60
40
20
0
-20
-40
-60
0
50
100
FIGURE 5. REFERENCE VOLTAGE CHANGE vs TOTAL DOSE
RADIATION
250
300
2
LINE REGULATION -4V TO -30V (mV)
1A DROPOUT VOLTAGE (mV)
200
FIGURE 6. 0.1A DROP-OUT VOLTAGE CHANGE vs TOTAL DOSE
RADIATION
3
2
1
0
-1
-2
-3
150
krad(Si)
krad(Si)
0
50
100
150
krad(Si)
200
250
1
0
-1
-2
300
0
50
100
150
200
250
300
krad(Si)
FIGURE 7. 1A DROP-OUT VOLTAGE CHANGE vs TOTAL DOSE
RADIATION
FIGURE 8. OUTPUT VOLTAGE LINE REGULATION CHANGE vs
TOTAL DOSE RADIATION
LOAD REGULATION 3mA TO 1A (mV)
2
1
0
-1
-2
0
50
100
150
200
250
300
krad(Si)
FIGURE 9. OUTPUT VOLTAGE LOAD REGULATION CHANGE vs TOTAL DOSE RADIATION
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ISL72991RH
Typical Performance Curves
1.6
1.4
1.4
+25°C
CURRENT LIMIT (A)
CURRENT LIMIT (A)
1.2
1.0
+125°C
0.8
-55°C
0.6
0.4
0.2
0.0
2
+25°C
1.2
1.0
+125°C
0.8
-55°C
0.6
0.4
0.2
3
4
5
6
7
RCL (kΩ)
8
9
0.0
2
10
3
1.4
+25°C
2.0
1.0
CURRENT LIMIT (A)
1.2
8
9
10
+125°C
0.8
-55°C
0.6
0.4
+25°C
1.5
-55°C
1.0
0.5
+125°C
0.2
2
3
4
5
6
RCL (kΩ)
7
8
9
0.0
10
2
3
-1.244
VREF
(VIN = -3.5V, IOUT = 0A)
-1.250
-50
0
25
50
75
TEMPERATURE (°C)
7
10
+125°C
600
+25°C
-55°C
100
FIGURE 14. VREF vs TEMPERATURE
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9
200
VREF
(VIN = -30V, IOUT = 0A)
-25
8
400
VREF
(VIN = -30V, IOUT = 1A)
-1.249
7
800
-1.247
-1.248
6
RCL (kΩ)
VDO
(VOUT = -10V)
1000
VDO (mV)
-1.246
5
1200
VREF
(VIN = -3.5V, IOUT = 1A)
-1.245
4
FIGURE 13. -20VIN, -10VOUT
FIGURE 12. -12VIN, -10VOUT
VREF (V)
6
7
RCL (kΩ)
2.5
1.6
0.0
5
FIGURE 11. -12VIN, -5VOUT
FIGURE 10. -7VIN, -5VOUT
CURRENT LIMIT (A)
4
125
150
0
0
100
200
300
400
500
600
700
800
CONTINUOUS OUTPUT CURRENT (mA)
FIGURE 15. DROP_OUT VOLTAGE vs TEMPERATURE
May 7, 2015
FN9054.4
ISL72991RH
Typical Performance Curves (Continued)
10
3.0
VLDR
(IOUT = 3mA TO 1A)
2.5
8
VLNR
(VIN = -4V TO -30V, IOUT = 100mA)
1.5
VLDR (mV)
VLNR (mV)
2.0
6
4
1.0
2
0.5
0.0
-50
-25
25
50
75
TEMPERATURE (°C)
0
100
0
125
FIGURE 16. LINE REGULATION vs TEMPERATURE
-40
-50
-50
PSRR (dB)
-60
PSRR (dB)
COUT = 10µF
COUT = 30µF
-90
10k
100k
1M
-100
10
10M
FIGURE 18. PSRR vs FREQUENCY (VIN = -20V, VOUT = -18V)
100
1k
10k
100k
1M
10M
FIGURE 19. PSRR vs FREQUENCY (VIN = -7V, VOUT = -5V)
200
45
40
180
35
PHASE
30
160
140
25
120
20
100
15
80
10
PHASE (°)
GAIN (dB)
125
FREQUENCY (Hz)
FREQUENCY (Hz)
60
5
40
GAIN
0
20
-5
-10
100
100
COUT = 30µF
-90
1k
50
25
75
TEMPERATURE (°C)
COUT = 10µF
-70
-80
100
0
-60
-80
-100
10
-25
FIGURE 17. LOAD REGULATION vs TEMPERATURE
-40
-70
-50
1k
10k
FREQUENCY (Hz)
100k
FIGURE 20. GAIN/PHASE -12VIN, -5VOUT, 0.5A IOUT
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1M
0
FIGURE 21. THERMAL (VIN = -12V, VOUT = -5V, IOUT = 0.74A,
TA = +25°C)
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FN9054.4
ISL72991RH
Functional Description
Layout Guidelines
The radiation hardened ISL72991RH is a low dropout adjustable
negative regulator with an output voltage range of -2.25V to -26V.
The device features a 1A output current capability, an adjustable
current limit pin (ILIM) and a shutdown pin (SD) for easy on/off
control. The part is constructed using the Intersil dielectrically
isolated, complimentary bipolar RSG process. It is immune to
single-event latch-up and has been specifically designed to provide
reliable performance in harsh radiation environments.
Application Information
Output Voltage Programming
The output voltage of the regulator can be programmed with two
external resistors and is described by Equation 1:
V OUT = – 1.25  1 + R 1  R 2  –  I ADJ  R 1 
The stability of the regulator is sensitive to layout. It is strongly
recommended that a continuous copper ground plane (1 oz. or
greater) be used. In addition, component lead lengths and
interconnects should be minimized, but should not exceed 1/2 inch.
Finally, the return lead of the compensation capacitor (CC) should be
connected as close as possible to the GND pin of the IC.
2.0
1.8
+25°C
1.6
CURRENT LIMIT (A)
Functional Overview
(EQ. 1)
1.4
1.2
-12VIN, -5VOUT
1.0
0.8
0.6
0.4
-7VIN, -5VOUT
0.2
Output Current Limit Programming
0.0
The output current limit threshold of the regulator is set with a single
external resistor (RCL) connected from ILIM to ground.
Figure 24 shows that for a given differential voltage (VIN to VOUT)
and temperature, the effect of VIN amplitude is less significant than
seen in Figure 22.
4
5
6
RCL (kΩ)
7
8
9
10
1.4
-7VIN, -5VOUT
1.2
CURRENT LIMIT (A)
Figure 23 shows the effect of temperature at a single VIN to VOUT
voltage condition across the RCL range of 2.1kΩ to 10kΩ.
3
FIGURE 22. ICL vs RCL AND VIN AMPLITUDE
The effective current limit at any single RCL value is influenced by
the VIN to VOUT difference, temperature and VIN amplitude.
Figures 22 through 24 illustrate these effects.
Figure 22 shows that for a given VOUT (-5V) and temperature
(+25°C) the effect of VIN to VOUT differential on the current limit
level is significant.
2
+25°C
1.0
0.8
-55°C
0.6
+125°C
0.4
0.2
Because of these numerous variables, there is no one formula
relating RCL to ICL that will suffice for the range of likely possible
conditions. Figures 10 through 13 on page 7provide guidance in
setting the RCL value for a limited number of possible conditions.
Users are advised to evaluate their specific condition for satisfactory
performance.
0.0
2
3
4
5
6
RCL (kΩ)
7
8
9
10
9
10
FIGURE 23. ICL vs RCL AND TEMPERATURE
1.4
Capacitor Selection
An output capacitor of at least 10µF must be used to insure stability
of the regulator. Additional capacitance may be added as required
to improve the dynamic response of the regulator. Solid tantalum or
ceramic capacitors are recommended.
Loop Compensation
CURRENT LIMIT (A)
An input capacitor is required if the regulator is located more than
6 inches from the power supply filter capacitors. A 10µF solid
tantalum capacitor is recommended.
+25°C
1.2
-12VIN, -10VOUT
1.0
0.8
0.6
-7VIN, -5VOUT
0.4
0.2
The output capacitor and ESR comprise a zero in the loop transfer
function that must be compensated with a pole to ensure loop
stability in accordance with Equation 2:
(EQ. 2)
C C  R2 = C OUT  ESR
0.0
2
3
4
5
6
RCL (kΩ)
7
8
FIGURE 24. ICL vs RCL AND VIN TO VOUT DIFFERENTIAL
The compensating capacitor should be a low ESR ceramic type.
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ISL72991RH
Package Characteristics
TOP METALLIZATION
Type: AlSiCu (Si 0.75-1%/Cu 0.5%)
Thickness: 16.0kÅ ± 2kÅ
Weight of Packaged Device
2.2 Grams (Typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Unbiased
Case Isolation to Any Lead: 20 x 109 Ω (min)
ASSEMBLY RELATED INFORMATION
Substrate & Lid Potential
Floating
Die Characteristics
ADDITIONAL INFORMATION
Die Dimensions
Worst Case Current Density
< 2 x 105 A/cm2
5870µm x 5210µm (231.1mils x 205.1mils)
Thickness: 483µm ± 25.4µm (19mils ± 1 mil)
PROCESS
Interface Materials
Dielectrically Isolated Radiation Hardened Silicon Gate
GLASSIVATION
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ± 1.0kÅ
Metallization Mask Layout
(1) VIN
28
(27) VIN
27
1
2
(2) VIN
(28) VIN
(14) VOUT
14
15
(16) VOUT
16
(15) VOUT
10
17
12
(12) ILIM
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18
(18) ADJUST
11
(11) GND
(17) SHUTDOWN
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FN9054.4
ISL72991RH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Revision.
DATE
REVISION
CHANGE
May 7, 2015
FN9054.4
Replaced Figures 10, 11, 12 and 13 on page 7.
Replaced Figures 22, 23 and 24 on page 9.
Updated Equation 1 on page 9: from VOUT = -1.25(1+R2/R1) - (IADJ x R2)
to VOUT = -1.25(1+R1/R2) - (IADJ x R1).
January 29, 2015
FN9054.3
“Typical Performance Curves” on page 7: Added Figures 18 and 19.
March 26, 2014
FN9054.2
Added Related Literature on page 1.
Added significant relevant content throughout the document, expanding from 3 to 12 pages.
June, 28, 2004
FN9054.1
Updated file.
July 9, 2001
FN9054.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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11
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FN9054.4
ISL72991RH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
e
A
INCHES
PIN NO. 1
ID AREA
SYMBOL
-A-
D
-B-
S1
b
E1
0.004 M
H A-B S
Q
D S
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HE2
L
E3
SEATING AND
BASE PLANE
c1
L
E3
BASE
METAL
(c)
b1
M
M
(b)
SECTION A-A
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.740
-
18.80
3
E
0.460
0.520
E1
-
0.550
-
E2
0.180
-
4.57
-
-
E3
0.030
-
0.76
-
7
2
e
LEAD FINISH
MIN
11.68
0.050 BSC
13.21
-
13.97
3
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.00
-
0.00
-
6
M
-
0.0015
-
0.04
-
N
28
28
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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FN9054.4
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