an1850

Application Note 1850
ISL75052SEH High Performance 3A LDO Evaluation
Board User Guide
Description
What’s Inside
The ISL75052SEH is a high-performance, adjustable,
low-voltage, high-current, low-dropout linear regulator
specified at 1.5A rated output current for input voltages from
4.0V to 13.2V. The LDO outputs can be adjusted from 0.6V to
12.7V by means of two preset resistors. Salient features of the
part include:
The evaluation kit contains the following:
• TID, ELDRS and SEE Rated
• Very Fast Load Transient Response
• ±2.0% Guaranteed VOUT Accuracy over Line, Load and
Temperature
• Typical Dropout of 225mV at 1.5A
• ISL75052SEHEVAL1Z evaluation board
• ISL75052SEH datasheet
• AN1850 application note
Test Steps
1. Select the desired output voltage by shorting one of the
jumpers from J1 through J5. The option of JP6 provides for
continuous adjustment of VOUT using potentiometer R6.
2. Set the OCP limit by using jumpers JP8 and JP9.
JP9 = 0.275A min, and JP8 = 2.75A min.
3. Close JP7. Also closing jumper JP11 (2 and 3) selects
R16 = 5.49k as pull-up for PGOOD. Close JP12 (1 and 2).
• EN Feature
• PG Feature
4. Connect the input supply to VIN/GND and the load to
VOUT/GND. Select the VIN to VOUT ratio to keep dissipation
within the thermal limits of the device.
• OCP Feature
• Short-circuit and Over-temperature Protection
The ISL75052SEHEVAL1Z evaluation board provides a simple
platform to evaluate performance of the ISL75052SEH. The
device output voltage is adjustable, and jumpers are provided
to easily set popular output voltages.
5. Use JP10 to enable/disable the IC; Open = Enable, and
Close = Disable. (Note: For REVB boards, Close = Enable
and Open = Disable.)
FIGURE 1. ISL75052SEHEVAL1Z EVALUATION BOARD
July 2, 2013
AN1850.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1850
Optimizing LDO Performance
Performance of the ISL75052SEH can be optimized by following
the guidelines provided in this application note.
Input and Output Capacitor Selection
RH operation requires the use of a combination of tantalum and
ceramic capacitors to achieve a good volume-to-capacitance
ratio. The recommended combination is a 2x100µF, 60mΩ, 25V
KEMET T541 series tantalum capacitor in parallel with a 0.1µF
MIL-PRF-49470 CDR04 ceramic capacitor. This is to be
connected between VIN to GND pins and VOUT to GND pins of the
LDO, with PCB traces no longer than 0.5cm. The stability of the
device depends on the capacitance and ESR of the output
capacitor. The usable ESR range for the device is 6mΩ to
100mΩ. At the lower limit of ESR = 6mΩ, the phase margin is
about 51°C. On the high side, an ESR of 100mΩ is found to limit
the gain margin at around 10dB. The typical GM/PM seen on the
ISL75052SEHEVAL1Z evaluation board for VIN = 3.3V,
VOUT = 1.8V, and IOUT = 3A, with a 220µF, 10V, 25mΩ capacitor,
is GM = 16.3dB and PM = 69.16°C.
Output Voltage Adjustment
The output voltage can be adjusted by means of the resistor
divider shown in Figure 2 as RTOP and RBOTTOM.
VIN
VOUT
ISL75052SEH
ADJ
VOUT
(V)
RTOP
(kΩ)
RBOTTOM
(kΩ)
COUT
(µF)
10.0
15.8
1.0
200
9.0
15.8
1.13
200
5.0
15.8
2.15
200
4.0
15.8
2.74
200
2.5
(Note 1)
15.8
4.87
47
2.5
15.8
4.87
200
NOTE:
1. Either option could be used depending on cost/performance
requirements.
Layout Guidelines
Good PCB layout is important to achieving expected
performance. When placing components and routing traces,
minimize ground impedance and keep parasitic inductance low.
Give the input and output capacitors a good ground connection,
and place them as close to the IC as possible. Route the traces
connecting the ADJ pin away from noisy planes and traces, and
keep the board capacitance of the ADJ net to GND as low as
possible.
Thermal Guidelines
PG
EN
TABLE 1. RECOMMENDED OUTPUT CAPACITOR VALUES
RTOP
COUT
CIN
OCP
RBOTTOM
FIGURE 2. ISL75052SEH TYPICAL APPLICATION
The resistor values for typical output voltages are given in
Table 1. The values listed provide for an Evaluation board output
voltage that is about 50mV higher than the desired set point to
allow for the drop on the line connecting the Evaluation board to
the desired load.
If the die temperature exceeds +175°C typical, then the LDO
output shuts down to zero until the die temperature cools to
+155°C typical. The level of power combined with the thermal
impedance of the package (JC of 4°C/W for the 18 Ld CDFP
package) determines whether the junction temperature exceeds
the thermal shutdown temperature specified in the “Electrical
Specifications” table of the ISL75052SEH datasheet. Mount the
device on a high effective thermal conductivity PCB with thermal
vias, per JESD51-7 and JESD51-5. Place a silpad between
package base and PCB copper plane. Select the VIN and VOUT
ratios to ensure that dissipation for the selected VIN range keeps
TJ within the recommended operating level of 150°C for normal
operation.
The resistor divider values can be calculated using the equation:
VOUT = (0.6X(1+RTOP/RBOTTOM)
Assuming a value RTOP = 15.8k and knowing the required output
voltage setting one can calculate the RBOTTOM.
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2
AN1850.0
July 2, 2013
Application Note 1850
Typical Performance Curves
ILOAD = 0A.
Unless otherwise specified, VIN = VOUT + 0.4V, VOUT = 2.5V, CIN = COUT = 200µF, TJ = +25°C,
VOUT
VOUT
EN
EN
VIN
VIN
PGOOD
PGOOD
1ms/DIV
FIGURE 3. START-UP WAVEFORMS: VIN = 4.0V, VOUT = 2.5V,
IOUT = 0.1A, EN LOW TO HIGH
1ms/DIV
FIGURE 4. START-UP WAVEFORMS: VIN = 4.0V, VOUT = 2.5V,
IOUT = 1.5A, EN LOW TO HIGH
VOUT
VOUT
VIN
VIN
PGOOD
PGOOD
EN
EN
5ms/DIV
FIGURE 5. SHUTDOWN WAVEFORM: VIN = 4.0V, VOUT = 2.5V,
IOUT = 0.1A EN HIGH TO LOW
VOUT
FIGURE 6. SHUTDOWN WAVEFORM: VIN = 4.0V, VOUT = 2.5V,
IOUT = 1.5A, EN HIGH TO LOW
VOUT
IOUT
IOUT
500µs/DIV
500µs/DIV
FIGURE 7. LOAD TRANSIENT, VIN = 13.2.0V, VOUT = 10.0V,
IOUT = 0A TO 1.6A, COUT = 200µF 30mΩ
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1ms/DIV
3
FIGURE 8. LOAD TRANSIENT, VIN = 13.2V, VOUT = 4.0V,
IOUT = 0.15A TO 1.6A, COUT = 200µF 30mΩ
AN1850.0
July 2, 2013
Application Note 1850
Typical Performance Curves
ILOAD = 0A. (Continued)
Unless otherwise specified, VIN = VOUT + 0.4V, VOUT = 2.5V, CIN = COUT = 200µF, TJ = +25°C,
0.30
0.30
DROPOUT V AT 150V
DROPOUT V AT 150V
DROPOUT VOLTAGE (V)
DROPOUT VOLTAGE (V)
0.25
DROPOUT V AT 125°C
0.20
DROPOUT V AT 25°C
0.15
0.10
0.05
0.00
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.25
DROPOUT V AT 125°C
0.20
0.10
0.05
0.00
1.6
DROPOUT V AT 25°C
0.15
0
0.2
0.4
0.6
IOUT (A)
FIGURE 9. DROPOUT vs I OUT AT VOUT = 3.6V
VIN = 5.5V, VOUT +25°C
2.55
VOUT (V)
2.56
VIN = 12.0V, VOUT +125°C
2.58
VIN = 4.5V, VOUT +25°C
2.57
VIN = 10.5V, VOUT +125°C
2.59
VIN = 4.0V, VOUT +25°C
2.58
VOUT (V)
1.6
2.57V +1.5%
2.60
2.59
VIN = 5.0V, VOUT +25°C
2.57
2.56
VIN = 14.7V, VOUT +125°C
VIN = 13.2V, VOUT +125°C
2.55
2.54
2.54
2.57V -1.5%
2.53
0
0.2
0.4
2.57V -1.5%
2.53
0.6
0.8
IOUT (A)
1.0
1.2
1.4
2.52
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IOUT (A)
FIGURE 11. LOAD REGULATION VOUT vs I OUT
FIGURE 12. LOAD REGULATION VADJ vs IOUT
10.35
2.61
2.57V +1.5%
2.60
2.59
VOUT (V)
VIN = 12.0V, VOUT +25°C
2.56
VIN = 14.7V, VOUT -55°C
10.20
10.15
VIN = 14.7V, VOUT +25°C
10.10
VIN = 13.2V, VOUT -55°C
2.54
VIN = 10.8V, VOUT +25°C
10.25
VIN = 12.0V, VOUT -55°C
2.57
2.55
10.17V +1.5%
10.30
VIN = 10.5V, VOUT -55°C
2.58
VOUT (V)
1.4
2.61
2.57V +1.5%
2.60
10.05
2.53
2.52
1.2
FIGURE 10. DROPOUT vs I OUT AT VOUT = 12.7V
2.61
2.52
0.8
1.0
IOUT (A)
2.57V -1.5%
0
0.2
0.4
0.6
0.8
1.0
1.2
IOUT (A)
FIGURE 13. LOAD REGULATION VOUT vs I OUT
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4
1.4
1.6
10.00
VIN = 13.2V, VOUT +25°C
10.17V -1.5%
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IOUT (A)
FIGURE 14. LOAD REGULATION VADJ vs IOUT
AN1850.0
July 2, 2013
Application Note 1850
Typical Performance Curves
Unless otherwise specified, VIN = VOUT + 0.4V, VOUT = 2.5V, CIN = COUT = 200µF, TJ = +25°C,
ILOAD = 0A. (Continued)
10.35
10.35
10.17V +1.5%
10.30
VIN = 10.8V, VOUT -55°C
10.25
VIN = 10.8V, VOUT +125°C
10.20
VOUT (V)
VOUT (V)
10.25
VIN = 12.0V, VOUT +125°C
10.15
10.10
VIN = 13.2V, VOUT +125°C
10.17V -1.5%
0
0.2
0.4
0.6
10.20
VIN = 14.7V, VOUT -55°C
10.15
0.8
1.0
1.2
1.4
10.05
10.00
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IOUT (A)
FIGURE 15. LOAD REGULATION VOUT vs IOUT
FIGURE 16. LOAD REGULATION VADJ vs I OUT
13.00
13.00
12.75V +1.5%
12.95
12.90
12.90
12.85
12.85
VIN = 13.2V, VOUT +25°C
12.80
12.75
12.70
12.65
12.55
0.2
12.75
VIN = 14.7, VOUT +125°C
12.70
12.60
VIN = 16.2V, VOUT +25°C
0.4
0.6
VIN = 16.2V, VOUT +125°C
VIN = 13.2V, VOUT +125°C
12.55
12.75V -1.5%
0
12.80
12.65
VIN = 14.7, VOUT +25°C
12.60
12.75V +1.5%
12.95
VOUT (V)
VOUT (V)
VIN = 13.2V, VOUT -55°C
10.17V -1.5%
IOUT (A)
12.50
VIN = 12.0V, VOUT -55°C
10.10
VIN = 14.7V, VOUT +125°C
10.05
10.00
10.17V +1.5%
10.30
0.8
1.0
1.2
1.4
12.50
1.6
12.75V -1.5%
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IOUT (A)
IOUT (A)
FIGURE 17. LOAD REGULATION VOUT vs I OUT
FIGURE 18. LOAD REGULATION VOUT vs I OUT
13.00
12.95 12.75V +1.5%
12.90
VOUT (V)
12.85
12.80
VIN = 14.7, VOUT -55°C
12.75
VIN = 13.2V, VOUT -55°C
12.70
12.65
12.60
12.55
12.50
VIN = 16.2V, VOUT -55°C
12.75V -1.5%
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IOUT (A)
FIGURE 19. LOAD REGULATION VOUT vs I OUT
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5
AN1850.0
July 2, 2013
VIN
COMP
12
NC
GND
100
R8
C11
DNP
DNP
JP7
C12
E
OUT
E
R7
15.8K
VOUTP
10K
1K
R5
1.13K
R4
2.15K
3
JP6
TP8
4
1
TP3
TP9
0
E
MMBZ5231B
C 3
NC
D1
A
680
R16
R17
2
Q1
2
R14
ADJ.
10.0V
VOUT OPTIONS
3
3
TP15
1
JP5
9.0V
JP4
5.0V
JP3
4.0V
JP2
JP1
E
2.5V
0.1UF
C7
E
2
1
GND
VADJ
VOUT
SP1
549
TP14
VCC5
R9
E
TP12
10K
R15
ENABLE
100000PF
R3
E
PAD METAL
2.74K
VOUT
VCC5
C13
R2
TP7
9
VCC5
ISL75052SEH
3K
OCP_MIN
JP9
R10
E
300
J4
TP4
OCP_MAX
JP8
R11
GND
100000PF
C6
DNP
C5A
DNP
C4A
100UF
C5
C4
100UF
VOUT
PG
TP6
E
10
PGOOD
2N7002-7-F
E
Application Note 1850
OCP
17
J3
VOUT
8
22.1K 1000PF
11
3
GRN
OCP
NC
C10
2
RED
TP10
TP5
7
R13
1
2
5
E
JP11
TP13
COMP
1
13
E
IN
680
GND
100000PF
VADJ
ENABLE
VCC5
LED1
VIN
3
R18
4
2
5.49K
EN
6
E
14
VIN
JP12
1
SSL_LXA3025IGC
E
15
ADJ
4.87K
TP2
16
OPEN
3
GND
VOUT
JP10
C9
R6
2
1K
BYP
VOUT
R1
C3
DNP
DNP
C2A
C1A
J2
1
R19
100000PF
BYP
U1
100000PF
6
100UF
C2
TP1
100UF
VIN
C8
TP11
VIN
R12
J1
C1
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Schematic
AN1850.0
July 2, 2013
Application Note 1850
Bill of Materials
PART NUMBER
QTY UNITS
REFERENCE
DESIGNATOR
DESCRIPTION
MFR
MANUFACTURER PART
TBD
ISL75052SEHEV1ZREVBPCB
AVX
CDR03BP102BKMR
AVX
C3, C6, C8, C9, C13 CAP-MILQUAL, SMD,
1812, 0.1µF, 50V, 10%,
BX, ROHS
CDR04BX104AKMR
ISL75052SEHEV1ZREVBPCB
1
ea
CDR03BP102BKMR
1
ea
CDR04BX104AKMR-T
5
ea
H1045-00104-16V10-T
1
ea
C7
T495E107K025ATE100-T
4
ea
C1, C2, C4, C5
108-0740-001
4
ea
J1-J4
JOHNSON
108-0740-001
CONN-JACK,
BANANA-SS-SDRLESS, COMPONENTS
VERTICAL, ROHS
131-4353-00
1
ea
SP1
TEKTRONIX
CONN-SCOPE PROBE
TEST PT, COMPACT, PCB
MNT, ROHS
1514-2
6
ea
TP1-TP6
CONN-TURRET,
TERMINAL POST, TH,
ROHS
5002
9
ea
TP7-TP15
CONN-MINI TEST POINT, KEYSTONE
VERTICAL, WHITE, ROHS
68000-236HLF-1X3
2
ea
JP11, JP12
CONN-HEADER, 1x3,
BREAKAWY 1X36,
2.54mm, ROHS
BERG/FCI
68000-236HLF
69190-202HLF
10
ea
JP1-JP10
CONN-HEADER, 1X2,
RETENTIVE, 2.54mm,
0.230X 0.120, ROHS
BERG/FCI
69190-202HLF
MMBZ5231B-7-F-T
1
ea
D1
DIODE-ZENER, SMD,
SOT-23, 3P, 5.1V,
350mW, ROHS
DIODES INC.
MMBZ5231B-7-F
SSL-LXA3025IGC-TR
1
ea
LED1
LED, SMD, 3x2.5mm,
4P, RED/GREEN,
12/20MCD, 2V
LUMEX
SSL-LXA3025IGC-TR
2N7002-7-F-T
1
ea
Q1
TRANSISTOR,
N-CHANNEL, 3LD,
SOT-23, 60V, 115mA,
ROHS
DIODES, INC. 2N7002-7-F
3299W-1-103LF
1
ea
R6
POT-TRIM, TH, 3P, 10k, BOURNS
1/2W, 10%, 3/8SQ,
25TURN, TOPADJ, ROHS
H2506-DNP
0
ea
R8
RESISTOR, SMD, 0805,
DNP, DNP, DNP, TF
H2511-00R00-1/10W-T
1
ea
R14
RES, SMD, 0603, 0Ω,
1/10W, TF, ROHS
H2511-01000-1/10W1-T
1
ea
R9
RES, SMD, 0603, 100Ω, VENKEL
1/10W, 1%, TF, ROHS
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7
SEE LABEL-RENAME PWB-PCB,
BOARD
ISL75052SEHEV1Z,
REVB, ROHS
C10
CAP-MILPRF-55681,
SMD, 1808, 0.001µF,
100V, 10%, ROHS
CAP, SMD, 0603, 0.1µF, MURATA
16V, 10%, X7R, ROHS
CAP-TANT, LOW ESR,
SMD, E, 100µF, 25V,
10%, 100mΩ, ROHS
KEMET
KEYSTONE
VENKEL
GRM39X7R104K016AD
MFR
PANASONIC
T495E107K025ATE100
131-4353-00
1514-2
5002
ON
SEMICONDUCTOR
3299W-1-103LF
CR0603-10W-000T
ROHM
CR0603-10W-1000FT
ROHM
AN1850.0
July 2, 2013
Application Note 1850
Bill of Materials
PART NUMBER
(Continued)
QTY UNITS
REFERENCE
DESIGNATOR
DESCRIPTION
MFR
MANUFACTURER PART
MFR
H2511-01001-1/10W1-T
1
ea
R5
RES, SMD, 0603, 1k,
1/10W, 1%, TF, ROHS
PANASONIC
ERJ-3EKF1001V
VENKEL
H2511-01002-1/10W1-T
1
ea
R12
RES, SMD, 0603, 10k,
1/10W, 1%, TF, ROHS
KOA
RK73H1JT1002F
VENKEL
H2511-01131-1/10W1-T
1
ea
R4
RES, SMD, 0603, 1.13k, YAGEO
1/10W, 1%, TF, ROHS
RC0603FR-071K13L
ROHM
H2511-01582-1/10W1-T
1
ea
R7
RES, SMD, 0603, 15.8k, VENKEL
1/10W, 1%, TF, ROHS
CR0603-10W-1582FT
PANASONIC
H2511-02151-1/10W1-T
1
ea
R3
RES, SMD, 0603, 2.15k, YAGEO
1/10W, 1%, TF, ROHS
RC0603FR-072K15L
VENKEL
H2511-02212-1/10W1-T
1
ea
R13
RES, SMD, 0603, 22.1k, PANASONIC
1/10W, 1%, TF, ROHS
ERJ-3EKF2212V
VENKEL
H2511-02741-1/10W1-T
1
ea
R2
RES, SMD, 0603, 2.74k, VENKEL
1/10W, 1%, TF, ROHS
CR0603-10W-2741FT
YAGEO
H2511-03000-1/10W1-T
1
ea
R11
RES, SMD, 0603, 300Ω, ROHM
1/10W, 1%, TF, ROHS
MCR03EZPFX3000
VISHAY/DALE
H2511-03001-1/10W1-T
1
ea
R10
RES, SMD, 0603, 3k,
1/10W, 1%, TF, ROHS
RC0603FR-073KL
VENKEL
H2511-04871-1/10W1-T
1
ea
R1
RES, SMD, 0603, 4.87k, PANASONIC
1/10W, 1%, TF, ROHS
ERJ-3EKF4871V
VISHAY/DALE
H2511-05490-1/10W1-T
1
ea
R15
RES, SMD, 0603, 549Ω, VENKEL
1/10W, 1%, TF, ROHS
CR0603-10W-5490FT
PANASONIC
H2511-05491-1/10W1-T
1
ea
R16
RES, SMD, 0603, 5.49k, VENKEL
1/10W, 1%, TF, ROHS
CR0603-10W-5491FT
YAGEO
H2511-06800-1/10W1-T
2
ea
R17, R18
RES, SMD, 0603, 680Ω, ROHM
1/10W, 1%, TF, ROHS
MCR03EZPFX6800
VENKEL
H2520-01001-1/2W1-T
1
ea
R19
RES, SMD, 2010, 1k,
1/2W, 1%, TF, ROHS
ERJ-12SF1001U
VISHAY/DALE
4-40X1/4-SCREW-SS
4
ea
Four corners
SCREW, 4-40X1/4in,
PAN, SS, PHILLIPS
4-40X3/4-STANDOFF-METAL
4
ea
Four corners
STANDOFF, 4-40X3/4in, KEYSTONE
F/F, HEX, ALUMINUM,
ROHS
2204 (.250 OD)
8X8-STATIC-BAG
1
ea
Place assy in bag
BAG, STATIC, 8X8, ZIP
LOC, ROHS
ULINE
S-5092
DNP
0
ea
U1
DO NOT POPULATE OR
(ISL75052SEHQF) PURCHASE
LABEL-DATE CODE
1
ea
LABEL-DATE
CODE_BOM
REV#_SERIAL# LABEL
ON ZIL & QUEL
INTERSIL
LABEL-DATE CODE
LABEL-RENAME BOARD
1
ea
INTERSIL
LABEL-RENAME BOARD
Submit Document Feedback
8
RENAME PCB TO: LABEL, TO RENAME
ISL75052SEHEVAL1Z BOARD
YAGEO
PANASONIC
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Layout
FIGURE 20. SILK SCREEN TOP
FIGURE 21. TOP LAYER COMPONENT SIDE
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(Continued)
FIGURE 22. LAYER 2
FIGURE 23. LAYER 3
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(Continued)
FIGURE 24. BOTTOM LAYER SOLDER SIDE
FIGURE 25. SILK SCREEN BOTTOM
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(Continued)
FIGURE 26. SILK SCREEN BOTTOM MIRROR
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cautioned to verify that the document is current before proceeding.
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Drill Drawings
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