DATASHEET

CD4071BMS, CD4072BMS
ESIGNS
CD4075BMS
R NEW D N T
O
F
D
E
E
END
PL AC E M
ECOMM
December 1992
E D RE
NO T R
nter at
MMEND
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NO
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tersil.co
our Tech
contact ERSIL or www.in
T
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Features
CMOS OR Gate
Pinout
• High-Voltage Types (20V Rating)
CD4071BMS
TOP VIEW
• CD4071BMS Quad 2-Input OR Gate
• CD4072BMS Dual 4-Input OR Gate
A 1
14 VDD
B 2
13 H
J=A+B 3
12 G
K=C+C 4
11 M = G + H
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation:
- tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics
C 5
10 L = E + F
D 6
9 F
VSS 7
8 E
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
CD4072BMS
TOP VIEW
14 VDD
J=A+B+C+D 1
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
A 2
13 K = E +F + G + H
B 3
12 H
C 4
11 G
Description
D 5
10 F
NC 6
9 E
CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the
positive-logic OR function and supplement the existing family of CMOS gates.
NC = NO CONNECTION
The CD4071BMS, CD4072BMS and CD4075BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP
*H4H
Frit Seal DIP
H1B
Ceramic Flatpack
H3W
*CD4071, CD4072
†CD4075 Only
8 NC
VSS 7
CD4075BMS
TOP VIEW
†H4Q
A 1
14 VDD
B 2
13 G
D 3
12 H
E 4
11 I
F 5
10 L = G + H + I
K=D+E+F 6
VSS 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-444
9 J=A+B+C
8 C
File Number
3323
CD4071BMS, CD4072BMS, CD4075BMS
Functional Diagram
VDD
14
1
2
3
5
6
4
8
9
10
12
13
11
B
A
D
C
F
E
H
G
J
K
L
M
7
VSS
CD4071BMS
VDD
14
A
B
C
D
2
3
1
4
J
5
9
E
10
F
11
G
12
H
13
K
7
VSS
CD4072BMS
VDD
14
C
B
A
F
1
9
2
4
6
5
D
11
I
12
H
13
G
10
E
J
8
3
7
VSS
CD4075BMS
7-445
K
L
Specifications CD4071BMS, CD4072BMS, CD4075BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input  10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm  0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
TEMPERATURE
MIN
MAX
1
+25oC
-
0.5
A
2
+125oC
-
50
A
3
-55oC
-
0.5
A
1
+25
oC
-100
-
nA
2
+125oC
-1000
-
nA
VDD = 18V
3
-55oC
-100
-
nA
VDD = 20
1
+25oC
-
100
nA
nA
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
Input Leakage Current
IIL
IIH
VIN = VDD or GND
VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
VDD = 20
VDD = 18V
o
UNITS
2
+125 C
-
1000
3
-55oC
-
100
nA
-
50
mV
-
V
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
o
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25 C
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10A
1
+25oC
-2.8
-0.7
V
oC
0.7
2.8
V
P Threshold Voltage
Functional
VPTH
F
VSS = 0V, IDD = 10A
1
+25
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
VOH > VOL <
VDD/2 VDD/2
V
-55oC
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25 C, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-446
o
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Transition Time
SYMBOL
TPHL
TPLH
TTHL
TTLH
CONDITIONS (NOTES 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
10, 11
VDD = 5V, VIN = VDD or GND
+25oC
9
+125
-55oC
+25oC
9
10, 11
oC,
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
250
ns
-
338
ns
-
200
ns
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
-55oC, +25oC
-
0.25
A
-
7.5
A
+125
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
oC,
oC
+25oC
-
0.5
A
+125oC
-
15
A
oC,
-
0.5
A
-55
-55
+25oC
o
+125 C
-
30
A
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
0.64
-
mA
0.9
-
mA
1.6
-
mA
-55
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125oC
-55
Output Current (Sink)
Output Current (Source)
IOL15
IOH5A
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-
-0.64
mA
-
-1.15
mA
-
-2.0
mA
-
-0.9
mA
-
-2.6
mA
oC
+125oC
-55
Output Current (Source)
oC
+125
-55
Output Current (Source)
oC
oC
+125oC
o
-55 C
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
oC
-
-2.4
mA
-55oC
-
-4.2
mA
+125
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
7
-
V
Propagation Delay
TPHL
TPLH
1, 2, 3
+25oC
-
120
ns
1, 2, 3
oC
-
90
ns
VDD = 10V
VDD = 15V
7-447
+25
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Transition Time
TTHL
TTLH
Input Capacitance
CONDITIONS
VDD = 10V
VDD = 15V
CIN
Any Input
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
-
100
ns
o
1, 2, 3
+25 C
-
80
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
VTN
P Threshold Voltage
VTP
VTP
P Threshold Voltage
Delta
Functional
F
CONDITIONS
NOTES
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10A
TEMPERATURE
o
-
2.5
A
1, 4
+25
oC
-2.8
-0.2
V
oC
-
1
V
0.2
2.8
V
-
1
V
+25
VSS = 0V, IDD = 10A
1, 4
+25oC
1, 4
oC
+25
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
UNITS
+25 C
1, 4
VDD = 18V, VIN = VDD or GND
MAX
1, 4
VDD = 10V, ISS = -10A
VSS = 0V, IDD = 10A
MIN
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - SSI
IDD
0.1A
Output Current (Sink)
IOL5
 20% x Pre-Test Reading
IOH5A
 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
7-448
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
Group B
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V  -0.5V
50kHz
3, 4, 10, 11
1, 2, 5, 6, 8, 9, 12,
13
1, 13
2 - 5, 9 - 12
6, 9, 10
1 - 5, 8, 11 - 13
25kHz
PART NUMBER CD4071BMS
Static Burn-In 1
Note 1
3, 4, 10, 11
1, 2, 5 - 9, 12 - 13
14
Static Burn-In 2
Note 1
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9,
12 - 14
Dynamic BurnIn Note 1
-
7
14
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9,
12 - 14
Irradiation
Note 2
PART NUMBER CD4072BMS
Static Burn-In 1
Note 1
1, 6, 8, 13
2 - 5, 7, 9 - 12
14
Static Burn-In 2
Note 1
1, 6, 8, 13
7
2 - 5, 9 - 12, 14
Dynamic BurnIn Note 1
6, 8
7
14
1, 6, 8, 13
7
2 - 5, 9 - 12, 14
Irradiation
Note 2
PART NUMBER CD4075BMS
Static Burn-In 1
Note 1
6, 9, 10
1 - 5, 7, 8, 11 - 13
14
Static Burn-In 2
Note 1
6, 9, 10
7
1 - 5, 8, 11 - 14
Dynamic BurnIn Note 1
-
7
14
6, 9, 10
7
1 - 5, 8, 11 - 14
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V  0.5V
7-449
CD4071BMS, CD4072BMS, CD4075BMS
VDD
14
p
p
p
p
n
n
n
p
*
1 (6, 8, 13)
n
p
*
2 (5,9, 12)
VDD
3 (4, 10, 11)
n
VSS
*
n
7
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)
B
1 (6, 8, 13)
J
A
3 (4, 10, 11)
2 (5, 9, 12)
FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)
VDD
INV.1**
VDD
p
p
p
VDD
n
p
2 (12)
VDD
p
*
p
1 (13)
n
n
n
VSS
VSS
VDD
p
3 (11)
*
*
5 (9)
n
n
VSS
VSS
p
INV 2**
VDD
n
INV 3**
n
4 (10)
*
VSS
INV 4**
VSS
** INVERTERS 2, 3 AND 4 ARE IDENTICAL TO INVERTER 1.
*
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)
7-450
CD4071BMS, CD4072BMS, CD4075BMS
A
2 (12)
B
3 (11)
J
D
1 (13)
5 (9)
C
4 (10)
FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)
VDD
14
p
p
p
n
p
p
n
n
p
9 (6, 10)
8 (5, 13)
*
n
n
2 (4, 12)
p
n
*
n
VDD
p
n
*
1 (3, 11)
n
VSS
*
7
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)
A
1 (3, 11)
J
B
2 (4, 12)
9 (6, 10)
C
8 (5, 13)
FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)
7-451
CD4071BMS, CD4072BMS, CD4075BMS
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
15
10V
10
5V
5
0
5
10
15
INPUT VOLTAGE (VIN) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
20
10V
10
5V
5
10
50
10V
15V
10.0
10V
7.5
5.0
2.5
5V
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-5
-20
-30
FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
-25
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-10
-15V
-15
FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-452
TE (PD) (W)
105
AMBIENT TEMPERATURE (TA) = +25oC
LH) (ns)
10
FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
-15
-15V
5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-10
-10V
80
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
0
FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
60
15.0
15
AMBIENT TEMPERATURE (TA) = +25oC
40
AMBIENT TEMPERATURE (TA) = +25oC
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
20
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
25
0
100
LOAD CAPACITANCE (CL) (pF)
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
5
SUPPLY VOLTAGE (VDD) = 5V
0
AMBIENT TEMPERATURE (TA) = +25oC
15
AMBIENT TEMPERATURE (TA) = +25oC
150
20
FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS
30
200
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
OUTPUT VOLTAGE (VO) (V)
20
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
Typical Performance Characteristics
8
6
4
2
104
8
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
10V
CD4071BMS, CD4072BMS, CD4075BMS
Chip Dimensions and Pad Layouts
CD4071BMS
CD4072BMS
CD4075BMS
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ 14kÅ,
AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
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