DATASHEET

Rad-Hard, 5.0V/3.3V µ-Processor Supervisory Circuits
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
This family of devices are radiation hardened 5.0V/3.3V
supervisory circuits that reduce the complexity required to
monitor supply voltages in microprocessor systems. These
devices significantly improve accuracy and reliability relative to
discrete solutions. Each IC provides four key functions.
1. A reset output during power-up, power-down, and brownout
conditions.
2. An independent watchdog output that goes low if the
watchdog input has not been toggled within 1.6s.
3. A precision threshold detector for monitoring a power
supply other than VDD.
4. An active-low manual-reset input.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the “Ordering Information” table on page 3
must be used when ordering.
Detailed Electrical Specifications for the ISL705AEH,
ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH and
ISL706CEH are contained in SMD 5962-11213. A “hot-link” is
also provided on our website for downloading.
Features
• Electrically Screened to SMD 5962-11213
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardness
- High Dose Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- Low Dose Rate . . . . . . . . . . . . . . . . . . . 100krad(Si) (Note 1)
- SEL/SEB LETTH . . . . . . . . . . . . . . . . . . . . 86MeV * cm2/mg
• Precision Supply Voltage Monitor
- 4.65V Threshold in the ISL705AEH/BEH/CEH
- 3.08V Threshold in the ISL706AEH/BEH/CEH
• 200ms (Typ) Reset Pulse Width
- Active High, Active Low and Open Drain Options
• Independent Watchdog Timer with 1.6s (Typ) Timeout
• Precision Threshold Detector
- 1.25V Threshold in the ISL705AEH/BEH/CEH
- 0.6V Threshold in the ISL706AEH/BEH/CEH
• Debounced TTL/CMOS Compatible Manual-Reset Input
• Reset Output Valid at VDD = 1.2V
Applications
• Supervisor for µ-Processors, µ-Controllers, FPGAs and DSPs
Related Literature
• Critical Power Supply Monitoring
• AN1650, “ISL705XRH Evaluation Board User’s Guide”
• Reliable Replacement of Discrete Solutions
• AN1671, “ISL706xRH Evaluation Board User’s Guide”
• AN1651, “Single Event Effects (SEE) Testing of the
ISL705xRH/EH and ISL706xRH/EH Rad Hard Supervisory
Circuits”
5V POWER SUPPLY
1.4
1.2
VCC
WDO 8
NMI
2 VDD
RST 7
RST
3 GND
WDI 6
I/O
4 PFI
PFO
49.9k
µP
5
ISL705xEH
1.0
VPFI (V)
165k
1 MR
0.8
0.6
0.4
ISL706xEH
0.2
ISL705AEH
0
5V SUPERVISOR APPLICATION WITH OVERVOLTAGE PROTECTION
0
25
50
75
100
125
150
krad (Si)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. PRECISION THRESHOLD DETECTOR LOW DOSE
IONIZING CHARACTERISTIC CURVE
NOTE:
1. Product capability established by initial characterization. The EH version is acceptance tested on a wafer by wafer basis to 50krad(Si) at low dose rate.
March 30, 2012
FN8262.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Pin Configurations
ISL705BEH, ISL706BEH
(8 LD FLATPACK)
TOP VIEW
ISL705AEH, ISL706AEH
(8 LD FLATPACK)
TOP VIEW
ISL705CEH, ISL706CEH
(8 LD FLATPACK)
TOP VIEW
MR
1
8
WDO
MR
1
8
WDO
MR
1
8
WDO
VDD
2
7
RST
VDD
2
7
RST
VDD
2
7
RST_OD
GND
3
6
WDI
GND
3
6
WDI
GND
3
6
WDI
PFI
4
5
PFO
PFI
4
5
PFO
PFI
4
5
PFO
Pin Descriptions
ISL705AEH
ISL706AEH
ISL705BEH
ISL706BEH
ISL705CEH
ISL706CEH
NAME
DESCRIPTION
1
1
1
MR
Manual Reset. MR is an active-low, debounced, TTL/CMOS compatible input that may
be used to trigger a reset pulse.
2
2
2
VDD
Power Supply. VDD is a supply voltage input that provides power to all internal circuitry.
This input is also monitored and used to trigger a reset pulse. Reset is guaranteed
operable after VDD rises above 1.2V.
3
3
3
GND
Ground. GND is a supply voltage return for all internal circuitry. This return establishes
the reference level for voltage detection and should be connected to signal ground.
4
4
4
PFI
Power Fail Input. PFI is an input to a threshold detector, which may be used to monitor
another supply voltage level. The threshold of the detector (VPFI) is 1.25V in the
ISL705AEH/BEH/CEH and 0.6V in the ISL706AEH/BEH/CEH.
5
5
5
PFO
Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that
indicates the voltage at the PFI pin is less than VPFI.
6
6
6
WDI
Watchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes
low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay cleared
and will not count. As soon as reset is released and WDI is driven high or low, the timer
will start counting. Floating WDI or connecting WDI to a high impedance tri-state buffer
disables the watchdog feature.
7
-
-
RST
Reset. RST is an active-low, push-pull output that is guaranteed to be low once VDD
reaches 1.2V. As VDD rises, RST stays low. When VDD rises above a 4.65V
(ISL705AEH/BEH/CEH) or 3.08V (ISL706AEH/BEH/CEH) reset threshold, an internal
timer releases RST after about 200ms. RST pulses low whenever VDD goes below the
reset threshold. If a brownout condition occurs in the middle of a previously initiated
reset pulse, the pulse will continue for at least 140ms. On power-down, once VDD falls
below the reset threshold, RST goes low and is guaranteed low until VDD drops below
1.2V.
Reset. RST is an active-high, push-pull output. RST is the inverse of RST.
-
7
-
RST
-
-
7
RST_OD
Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.
This pin may be pulled up to VDD with a resistor consistent with the sink and leakage
current specifications of the output. Behavior is otherwise identical to the RST pin.
8
8
8
WDO
Watchdog Output. WDO is an active-low, push-pull output that goes low if the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is
usually connected to the non-maskable interrupt input of a microprocessor. When VDD
drops below the reset threshold, WDO will go low whether or not the watchdog timer
has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since
floating WDI disables the internal timer, WDO goes low only when VDD drops below the
reset threshold, thus functioning as a low line output.
2
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Ordering Information
ORDERING NUMBER
PART NUMBER
TEMP RANGE
(°C)
PACKAGE
(RoHs Compliant)
5962R1121307VXC
ISL705AEHVF (Note 2)
-55 to +125
8 Ld Flatpack
5962R1121307V9A
ISL705AEHVX
-55 to +125
Die
ISL705ARHF/PROTO
ISL705ARHF/PROTO (Note 2)
-55 to +125
8 Ld Flatpack
ISL705ARHX/SAMPLE
ISL705ARHX/SAMPLE
-55 to +125
Die
5962R1121308VXC
ISL705BEHVF (Note 2)
-55 to +125
8 Ld Flatpack
5962R1121308V9A
ISL705BEHVX
-55 to +125
Die
ISL705BRHF/PROTO
ISL705BRHF/PROTO (Note 2)
-55 to +125
8 Ld Flatpack
ISL705BRHX/SAMPLE
ISL705BRHX/SAMPLE
-55 to +125
Die
5962R1121309VXC
ISL705CEHVF (Note 2)
-55 to +125
8 Ld Flatpack
5962R1121309V9A
ISL705CEHVX
-55 to +125
Die
ISL705CRHF/PROTO
ISL705CRHF/PROTO (Note 2)
-55 to +125
8 Ld Flatpack
ISL705CRHX/SAMPLE
ISL705CRHX/SAMPLE
-55 to +125
Die
5962R1121310VXC
ISL706AEHVF (Note 2)
-55 to +125
8 Ld Flatpack
5962R1121310V9A
ISL706AEHVX
-55 to +125
Die
ISL706ARHF/PROTO
ISL706ARHF/PROTO (Note 2)
-55 to +125
8 Ld Flatpack
ISL706ARHX/SAMPLE
ISL706ARHX/SAMPLE
-55 to +125
Die
5962R1121311VXC
ISL706BEHVF (Note 2)
-55 to +125
8 Ld Flatpack
5962R1121311V9A
ISL706BEHVX
-55 to +125
Die
ISL706BRHF/PROTO
ISL706BRHF/PROTO (Note 2)
-55 to +125
8 Ld Flatpack
ISL706BRHX/SAMPLE
ISL706BRHX/SAMPLE
-55 to +125
Die
5962R1121312VXC
ISL706CEHVF (Note 2)
-55 to +125
8 Ld Flatpack
5962R1121312V9A
ISL706CEHVX
-55 to +125
Die
ISL706CRHF/PROTO
ISL706CRHF/PROTO (Note 2)
-55 to +125
8 Ld Flatpack
ISL706CRHX/SAMPLE
ISL706CRHX/SAMPLE
-55 to +125
Die
ISL705XRHEVAL1Z
ISL705XRH Evaluation Board
ISL706XRHEVAL1Z
ISL706XRH Evaluation Board
PKG. DWG. #
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
K8.A
NOTE:
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
3
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Functional Block Diagrams
VDD
VDD
VDD
RST
RST_OD
POR
RST
POR
+- VREF
+- VREF
MR
+- VREF
MR
MR
PB
PB
PB
WDO
WDI
POR
WDO
WDT
PFI
PF
PFI
PFO
+- VREF
WDO
WDT
WDI
WDI
PF
+- VREF
GND
ISL705AEH, ISL706AEH
PFO
WDT
PFI
PF
+- VREF
GND
ISL705BEH, ISL706BEH
PFO
GND
ISL705CEH, ISL706CEH
Timing Diagrams
VRST
VDD
1.2V
>tMR
MR
tRST
tRST
tRST
RST
<tMD
RST
FIGURE 3. RST, RST, MR AND WDO TIMING DIAGRAM
VRST
VDD
1.2V
< tWD
< tWD
< tWD
WDI
tWD
>tWP
tWD
WDO
tRST
RST
tRST
FIGURE 4. WATCHDOG TIMING DIAGRAM
4
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ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Voltage on All Other Inputs . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . .3.0kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . .1.0kV
Latch Up (Tested per JESD-78C) . . . . . . . . . . . . . . . . . . . . . . Class 2, Level A
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld Flatpack Package (Notes 3, 4). . . . . .
140
15
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
ISL705AEH/BEH/CEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.5V
ISL706AEH/BEH/CEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For θJC, the “case temp” location is the center of the package underside.
Electrical Specifications
Unless otherwise specified VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V for the
ISL706AEH/BEH/CEH TA = -55°C to +125°C. Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total ionizing dose of
100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of
<10mrad(Si)/s.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 6) (Note 5) UNITS
POWER SUPPLY SECTION
VDD
IDD
Operating Supply Voltage (Note 7)
Operating Supply Current
ISL705AEH/BEH/CEH
1.2
5
5.5
V
ISL706AEH/BEH/CEH
1.2
3.3
3.6
V
ISL705AEH/BEH/CEH
530
µA
ISL706AEH/BEH/CEH
400
µA
RESET SECTION
VRST
VHYS
Reset Threshold Voltage
Reset Threshold Voltage Hysteresis
tRST
Reset Pulse Width
VOUT
Reset Output Voltage
ISL705AEH/BEH/CEH
4.50
4.65
4.75
V
ISL706AEH/BEH/CEH
3.00
3.08
3.15
V
ISL705AEH/BEH/CEH
20
40
mV
ISL706AEH/BEH/CEH
20
30
mV
140
200
ISL705AEH/BEH, ISOURCE = 800µA
VDD - 1.5
ISL705AEH/BEH/CEH, ISINK = 3.2mA
ISL706AEH/BEH, ISOURCE = 500µA
Reset Output Leakage Current
5
ms
V
0.4
0.8 x VDD
V
V
ISL706AEH/BEH/CEH, ISINK = 1.2mA
0.3
V
ISL70XAEH/CEH, VDD = 1.2V, ISINK = 100µA
0.3
V
ISL70XBEH, VDD = 1.2V, ISOURCE = 4µA
ILEAK
280
0.9
V
ISL705CEH, VOUT = VDD
1
µA
ISL706CEH, VOUT = VDD
1
µA
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Electrical Specifications
Unless otherwise specified VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V for the
ISL706AEH/BEH/CEH TA = -55°C to +125°C. Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total ionizing dose of
100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of
<10mrad(Si)/s. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 6) (Note 5) UNITS
WATCHDOG SECTION
tWD
Watchdog Time-Out Period
tWP
Watchdog Input (WDI) Pulse Width
VIL
Watchdog Input (WDI) Threshold Voltage
1.00
ns
ISL706AEH/BEH/CEH, VIL = 0.4V, VIH = 0.8 x VDD
100
ns
ISL705AEH/BEH/CEH
VIL
ISL706AEH/BEH/CEH
VIH
ISL706AEH/BEH/CEH
0.8
3.5
0.6
0.7 x VDD
Watchdog Output (WDO) Voltage
ISL705AEH/BEH/CEH, ISOURCE = 800µA
100
-100
µA
µA
5
µA
-5
µA
VDD - 1.5
V
ISL705AEH/BEH/CEH, ISINK = 1.2mA
ISL706AEH/BEH/CEH, ISOURCE = 500µA
V
V
ISL706AEH/BEH/CEH, WDI = VDD
ISL706AEH/BEH/CEH, WDI = 0V
V
V
ISL705AEH/BEH/CEH, WDI = VDD
ISL705AEH/BEH/CEH, WDI = 0V
VWDO
s
50
ISL705AEH/BEH/CEH
Watchdog Input (WDI) Current
2.25
ISL705AEH/BEH/CEH, VIL = 0.4V, VIH = 0.8 x VDD
VIH
IWDI
1.60
0.4
0.8 x VDD
V
V
ISL706AEH/BEH/CEH, ISINK = 500µA
0.3
V
MANUAL RESET SECTION
IMR
tMR
VIL
Manual Reset (MR) Pull-up Current
Manual Reset (MR) Pulse Width
Manual Reset (MR) Input Threshold Voltage
ISL705AEH/BEH/CEH, MR = 0V
-500
-100
µA
ISL706AEH/BEH/CEH, MR = 0V
-250
-25
µA
ISL705AEH/BEH/CEH
150
ns
ISL706AEH/BEH/CEH
150
ns
ISL705AEH/BEH/CEH
VIH
2.0
VIL
0.6
0.7 x VDD
Manual Reset (MR) to Reset Out Delay
V
V
ISL706AEH/BEH/CEH
VIH
tMD
0.8
V
V
ISL705AEH/BEH/CEH
100
ns
ISL706AEH/BEH/CEH
100
ns
THRESHOLD DETECTOR SECTION
VPFI
IPFI
VPFO
Power Fail Input (PFI) Input Threshold
Voltage
ISL705AEH/BEH/CEH
1.20
1.25
1.30
V
ISL706AEH/BEH/CEH
0.576
0.6
0.624
V
10
nA
Power Fail Input (PFI) Input Current
Power Fail Output (PFO) Output Voltage
-10
ISL705AEH/BEH/CEH, ISOURCE = 800µA
VDD - 1.5
V
ISL705AEH/BEH/CEH, ISINK = 3.2mA
ISL706AEH/BEH/CEH, ISOURCE = 500µA
0.4
0.8 x VDD
V
ISL706AEH/BEH/CEH, ISINK = 1.2mA
tRPFI
V
0.3
V
PFI Rising Threshold Crossing to PFO Delay ISL705AEH/BEH/CEH
7
15
µs
ISL706AEH/BEH/CEH
11
20
µs
6
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Electrical Specifications
Unless otherwise specified VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V for the
ISL706AEH/BEH/CEH TA = -55°C to +125°C. Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total ionizing dose of
100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of
<10mrad(Si)/s. (Continued)
SYMBOL
PARAMETER
tFPFI
MIN
(Note 5)
CONDITIONS
TYP
MAX
(Note 6) (Note 5) UNITS
PFI Falling Threshold Crossing to PFO Delay ISL705AEH/BEH/CEH
20
35
µs
ISL706AEH/BEH/CEH
25
40
µs
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Typical values shown reflect TA = TJ = +25°C operation and are not guaranteed.
7. Reset is the only parameter operable within 1.2V and the minimum recommended operating supply voltage.
Typical Performance Curves
550
5.0
500
4.5
450
VRST (V)
IDD (µA)
400
350
300
3.5
3.0
ISL706xEH
ISL706xEH
2.5
250
200
-80
ISL705xEH
4.0
ISL705xEH
-60
-40
-20
0
20
40
60
80
100 120 140
2.0
-80
-60
TEMPERATURE (°C)
-40
-20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
FIGURE 5. IDD vs TEMPERATURE
FIGURE 6. VRST vs TEMPERATURE
1.4
1.2
VDD
ISL705xEH
VPFI (V)
1.0
0.8
RST
0.6
0.4
ISL706xEH
RST
0.2
0
-80
-60
-40
-20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
FIGURE 7. VPFI vs TEMPERATURE
7
FIGURE 8. ISL705xEH RESET and RESET ASSERTION
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Typical Performance Curves (Continued)
VDD
VDD
RST
RST
RST
RST
FIGURE 9. ISL706xEH RESET AND RESET ASSERTION
FIGURE 10. ISL705xEH RESET AND RESET DEASSERTION
VDD
PFO
RST
PFI
RST
FIGURE 11. ISL706xEH RESET AND RESET DEASSERTION
FIGURE 12. ISL705xEH PFI TO PFO RESPONSE
PFO
PFI
FIGURE 13. ISL706xEH PFI TO PFO RESPONSE
8
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Post Radiation Characteristics Unless otherwise specified, VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V
for the ISL706AEH/BEH/CEH TA = +25°C. This data is parameter deltas post radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to
show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed.
SYMBOL
PARAMETER
CONDITIONS
0 - 25kRad
0 - 50kRad
0 - 75kRad
0 - 100kRad
UNITS
ISL705AEH/BEH/CEH
-2
-2.44
-3.86
-4.88
µA
ISL706AEH/BEH/CEH
-4.79
-7.47
-6.93
-8.88
µA
ISL705AEH/BEH/CEH
-8.1
-13.1
-17.5
-18.1
mV
ISL706AEH/BEH/CEH
-1
-3.25
-5.38
-7.25
mV
ISL705AEH/BEH/CEH
-3.75
-1.9
-5
-3.12
mV
ISL706AEH/BEH/CEH
0.375
0.25
0.625
0.625
mV
-2.13
-2.18
-2.39
-2.35
ms
-56
-72
-81
-80
ms
ISL705AEH/BEH/CEH
0.028
0.146
0.274
0.368
ns
ISL706AEH/BEH/CEH
0.305
0.605
0.793
0.956
ns
0.94
0.31
0
-0.62
mV
POWER SUPPLY SECTION
IDD
Operating Supply Current
RESET SECTION
VRST
Reset Threshold Voltage
VHYS
Reset Threshold Voltage
Hysteresis
tRST
Reset Pulse Width
WATCHDOG SECTION
tWD
Watchdog Time-Out Period
MANUAL RESET SECTION
tMD
Manual Reset (MR) to Reset
Out Delay
THRESHOLD DETECTOR SECTION
VPFI
Power Fail Input (PFI) Input
Threshold Voltage
ISL705AEH/BEH/CEH
ISL706AEH/BEH/CEH
-1.56
-2.5
-2.5
-2.5
mV
tRPFI
PFI Rising Threshold
Crossing to PFO Delay
ISL705AEH/BEH/CEH
-0.026
-0.047
-0.085
-0.068
µs
ISL706AEH/BEH/CEH
0.028
-0.058
0.11
-0.11
µs
PFI Falling Threshold
Crossing to PFO Delay
ISL705AEH/BEH/CEH
-0.397
-0.77
-1.17
-2.88
µs
ISL706AEH/BEH/CEH
-0.35
-0.782
-1.516
-2.087
µs
tFPFI
Post Radiation Characteristics Unless otherwise specified, VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V
for the ISL706AEH/BEH/CEH TA = +25°C. This data is typical mean test data post radiation exposure at a rate of <10mrad(Si)/s. This data is intended
to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed
540
4.80
530
4.75
520
VRST (V)
IDD (µA)
BIASED
500
490
480
4.65
4.60
GROUNDED
4.55
470
GROUNDED
460
450
0
BIASED
4.70
510
25
50
75
krad(Si)
100
4.50
125
150
FIGURE 14. ISL705xEH IDD vs LOW DOSE RATE RADIATION
9
4.45
0
25
50
75
krad(Si)
100
125
150
FIGURE 15. ISL705xEH VRST vs LOW DOSE RATE RADIATION
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
240
100
90
80
70
60
50
40
30
20
10
0
220
GROUNDED
BIASED
tRST (ms)
VHYS (mV)
Post Radiation Characteristics Unless otherwise specified, VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V
for the ISL706AEH/BEH/CEH TA = +25°C. This data is typical mean test data post radiation exposure at a rate of <10mrad(Si)/s. This data is intended
to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed
GROUNDED
200
180
BIASED
160
140
120
0
25
50
75
100
125
150
0
25
50
FIGURE 16. ISL705xEH VHYS vs LOW DOSE RATE RADIATION
125
150
40
1.8
35
GROUNDED
1.6
tMD (ns)
tWD (s)
100
FIGURE 17. ISL705xEH tRST vs LOW DOSE RATE RADIATION
2.0
1.4
GROUNDED
30
25
BIASED
1.2
BIASED
20
1.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
krad(Si)
krad(Si)
FIGURE 18. ISL705xEH tWD vs LOW DOSE RATE RADIATION
FIGURE 19. ISL705xEH tMD vs LOW DOSE RATE RADIATION
1.500
10
8
1.375
tRPFI (µs)
BIASED
VPFI (V)
75
krad(Si)
krad(Si)
1.250
GROUNDED
1.125
BIASED
6
4
GROUNDED
2
1.000
0
0
25
50
75
100
125
150
krad(Si)
FIGURE 20. ISL705xEH VPFI vs LOW DOSE RATE RADIATION
10
0
25
50
75
100
125
150
krad(Si)
FIGURE 21. ISL705xEH tRPFI vs LOW DOSE RATE RADIATION
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Post Radiation Characteristics Unless otherwise specified, VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V
for the ISL706AEH/BEH/CEH TA = +25°C. This data is typical mean test data post radiation exposure at a rate of <10mrad(Si)/s. This data is intended
to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed
40
400
35
375
BIASED
25
IDD (µA)
tFPFI (µs)
30
20
15
BIASED
350
GROUNDED
GROUNDED
10
325
5
0
300
0
25
50
75
100
125
150
0
25
50
FIGURE 22. ISL705xEH tFPFI vs LOW DOSE RATE RADIATION
125
150
60
50
3.15
BIASED
VHYS (mV)
VRST (V)
100
FIGURE 23. ISL706xEH IDD vs LOW DOSE RATE RADIATION
3.20
3.10
3.05
GROUNDED
3.00
BIASED
40
30
20
GROUNDED
10
2.95
0
0
25
50
75
100
125
0
150
25
50
krad(Si)
75
100
125
150
krad(Si)
FIGURE 24. ISL706xEH VRST vs LOW DOSE RATE RADIATION
FIGURE 25. ISL706xEH VHYS vs LOW DOSE RATE RADIATION
2.0
240
220
1.8
GROUNDED
200
tWD (s)
tRST (ms)
75
krad(Si)
krad(Si)
180
BIASED
160
BIASED
1.6
1.4
GROUNDED
1.2
140
120
1.0
0
25
50
75
100
125
150
krad(Si)
FIGURE 26. ISL706xEH tRST vs LOW DOSE RATE RADIATION
11
0
25
50
75
100
125
150
krad(Si)
FIGURE 27. ISL706xEH tWD vs LOW DOSE RATE RADIATION
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
40
0.62
35
0.61
GROUNDED
BIASED
VPFI (V)
tMD (ns)
Post Radiation Characteristics Unless otherwise specified, VDD = 4.75V to 5.5V for the ISL705AEH/BEH/CEH, VDD = 3.15V to 3.6V
for the ISL706AEH/BEH/CEH TA = +25°C. This data is typical mean test data post radiation exposure at a rate of <10mrad(Si)/s. This data is intended
to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed
30
25
BIASED
0.60
GROUNDED
0.59
20
0.58
0
25
50
75
100
125
150
0
25
50
75
100
125
150
krad(Si)
krad(Si)
FIGURE 28. ISL706xEH tMD vs LOW DOSE RATE RADIATION
FIGURE 29. ISL706xEH VPFI vs LOW DOSE RATE RADIATION
20
40
35
30
tFPFI (µs)
tRPFI (µs)
15
BIASED
10
GROUNDED
25
20
BIASED
15
10
5
GROUNDED
5
0
0
0
25
50
75
100
125
150
krad(Si)
FIGURE 30. ISL706xEH tRPFI vs LOW DOSE RATE RADIATION
12
0
25
50
75
100
125
150
krad(Si)
FIGURE 31. ISL706xEH tFPFI vs LOW DOSE RATE RADIATION
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Functional Overview
The ISL705xEH and ISL706xEH provide the functions needed for
monitoring critical voltages in high reliability applications, such as
microprocessor systems. Functions of the these supervisors include
power-on reset control, supply voltage supervisions, power-fail
detection, manual-reset assertion and a watch dog timer. The
integration of all these functions along with their high threshold
accuracy, low power consumption, and radiation tolerance make
these devices ideal for critical supply monitoring.
Reset Output
Reset control has long been a critical aspect of embedded
control design. Microprocessors require a reset signal during
power up to ensure that the system environment is stable before
initialization.
The reset signal provides several benefits:
• It prevents the system microprocessor from starting to operate
with insufficient voltage.
R1
VIN
PFI
R2
ISL705xEH/ISL706xEH
FIGURE 32. CUSTOM V TH WITH RESISTOR DIVIDER ON PFI
Manual Reset
The manual reset input (MR) allows designers to add manual
system reset capability via a push button switch (see Figure 33).
The MR input is an active low debounced input that asserts reset
if the MR pin is pulled low to less than VIL for at least 150ns.
After MR is released, the reset output remains asserted for tRST
and then released. MR is a TTL/CMOS logic compatible, so it can
be driven by external logic. By connecting WDO to MR, one can
force a watchdog time out to generate a reset pulse.
• It prevents the processor from operating prior to stabilization
of the oscillator.
20k
• It ensures that the monitored device is held out of operation
until internal registers are initialized.
MR
• It allows time for an FPGA to perform its self configuration
prior to initialization of the circuit.
On power-up, once VDD reaches 1.2V, RST is guaranteed logic
low. As VDD rises, RST stays low. When VDD rises above the reset
threshold (VRST), an internal timer releases RST after 200ms
(typ). RST pulses low whenever VDD degrades to below VRST (see
Figure 3). If a brownout condition occurs in the middle of a
previously initiated reset pulse, the pulse is lengthened 200ms
(typ).
On power-down, once VDD falls below the reset threshold, RST
stays low and is guaranteed to be low until VDD drops below 1.2V.
The ISL705BEH and ISL706BEH active-high RST output is simply
the complement of the RST output, and is guaranteed to be valid
with VDD down to 1.2V. The ISL705CEH and ISL706CEH
active-low open-drain reset output is functionally identical to RST.
Power Failure Monitor
Besides monitoring VDD for reset control, these devices have a
Power-Failure Monitor feature that supervises an additional
critical voltage on the Power-Fail Input (PFI) pin. For example, the
PFI pin could be used to provide an early power-fail warning,
overvoltage detection or monitor a power supply other than VDD.
PFO goes low whenever PFI is less than VPFI.
The threshold detector can be adjusted using an external resistor
divider network to provide custom voltage monitoring for
voltages greater than VPFI, according to Equation 1 (see
Figure 32).
R1 + R2
V IN = V PFI ⎛ ----------------------⎞
⎝ R2 ⎠
(EQ. 1)
13
PB
ISL705xEH/ISL706xEH
FIGURE 33. CONNECTING A MANUAL RESET PUSH-BUTTON
Watch Dog Timer
The watchdog time circuit checks for coherent program
execution by monitoring the WDI pin. If the processor does not
toggle the watchdog input within tWD (1.0s min), WDO will go
low. As long as reset is asserted or the WDI pin is tri-stated, the
watchdog timer will stay cleared and not count. As soon as reset
is released and WDI is driven high or low, the timer will start
counting. Pulses as short as 50ns can be detected on the
ISL705xEH, on ISL706xEH pulses as short as 100ns can be
detected.
Whenever there is a low-voltage VDD condition, WDO goes low.
Unlike the reset outputs, however, WDO goes high as soon as
VDD rises above its voltage trip point (see Figure 4). With WDI
open or connected to a tri-stated high impedance input, the
Watchdog Timer is disabled and only pulls low when VDD < VRST.
Applications Information
Negative Voltage Sensing
This family of devices can be used to sense and monitor the
presence of both a positive and negative rail. VDD is used to
monitor the positive supply while PFI monitors the negative rail.
PFO is high when the negative rail degrades below a VTRIP value
and remains low when the negative rail is above the Vtrip value.
As the differential voltage across the R1, R2 divider is increased,
the resistor values must be chosen such that the PFI node is
<1.25V when the -V supply is satisfactory and the positive supply
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
is at its maximum specified value. This allows the positive supply
to fluctuate within its acceptable range without signaling a reset
when configured as shown in Figure 34.
R1 ( V PFI – V TRIP )
R2 = --------------------------------------------V DD – V PFI
VDD
(EQ. 2)
RST
In Figure 34, the ISL705AEH is monitoring +5V through VDD and
-5V through PFI. In this example, the trip point (V TRIP) for the
negative supply rail is set for -4.5V. Equation 2 can be used to
select the appropriate resistor values. R1 is selected arbitrarily as
100kΩ, VDD = 5V, VPFI = 1.25V, and V TRIP = (-4.5V). By plugging
the values into Equation 2 (as shown in Equation 3) it can be
seen a resistor of 153.3kΩ is needed. The closest 1% resistor
value is 154kΩ.
100k ( 1.25 – ( – 4.5 ) )
R2 = ------------------------------------------------------ = 153.3kΩ
5 – 1.25
(EQ. 3)
+5V
100k
VDD
R1
MR
100k
100kΩ
ISL705AEH, ISL706AEH
FIGURE 35. RST VALID TO GROUND CIRCUIT
Assuring a Valid RST Output
On the ISL705BEH and ISL706BEH, when VDD falls below 1.2V, the
RST output can no longer source enough current to track VDD. As a
result, this pin can drift to undetermined voltages if left undriven. By
adding a pull-up resistor to the RST pin as shown in Figure 36, RST
will track VDD below 1.2V. The resistor value (R1) is not critical
however, it should be large enough not to exceed the sink capability
of RST pin at 1.2V. A 300kΩ resistor would suffice, assuming there
is no load on the RST pin during that time.
2N3904
PFO
PFI
VDD
R1
R2
300kΩ
RST
RST
-5V
ISL705AEH
FIGURE 34. ±5V MONITORING
ISL705BEH, ISL706BEH
FIGURE 36. RST VALID TO GROUND CIRCUIT
Figure 4 also has a general purpose NPN transistor in which the
base is connected to the PFO pin through a 100kΩ resistor. The
emitter is tied to ground and the collector is tied to MR signal.
This configuration allows the negative voltage sense circuit to
initiate a reset if it is not within its regulation window. A pull-up
on the MR ensures no false reset triggering when the negative
voltage is within its regulation window.
Assuring a Valid RST Output
When VDD falls below 1.2V, the RST output can no longer sink
current and is essentially an open circuit. As a result, this pin can
drift to undetermined voltages if left undriven. By adding a pull-down
resistor to the RST pin as shown in Figure 35, any stray charge or
leakage currents will be drained to ground and keep RST low when
VDD falls below 1.2V. The resistor value (R1) is not critical however, it
should be large enough not to load RST and small enough to pull
RST to ground. A 100kΩ resistor would suffice, assuming there is no
load on the RST pin during that time.
Selecting Pull-Up Resistor Values
The ISL705CEH and ISL706CEH have open drain active low reset
outputs (RST_OD). A pull-up resistor is needed to ensure RST_OD
is high when VDD is in a valid state (Figure 37). The resistor value
must be chosen in order not to exceed the sink capability of the
RST_OD pin. The ISL705AEH has a sink capability of 3.2mA and
the ISL706CEH has a sink capability of 1.2mA. Equation 4 may
be used to select resistor RPULL based on the pull-up voltage
VPULL. It is also important that the pull-up voltage does not
exceed VDD.
VPULL
VDD
RPULL
RST_OD
ISL706CEH, ISL705CEH
FIGURE 37. RST_OD PULL-UP CONNECTION
14
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
V PULL
R PULL = ---------------I SINK
(EQ. 4)
Adding Hysteresis to the PFI Comparator
The PFI comparator has no built in hysteresis, however the
designer may add hysteresis by connecting a resistor from the
PFO pin to the PFI pin, essentially adding positive feedback to the
comparator (see Figure 38).
The rising voltage, VTR is calculated as 2.98V and the falling
voltage VTF is calculated as 2.88V so 100mV hysteresis is
achieved.
An additional item to consider is that the output voltage is equal
to VDD, however according to the “Electrical Specifications” on
page 6, the output of the PFI comparator is guaranteed to be at
least (VDD-1.5) volts. When you take this worst case into account,
the hysteresis can be as low at 70mV.
Special Application Considerations
Using good decoupling practices will prevent transients (i.e., due
to switching noises and short duration droops in the supply
voltage) from causing unwanted resets and reduce the power-fail
circuit’s sensitivity to high-frequency noise on the line being
monitored.
VDD
RST
R1
PFO
PFI
R2
When the WDI input is left unconnected, it is recommended to
place a 10µF capacitor to ground to reduce single event
transients from arising in the WDO pin.
ISL705AEH
R3
FIGURE 38. POSITIVE FEEDBACK FOR HYSTERISIS
The following procedure allows the system designer to calculate
the components based on the requirements and on given data,
such as supply rail voltages, hysteresis band voltage (VHB), and
reference voltage (VPFI).
As described in the “Electrical Specifications” Table on page 7,
there is a delay on the PFO pin whenever PFI crosses the
threshold. This delay is due to internal filters on the PFI
comparator circuitry which were added to mitigate single event
transients. If the PFI input transitions below or above the
threshold and the duration of the transition is less than the delay,
the PFO pin will not change states.
The comparator only has two states of operation. When it is low,
the current through R3 is IR3 = VPFI/R3. When the output is high,
IR3 = (VDD - VPFI)/R3. The feedback current needs to be very
small so it does not induce oscillations; 200nA is a good starting
point. Now two values of R3 can be calculated with VDD = 5V and
VPFI = 1.25V; R3 = 6.25MΩ or 11.25MΩ, select the lowest value
of the two.
With R3 selected as 6.2MΩ (closest standard 1% resistor), R1
can be calculated as:
VHB
R1 = R3 ⎛ -----------⎞ = 124kΩ
⎝V ⎠
DD
(EQ. 5)
with VHB selected at 100mV. The closest standard value for R1 is
124kΩ. Then next step is select the rising trip voltage (VTR) such
that:
VHB
VTR > V PFI ⎛ 1 + -----------⎞
⎝
V ⎠
(EQ. 6)
DD
The rising threshold voltage is selected at 3.0V and R2 is
calculated by Equation 7.
1
VTR
1
R2 = 1 ⁄ ⎛ ------------------------------⎞ – ⎛ -------⎞ – ⎛ -------⎞
⎝ (V
⎠ ⎝ R1⎠ ⎝ R3⎠
PFI × R1 )
(EQ. 7)
Plugging in all the variables R2 in this example is 90.9kΩ again
this is choosing the closest 1% resistor. The final step is verify the
trip voltages.
1
1
1
VTR = ( V PFI ) × R1 ⎛ -------⎞ + ⎛ -------⎞ + ⎛ -------⎞
⎝ R1⎠ ⎝ R2⎠ ⎝ R3⎠
(EQ. 8)
R1 × VDD
VTF = VTR – ⎛ --------------------------⎞
⎝
⎠
R3
(EQ. 9)
15
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Package Characteristics
Weight of Packaged Device
0.31 Grams typical
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Lid Potential: Unbiased
Case Isolation to Any Lead: 20 x 109 Ω (min)
PROCESS
0.6µM BiCMOS Junction Isolated
ASSEMBLY RELATED INFORMATION
Die Characteristics
Substrate Potential
Die Dimensions
2030µm x 2030µm (79.9 mils x 79.9 mils)
Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil)
Unbiased
ADDITIONAL INFORMATION
Worst Case Current Density
Interface Materials
< 2 x 105 A/cm2
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
Transistor Count
1400
Metallization Mask Layout
MR
WDO
VDD
RST, RST, RST_OD
GND
WDI
PFI
16
PFO
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
TABLE 1. DIE LAYOUT X-Y COORDINATES
PAD NAME
PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
MR
1
0
0
110
110
1
VDD
2
-266.1
-435.35
110
110
1
GND
3
-266.1
-1184.75
110
110
1
PFI
4
-86.1
-1578
110
110
1
PFO
5
818.85
-1578
110
110
1
WDI
6
1321.9
-1233.5
110
110
1
RST, RST, RST_OD
7
1321.9
-534.05
110
110
1
WDO
8
1297
0
110
110
1
NOTE:
8. Origin of coordinates is the centroid of pad 1.
17
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
March 30, 2012
FN8262.0
CHANGE
Initial release
Products
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18
FN8262.0
March 30, 2012
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 12/10
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
0.005 (0.13)
MIN
4
PIN NO. 1
ID AREA
0.022 (0.56)
0.015 (0.38)
0.115 (2.92)
0.070 (1.18)
0.265 (6.73)
0.245 (6.22)
TOP VIEW
0.045 (1.14)
0.026 (0.66)
0.09 (0.23)
0.04 (0.10)
6
0.265 (6.75)
0.245 (6.22)
-D-
-H-
-C0.180 (4.57)
0.170 (4.32)
SEATING AND
BASE PLANE
0.370 (9.40)
0.250 (6.35)
0.03 (0.76) MIN
SIDE VIEW
0.007 (0.18)
0.004 (0.10)
NOTES:
LEAD FINISH
BASE
METAL
0.009 (0.23)
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
0.004 (0.10)
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
4. Measure dimension at all four corners.
3
SECTION A-A
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
19
FN8262.0
March 30, 2012
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