DATASHEET

DATASHEET
Radiation Hardened, High Performance Industry
Standard Single-Ended Current Mode PWM Controller
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
The ISL78840ASEH, ISL78841ASEH, ISL78843ASEH,
Features
ISL78845ASEH, ISL78840ASRH, ISL78841ASRH,
ISL78843ASRH, ISL78845ASRH are a high performance,
radiation hardened drop-in replacement for the popular 28C4x
and 18C4x PWM controllers suitable for a wide range of power
conversion applications including boost, flyback and isolated
output configurations. Its fast signal propagation and output
switching characteristics make this an ideal product for
existing and new designs.
Features include up to 13.2V operation, low operating current,
90µA typical start-up current, adjustable operating frequency
to 1MHz and high peak current drive capability with 50ns rise
and fall times.
Applications
• Electrically screened to DLA SMD #5962-07249
• QML Qualified Per MIL-PRF-38535 Requirements
• 1A MOSFET Gate Driver
• 90µA typical start-up current, 125µA Maximum
• 35ns propagation delay current sense to output
• Fast transient response with peak current mode control
• 9V to 13.2V operation
• Adjustable switching frequency to 1MHz
• 50ns rise and fall times with 1nF output load
• Trimmed timing capacitor discharge current for accurate
deadtime/maximum duty cycle control
• Current mode switching power supplies
• 1.5MHz bandwidth error amplifier
• Isolated buck and flyback regulators
• Boost regulators
• Tight tolerance voltage reference over line, load and
temperature
• Direction and speed control in motors
• ±3% current limit threshold
• Control of high current FET drivers
• Pb-free available (RoHS compliant)
Related Literature
• Radiation environment:
- High dose rate (50 - 300rad(Si)/s). . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Product capability established by initial characterization. The
“EH” version is acceptance tested on a wafer by wafer basis to
50krad(Si) at low dose rate. (Applies for ISL7884xASEH only)
• TR005, “Single Event Effects (SEE) Test Report for
ISL78843ASRH and ISL78845ASRH High Performance
Single-ended Current Mode PWM Controllers”
• TR006, “Neutron Testing of the ISL78845ASEH Pulse Width
Modulator”
Pin Configurations
ISL78840ASEH, ISL78841ASEH,
ISL78843ASEH, ISL78845ASEH ISL78840ASRH,
ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
(8 LD SBDIP)
TOP VIEW
ISL78840ASEH, ISL78841ASEH,
ISL78843ASEH, ISL78845ASEH ISL78840ASRH,
ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
(8 LD FLATPACK)
TOP VIEW
COMP
1
8
VREF
FB
2
7
VDD
CS
3
6
OUT
RTCT
4
5
GND
April 8, 2016
FN7952.1
1
COMP
1
8
VREF
FB
2
7
VDD
CS
3
6
OUT
RTCT
4
5
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Ordering Information
ORDERING NUMBER
(Note 1)
PART NUMBER
(Note 2)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
5962R0724905VPC
ISL78840ASEHVD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724906VPC
ISL78841ASEHVD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724907VPC
ISL78843ASEHVD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724908VPC
ISL78845ASEHVD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724905VXC
ISL78840ASEHVF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724906VXC
ISL78841ASEHVF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724907VXC
ISL78843ASEHVF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724908VXC
ISL78845ASEHVF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724905V9A
ISL78840ASEHVX
-55 to +125
Die
5962R0724906V9A
ISL78841ASEHVX
-55 to +125
Die
5962R0724907V9A
ISL78843ASEHVX
-55 to +125
Die
5962R0724908V9A
ISL78845ASEHVX
-55 to +125
Die
ISL78840ASRHVX/SAMPLE
ISL78840ASRHVX/SAMPLE
-55 to +125
Die
ISL78840ASRHF/PROTO
ISL78840ASRHF/PROTO
-55 to +125
8 Ld Flatpack
K8.A
5962R0724901QXC
ISL78840ASRHQF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724901VXC
ISL78840ASRHVF
-55 to +125
8 Ld Flatpack
K8.A
ISL78840ASRHD/PROTO
ISL78840ASRHD/PROTO
-55 to +125
8 Ld SBDIP
D8.3
5962R0724901QPC
ISL78840ASRHQD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724901VPC
ISL78840ASRHVD
-55 to +125
8 Ld SBDIP
D8.3
ISL78841ASRHVX/SAMPLE
ISL78841ASRHVX/SAMPLE
-55 to +125
Die
ISL78841ASRHF/PROTO
ISL78841ASRHF/PROTO
-55 to +125
8 Ld Flatpack
K8.A
5962R0724902QXC
ISL78841ASRHQF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724902VXC
ISL78841ASRHVF)
-55 to +125
8 Ld Flatpack
K8.A
ISL78841ASRHD/PROTO
ISL78841ASRHD/PROTO
-55 to +125
8 Ld SBDIP
D8.3
5962R0724902QPC
ISL78841ASRHQD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724902VPC
ISL78841ASRHVD
-55 to +125
8 Ld SBDIP
D8.3
ISL78843ASRHVX/SAMPLE
ISL78843ASRHVX/SAMPLE
-55 to +125
Die
ISL78843ASRHF/PROTO
ISL78843ASRHF/PROTO
-55 to +125
8 Ld Flatpack
K8.A
5962R0724903QXC
ISL78843ASRHQF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724903VXC
ISL78843ASRHVF
-55 to +125
8 Ld Flatpack
K8.A
ISL78843ASRHD/PROTO
ISL78843ASRHD/PROTO
-55 to +125
8 Ld SBDIP
D8.3
5962R0724903QPC
ISL78843ASRHQD
-55 to +125
8 Ld SBDIP
D8.3
5962R0724903VPC
ISL78843ASRHVD
-55 to +125
8 Ld SBDIP
D8.3
ISL78845ASRHVX/SAMPLE
ISL78845ASRHVX/SAMPLE
-55 to +125
Die
ISL78845ASRHF/PROTO
ISL78845ASRHF/PROTO
-55 to +125
8 Ld Flatpack
K8.A
5962R0724904QXC
ISL78845ASRHQF
-55 to +125
8 Ld Flatpack
K8.A
5962R0724904VXC
ISL78845ASRHVF
-55 to +125
8 Ld Flatpack
K8.A
ISL78845ASRHD/PROTO
ISL78845ASRHD/PROTO
-55 to +125
8 Ld SBDIP
D8.3
5962R0724904QPC
ISL78845ASRHQD
-55 to +125
8 Ld SBDIP
D8.3
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ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Ordering Information (Continued)
ORDERING NUMBER
(Note 1)
PART NUMBER
(Note 2)
5962R0724904VPC
TEMP. RANGE
(°C)
ISL78845ASRHVD
PACKAGE
(RoHS Compliant)
-55 to +125
8 Ld SBDIP
PKG. DWG. #
D8.3
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
RISING UVLO
(V)
MAXIMUM DUTY CYCLE
(%)
ISL78840ASxH
7.0
100
ISL78841ASxH
7.0
50
ISL78843ASxH
8.4
100
ISL78845ASxH
8.4
50
PART NUMBER
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
RTCT
4
This is the oscillator timing control pin. The operational frequency and maximum
duty cycle are set by connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth
waveform with a programmable frequency range up to 2.0MHz. The charge time, tC,
the discharge time, tD, the RTCT oscillator frequency, f and the maximum duty cycle,
DMAX, can be approximated from Equations 1 through 4:
t C  0.533  RT  CT
(EQ. 1)
0.008  RT – 3.83
t D  – RT  CT  In  --------------------------------------------- 
 0.008  RT – 1.71 
(EQ. 2)
f = 1  tC + tD
(EQ. 3)
D = tC  f
(EQ. 4)
The formulas have increased error at higher frequencies due to propagation delays.
Figure 7 may be used as a guideline in selecting the capacitor and resistor values
required for a given oscillator frequency for the ISL7884xASxH. The switching
frequency for the ISL78841ASxH and ISL78845ASxH will be half the RTCT oscillator
frequency.
COMP
1
COMP is the output of the error amplifier and the input of the PWM comparator. The
control loop frequency compensation network is connected between the COMP and
FB pins.
FB
2
The output voltage feedback is connected to the inverting input of the error amplifier
through this pin. The noninverting input of the error amplifier is internally tied to a
reference voltage.
CS
3
This is the current sense input to the PWM comparator. The range of the input signal
is nominally 0V to 1.0V and has an internal offset of 100mV.
GND
5
GND is the power and small signal reference ground for all functions.
OUT
6
This is the drive output to the power switching device. It is a high current output
capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE
output is actively held low when VDD is below the UVLO threshold.
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ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Pin Descriptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
VDD
7
VDD is the power connection for the device. The total supply current will depend on
the load applied to OUT. Total IDD current is the sum of the operating current and the
average output current. Knowing the operating frequency, f and the MOSFET gate
charge, Qg, the average output current can be calculated from Equation 5:
I OUT = Qg  f
(EQ. 5)
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to
the VDD and GND pins as possible.
VREF
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8
4
The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and
operating temperature. The recommended bypass to GND cap is in the range 0.1µF
to 0.22µF. A typical value of 0.15µF can be used.
FN7952.1
April 8, 2016
VDD
+
-
VREF
VREF
5V
START/STOP
UV COMPARATOR
ENABLE
VDD OK
VREF FAULT
+-
+
2.5V
A
4.65V
4.80V
+-
5
VREF
UV COMPARATOR
GND
A = 0.5
PWM
COMPARATOR
+-
CS
100mV
2R
+
-
FB
VF TOTAL = 1.15V
ERROR
AMPLIFIER
+
-
1.1V
CLAMP
ONLY
ISL78841A,
ISL78845A
R
Q
T
COMP
Q
OUT
S Q
36k
R Q
RESET
DOMINANT
VREF
100k
2.9V
1.0V
ON
150k
OSCILLATOR
COMPARATOR
<10ns
+
RTCT
CLOCK
8.4mA
ON
FN7952.1
April 8, 2016
FIGURE 1. BLOCK DIAGRAM
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
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Functional Block Diagram
CR5
+3.3V
C21
T1
R21
VIN+
+ C15
+ C16
+1.8V
C4
R3
CR4
6
C2
C17
CR2
C5
C22
+
+
C20
C19
RETURN
CR6
R1
36V TO 75V
R16
C6
C14
Q1
R4
R18
R19
U2
C3
C1
R17
R28
R22
C13
VIN-
R15
U3
R27
R20
U4
R26
COMP
VREF
CS
V DD
FB
OUT
GND
RTCT
ISL7884xASxH
R6
R10
CR1
Q3
VR1
C12
C11
C8
FN7952.1
April 8, 2016
FIGURE 2. TYPICAL APPLICATION - 48V INPUT DUAL OUTPUT FLYBACK
R13
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
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Typical Application - 48V Input Dual Output Flyback
R8
C10
CR1
L1
VIN+
+VOUT
+
C2
C3
7
R4
Q1
RETURN
R5
R9
C9
C1
R1
R2
U1
FB
CS
C4
RTCT
ISL7884xASxH
COMP
R7
VREF
VIN+
VDD
OUT
GND
R3
C7
VIN-
FN7952.1
April 8, 2016
FIGURE 3. TYPICAL APPLICATION - BOOST CONVERTER
C5
C6
C8
R6
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
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Typical Application - Boost Converter
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD Without Beam . . . . . . . . . . . . . (GND -0.3V) to +30.0V
Supply Voltage VDD Under Beam . . . . . . . . . . . . . . . (GND -0.3V) to +14.7V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to VDD + 0.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld Flatpack Package (Notes 3, 4)
140
15
98
15
8 Ld SBDIP Package (Notes 3, 4)
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage (Typical Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 13.2V
Radiation Information
Maximum Total Dose
Dose Rate = 50 - 100radSi/s . . . . . . . . . . . . . . . . . . . . . . . . 100krads (Si)
Dose Rate = 0.01rad(Si)/s (Note 6) . . . . . . . . . . . . . . . . . . . 100krad (Si)
SEB (No Burnout) (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2
SEL (No latch-up) (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 43Mev/mg/cm2
SET (Regulated VOUT within ±3%) (Note 7) . . . . . . . . . . . . 40Mev/mg/cm2
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the "case temp" location is the center of the ceramic on the package underside.
5. All voltages are with respect to GND.
6. Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer by wafer basis to 50krad(Si) at low dose
rate. (Applied only to ISL7884xASEH.)
7. SEE tests performed with VREF bypass capacitor of 0.22µF and fSW = 200kHz. SEB/L tests done on a standalone open loop configuration. SET tests
done in a closed loop configuration. For LET ≤ 43MeV/mg•cm2. The SEL observed requiring a power cycle to recover operation occurred at
≤ 43MeV/mg•cm2 < LET ≤ 80MeV/mg•cm2. For more information see: ISL7884xASRH SEE Test Report.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 5 and Typical
Application on page 6 schematics. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA = +25°C. Boldface limits apply across
the operating temperature range, -55 to +125°C.
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
ISL78840A, ISL78841A
6.5
7.0
7.5
V
ISL78843A, ISL78845A
8.0
8.4
9.0
V
ISL78840A, ISL78841A
6.1
6.6
6.9
V
ISL78843A, ISL78845A
7.3
7.6
8.0
V
ISL78840A, ISL78841A
-
0.4
-
V
ISL78843A, ISL78845A
-
0.8
-
V
VDD < START Threshold
-
90
125
µA
VDD < START Threshold, 100krad
-
300
500
µA
Operating Current, IDD
(Note 8)
-
2.9
4.0
mA
Operating Supply Current, ID
Includes 1nF GATE loading
-
4.75
5.50
mA
4.925
5.000
5.050
V
-
5
-
mV
Current Limit, Sourcing
-20
-
-
mA
Current Limit, Sinking
5
-
-
mA
-1.0
-
1.0
µA
PARAMETER
TEST CONDITIONS
UNDERVOLTAGE LOCKOUT
START Threshold
STOP Threshold
Hysteresis
Start-Up Current, IDD
REFERENCE VOLTAGE
Overall Accuracy
Over line (VDD = 9V to 13.2V), load of
1mA and 10mA, temperature
Long Term Stability
TA = +125°C, 1000 hours (Note 9)
CURRENT SENSE
Input Bias Current
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VCS = 1V
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FN7952.1
April 8, 2016
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 5 and Typical
Application on page 6 schematics. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA = +25°C. Boldface limits apply across
the operating temperature range, -55 to +125°C. (Continued)
PARAMETER
TEST CONDITIONS
Input Signal, Maximum
Gain, ACS = VCOMP/VCS
0 < VCS < 910mV, VFB = 0V
CS to OUT Delay
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
0.97
1.00
1.03
V
2.75
2.82
3.15
V/V
-
35
55
ns
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 9)
-
90
-
dB
Unity Gain Bandwidth
(Note 9)
-
1.5
-
MHz
Reference Voltage, VREF
VFB = VCOMP
2.475
2.500
2.530
V
FB Input Bias Current, FBIIB
VFB = 0V
-1.0
-0.2
1.0
µA
COMP Sink Current
VCOMP = 1.5V, VFB = 2.7V
1.0
-
-
mA
COMP Source Current
VCOMP = 1.5V, VFB = 2.3V
-0.4
-
-
mA
COMP VOH
VFB = 2.3V
4.80
-
VREF
V
COMP VOL
VFB = 2.7V
0.4
-
1.0
V
PSRR
Frequency = 120Hz, VDD = 9V to 13.2V
(Note 9)
-
80
-
dB
OSCILLATOR
Frequency Accuracy
Initial, TA = +25°C
48
51
53
kHz
Frequency Variation with VDD
TA= +25°C, (f13.2V - f9V)/f12V
-
0.2
1.0
%
Temperature Stability
(Note 9)
-
5
-
%
Amplitude, Peak-to-Peak
Static Test
-
1.75
-
V
RTCT Discharge Voltage (Valley Voltage)
Static Test
-
1.0
-
V
Discharge Current
RTCT = 2.0V
6.5
7.8
8.5
mA
OUTPUT
Gate VOH
VDD to OUT, IOUT = -100mA
-
1.0
2.0
V
Gate VOL
OUT to GND, IOUT = 100mA
-
1.0
2.0
V
Peak Output Current
COUT = 1nF (Note 9)
-
1.0
-
A
Rise Time
COUT = 1nF
-
35
60
ns
Fall Time
COUT = 1nF
-
20
40
ns
OUTPUT OFF State Leakage
VDD = 5V
-
-
50
µA
96.0
-
%
48.0
-
%
-
0
%
PWM
Maximum Duty Cycle
(ISL78840A, ISL78843A)
COMP = VREF
94.0
Maximum Duty Cycle
(ISL78841A, ISL78845A)
COMP = VREF
47.0
Minimum Duty Cycle
COMP = GND
-
NOTES:
8. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
9. Limits established by characterization and are not production tested.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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FN7952.1
April 8, 2016
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Typical Performance Curves
1.001
1.000
NORMALIZED VREF
NORMALIZED FREQUENCY
1.01
1.00
0.99
0.98
-60 -40 -20
0
20
40
60
80
0.999
0.998
0.997
0.996
0.995
-60
100 120 140
-40
-20
TEMPERATURE (°C)
103
FREQUENCY (kHz)
1.001
NORMALIZED EA REFERENCE
100 120 140
FIGURE 5. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 4. FREQUENCY vs TEMPERATURE
1.000
0.998
0.997
0.996
-60
0
20 40 60 80
TEMPERATURE (°C)
-20
0
20
40
60
80
100 120 140
220pF
330pF
470pF
1.0nF
10
1
-40
100pF
100
2.2nF
3.3nF
4.7nF
6.8nF
1
10
RT (kΩ)
TEMPERATURE (°C)
FIGURE 6. EA REFERENCE vs TEMPERATURE
100
FIGURE 7. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
Functional Description
Soft-Start Operation
Features
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
The ISL7884xASxH current mode PWM makes an ideal choice
for low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts, it is
the obvious choice for new designs or existing designs, which
require updating.
VREF
The ISL7884xASxH has a sawtooth oscillator with a
programmable frequency range to 2MHz, which can be
programmed with a resistor from VREF and a capacitor to GND on
the RTCT pin. (Please refer to Figure 7 for the resistor and
capacitance required for a given frequency.)
R1
COMP
Q1
C1
GND
ISL7884xAxEH
D1
Oscillator
FIGURE 8. SOFT-START
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ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
The COMP pin is clamped to the voltage on capacitor C1 plus a
base-emitter junction by transistor Q1. C1 is charged from VREF
through resistor R1 and the base current of Q1. At power-up C1 is
fully discharged, COMP is at ~0.7V and the duty cycle is zero. As
C1 charges, the voltage on COMP increases and the duty cycle
increases in proportion to the voltage on C1. When COMP
reaches the steady state operating point, the control loop takes
over and soft-start is complete. C1 continues to charge up to
VREF and no longer affects COMP. During power-down, diode D1
quickly discharges C1 so that the soft-start circuit is properly
initialized prior to the next power-on sequence.
Gate Drive
The ISL7884xAxEH is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole output of
the IC (OUT pin) and the gate of the MOSFET. This small series
resistor also damps any oscillations caused by the resonant tank
of the parasitic inductances in the traces of the board and the
FETs input capacitance. TID environment of >50krads requires
the use of a bleeder resistor of 10k from the OUT pin to GND.
Slope Compensation
For applications where the maximum duty cycle is less than 50%,
slope compensation may be used to improve noise immunity,
particularly at lighter loads. The amount of slope compensation
required for noise immunity is determined empirically, but is
generally about 10% of the full scale current feedback signal. For
applications where the duty cycle is greater than 50%, slope
compensation is required to prevent instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by subtracting
the external ramp from the voltage feedback error signal. Adding
the external ramp to the current feedback signal is the more
popular method.
From the small signal current-mode model [1] it can be shown
that the naturally-sampled modulator gain, Fm, without slope
compensation is calculated in Equation 6:
1
Fm = -----------------Sntsw
(EQ. 6)
Where Sn is the slope of the sawtooth signal and tsw is the
duration of the half-cycle. When an external ramp is added, the
modulator gain becomes Equation 7:
1
1
Fm = ------------------------------------- = ------------------------- Sn + Se tsw
m c Sntsw
(EQ. 8)
The criteria for determining the correct amount of external ramp
can be determined by appropriately setting the damping factor of
the double-pole located at the switching frequency. The
double-pole will be critically damped if the Q-factor is set to 1,
over-damped for Q < 1 and under-damped for Q > 1. An
under-damped condition may result in current loop instability.
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11
(EQ. 9)
Where D is the percent of on-time during a switching cycle.
Setting Q = 1 and solving for Se yields Equation 10:
1
1
S e = S n   --- + 0.5 ------------- – 1
1–D
 

(EQ. 10)
Since Sn and Se are the on-time slopes of the current ramp and
the external ramp, respectively, they can be multiplied by tON to
obtain the voltage change that occurs during tON.
1
1
V e = V n   --- + 0.5 ------------- – 1
1–D
 

(EQ. 11)
Where Vn is the change in the current feedback signal (I) during
the on-time and Ve is the voltage that must be added by the
external ramp.
For a flyback converter, Vn can be solved in terms of input
voltage, current transducer components and primary inductance,
yielding Equation 12:
D  T SW  V IN  R CS 1
1
V e = ----------------------------------------------------   --- + 0.5 ------------- – 1
1–D
 

Lp
V
(EQ. 12)
Where RCS is the current sense resistor, Tsw is the switching
period, Lp is the primary inductance, VIN is the minimum input
voltage and D is the maximum duty cycle.
The current sense signal at the end of the ON time for CCM
operation is Equation 13:
 1 – D   VO  T 
N S  R CS 
sw
V CS = ------------------------  I O + ----------------------------------------------
2L s
NP


V
(EQ. 13)
Where VCS is the voltage across the current sense resistor, Ls is
the secondary winding inductance and IO is the output current at
current limit. Equation 13 assumes the voltage drop across the
output rectifier is negligible.
Since the peak current limit threshold is 1.00V, the total current
feedback signal plus the external ramp voltage must sum to this
value when the output load is at the current limit threshold as
shown in Equation 14:
V e + V CS = 1V
(EQ. 14)
(EQ. 7)
Where Se is slope of the external ramp and becomes Equation 8:
Se
m c = 1 + ------Sn
1
Q = ------------------------------------------------  m c  1 – D  – 0.5 
Substituting Equations 12 and 13 into Equation 14 and solving
for RCS yields Equation 15:
1
R CS = --------------------------------------------------------------------------------------------------------------------------------------------------------1
- + 0.5  N
 1 – D   V O  T sw
D  T sw  V IN  -

---------------------------------   ------------------ – 1 + ------s-   I O + ---------------------------------------------


Np 
Lp
2L s
1–D



(EQ. 15)
FN7952.1
April 8, 2016
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Adding slope compensation is accomplished in the
ISL7884xASxH using an external buffer transistor and the RTCT
signal. A typical application sums the buffered RTCT signal with
the current sense feedback and applies the result to the CS pin
as shown in Figure 9.
RCS = 295mΩ
Determine the amount of voltage, Ve, that must be added to the
current feedback signal using Equation 12.
Ve = 92.4mV
Using Equation 17, solve for the summing resistor, R9, from CT to
CS.
R9 = 2.67kΩ
VREF
CS
R6
ISL78843ASxH
R9
Determine the new value of RCS (R’CS) using Equation 18.
R’CS = 350mΩ
Additional slope compensation may be considered for design
margin. The above discussion determines the minimum external
ramp that is required. The buffer transistor used to create the
external ramp from RTCT should have a sufficiently high gain
(>200) so as to minimize the required base current. Whatever
base current is required reduces the charging current into RTCT
and will reduce the oscillator frequency.
RTCT
C4
FIGURE 9. SLOPE COMPENSATION
Fault Conditions
Assuming the designer has selected values for the RC filter (R6
and C4) placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
2.05D  R 6
V e = ---------------------------R6 + R9
(EQ. 16)
V
The factor of 2.05 in Equation 16 arises from the peak amplitude
of the sawtooth waveform on RTCT minus a base-emitter junction
drop. That voltage multiplied by the maximum duty cycle is the
voltage source for the slope compensation. Rearranging to solve
for R9 yields Equation 17:
 2.05D – V e   R 6
R 9 = ---------------------------------------------Ve

(EQ. 17)
The value of RCS determined in Equation 15 must be rescaled so
that the current sense signal presented at the CS pin is that
predicted by Equation 13. The divider created by R6 and R9
makes this necessary.
R6 + R9
R CS = ---------------------  R CS
R9
A Fault condition occurs if VREF falls below 4.65V. When a Fault
is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault
condition clears and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. A unique section of the
ground plane must be designated for high di/dt currents
associated with the output stage. VDD should be bypassed
directly to GND with good high frequency capacitors.
References
[1] Ridley, R., “A New Continuous-Time Model for Current Mode
Control”, IEEE Transactions on Power Electronics, Vol. 6,
No. 2, April 1991.
(EQ. 18)
Example:
VIN = 12V
VO = 48V
Ls = 800µH
Ns/Np = 10
Lp = 8.0µH
IO = 200mA
Switching Frequency, fsw = 200kHz
Duty Cycle, D = 28.6%
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 15.
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FN7952.1
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ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Package Characteristics
Weight of Packaged Device
8 Ld Mini DIP: 0.7004 Grams
8 Ld Flatpack: 0.3605 Grams
Die Characteristics
Die Dimensions
2030µm x 2030µm (80 mils x 80 mils)
Thickness: 482µm ±25.4µm (19.0 mils ±1 mil)
SUBSTRATE
Silicon
BACKSIDE FINISH
Silicon
PROCESS
0.6µM BiCMOS Junction Isolated
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased
Interface Materials
ADDITIONAL INFORMATION
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ±0.03µm to 1.2µm ±0.12µm
Worst Case Current Density
< 2 x 105 A/cm2
Transistor Count
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
1278
Die Map
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ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
April 8, 2016
FN7952.1 Added part numbers “ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH” throughout the datasheet.
Added Related Literature section on page 1.
Moved Table 1 from page 1 to page 3.
Moved and updated the “Pin Descriptions” on page 3.
Updated the “Radiation Information” on page 8: Updated SEL (No latch-up) from”80Mev/mg/cm2” to
“43Mev/mg/cm2”.
Moved Note 7 (old Note 9) from page 9 to the end of the Abs max table.
May 4, 2012
FN7952.0 Initial Release.
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ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 4, 12/14
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
0.005 (0.13)
MIN
4
PIN NO. 1
ID AREA
0.022 (0.56)
0.015 (0.38)
0.110 (2.79)
0.087 (2.21)
0.265 (6.73)
0.245 (6.22)
TOP VIEW
0.036 (0.92)
0.026 (0.66)
0.009 (0.23)
0.004 (0.10)
6
0.265 (6.75)
0.245 (6.22)
-D-
-H-
-C-
0.180 (4.57)
0.170 (4.32)
SEATING AND
BASE PLANE
0.370 (9.40)
0.325 (8.26)
0.03 (0.76) MIN
SIDE VIEW
0.007 (0.18)
0.004 (0.10)
NOTES:
LEAD FINISH
0.009 (0.23)
BASE
METAL
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
2. If a pin one identification mark is used in addition to or instead of a tab,
the limits of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
3
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
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Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
LEAD FINISH
D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
SECTION A-A
D S
D
BASE
PLANE
Q
S2
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
eA/2
c
aaa M C A - B S D S
ccc M C A - B S D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2 and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the base
plane.
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
-
E
0.220
0.310
5.59
e
0.100 BSC
7.87
-
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
a
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
N
8
0.038
8
2
8
Rev. 0 4/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
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