8320ZxxA V

GS8320Z18/36AGT-xxxV
333 MHz–150 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
36Mb Pipelined and Flow Through
Synchronous NBT SRAMs
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8320Z18/36AGT-xxxV is a 36Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36AGT-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36AGT-xxxV is implemented with GSI's
high performance CMOS technology and is available in a
JEDEC-standard 100-pin TQFP package.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03 8/2013
tKQ
tCycle
Curr (x18)
Curr (x36)
tKQ
tCycle
Curr (x18)
Curr (x36)
-333
3.0
3.0
-250
3.0
4.0
-200
3.0
5.0
-150
3.8
6.7
Unit
ns
ns
365
425
290
345
250
290
215
240
mA
mA
5.0
5.0
270
315
5.5
5.5
245
280
6.5
6.5
210
250
7.5
7.5
200
230
ns
ns
mA
mA
1/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
A
A
E1
E2
NC
NC
BB
BA
E3
VDD
VSS
CK
W
CKE
G
ADV
A
A
A
A
GS8320Z18AGT-xxxV Pinout
NC
NC
NC
VDDQ
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
2M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03 8/2013
2/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
A
A
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
W
CKE
G
ADV
A
A
A
A
GS8320Z36AGT-xxxV Pinout
DQPC
DQC
DQC
VDDQ
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03 8/2013
3/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
100-Pin TQFP Pin Descriptions
Symbol
Type
Description
A 0, A 1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
Clock Input Signal
BA
In
Byte Write signal for data inputs DQA1-DQA9; active low
BB
In
Byte Write signal for data inputs DQB1-DQB9; active low
BC
In
Byte Write signal for data inputs DQC1-DQC9; active low
BD
In
Byte Write signal for data inputs DQD1-DQD9; active low
W
In
Write Enable; active low
E1
In
Chip Enable; active low
E2
In
Chip Enable; Active High. For self decoded depth expansion
E3
In
Chip Enable; Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
DQA
I/O
Byte A Data Input and Output pins
DQB
I/O
Byte B Data Input and Output pins
DQC
I/O
Byte C Data Input and Output pins
DQD
I/O
Byte D Data Input and Output pins
ZZ
In
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
LBO
In
Linear Burst Order; active low
VDD
In
Core power supply
VSS
In
Ground
VDDQ
In
Output driver power supply
NC
—
No Connect
Rev: 1.03 8/2013
4/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Register 1
Register 2
K
Write Data
Write Data
K
D
Q
K
FT
DQa–DQn
GS8320Z18/36AGT-xxxV NBT SRAM Functional Block Diagram
Memory
Array
Sense Amps
FT
Register 2
Register 1
Control Logic
5/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G
CKE
CK
E3
E2
E1
BD
BC
BB
BA
W
LBO
ADV
A0–An
K
K
Data Coherency
Match
Read, Write and
K
Write Address
Write Address
K
K
D
Q
SA1
SA0
Burst
Counter
SA1’
SA0’
Write Drivers
Rev: 1.03 8/2013
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
W
BA
BB
BC
BD
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.03 8/2013
6/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Synchronous Truth Table
Operation
Type
Address
CK
CKE
ADV
W
Bx
E1
E2
E3
G
ZZ
DQ
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Abort, Begin Burst
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z
1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
None
X
X
X
X
X
X
X
X
X
H
High-Z
Current
L-H
H
X
X
X
X
X
X
X
L
-
Sleep Mode
Clock Edge Ignore, Stall
Notes
1
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03 8/2013
7/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Pipeline and Flow Through Read Write Control State Diagram
D
B
Deselect
W
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
R
Burst Read
W
Burst Write
B
B
D
Key
D
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ Transition
Current State (n)
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
Current State
ƒ
ƒ
ƒ
Next State
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 1.03 8/2013
8/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Pipeline Mode Data I/O State Diagram
Intermediate
B W
R B
Intermediate
R
High Z
(Data In)
D
Data Out
(Q Valid)
W
D
Intermediate
Intermediate
W
Intermediate
R
High Z
B
D
Intermediate
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ Transition
Current State (n)
Transition
Intermediate State (N+1)
n
Next State (n+2)
n+1
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
Current State
Intermediate
State
Next State
ƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03 8/2013
9/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Flow Through Mode Data I/O State Diagram
B W
R B
R
High Z
(Data In)
Data Out
(Q Valid)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ Transition
Current State (n)
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
Current State
ƒ
ƒ
ƒ
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.03 8/2013
10/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.03 8/2013
Note:
The burst counter wraps to initial state on the 5th clock.
11/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
tZZR
tZZS
tZZH
ZZ
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.03 8/2013
12/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage on VDDQ Pins
–0.5 to VDD
V
VI/O
Voltage on I/O Pins
–0.5 to VDD +0.5 ( 4.6 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDD +0.5 ( 4.6 V max.)
V
IIN
Input Current on Any Pin
+/–20
mA
IOUT
Output Current on Any I/O Pin
+/–20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
–55 to 125
o
TBIAS
Temperature Under Bias
–55 to 125
o
C
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version)
Parameter
Symbol
Min.
Typ.
Max.
Unit
1.8 V Supply Voltage
VDD1
1.7
1.8
2.0
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
1.8 V VDDQ I/O Supply Voltage
VDDQ1
1.7
1.8
VDD
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
VDD
V
Parameter
Symbol
Min.
Typ.
Max.
Unit
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
VDDQ2 & VDDQ1 Range Logic Levels
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the
device.
2. VIH (max) must be met for any instantaneous value of VDD.
3. VDD needs to power-up before or at the same time as VDDQ to make sure VIH (max) is not exceeded.
Rev: 1.03 8/2013
13/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
85
C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
25
100
C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Package
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
100 TQFP
4-layer
28.7
23.8
22.3
15.1
6.5
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Note:
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
8
10
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
12
14
pF
Note:
These parameters are sample tested.
Rev: 1.03 8/2013
14/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDDQ/2
Output load
Fig. 1
Figure 1
Output Load 1
DQ
30pF*
50
VDDQ/2
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
FT Input Current
IIN
VDD  VIN  0 V
–100 uA
100 uA
Output Leakage Current
IOL
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
1.8 V Output High Voltage
VOH1
IOH = –4 mA, VDDQ = 1.7 V
VDDQ – 0.4 V
—
2.5 V Output High Voltage
VOH2
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
1.8 V Output Low Voltage
VOL1
IOL = 4 mA
—
0.4 V
2.5 V Output Low Voltage
VOL2
IOL = 8 mA
—
0.4 V
Rev: 1.03 8/2013
15/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
Rev: 1.03 8/2013
—
—
ZZ VDD – 0.2 V
Device Deselected;
All other inputs
VIH or  VIL
Operating
Current
Standby
Current
Deselect
Current
245
25
55
55
IDD
IDDQ
ISB
ISB
Flow Through
Pipeline
Flow Through
Flow Through
Pipeline
IDD
100
100
330
35
IDD
IDDQ
Pipeline
IDD
270
45
IDD
IDDQ
Flow Through
Pipeline
120
120
75
75
265
25
350
35
290
45
375
70
–40
to
85°C
-333
0
to
70°C
355
70
Symbol
IDD
IDDQ
Mode
Notes:
1. IDD and IDDQ apply to any combination of VDD and VDDQ operation.
2. All parameters listed are worst case scenario.
(x18)
Device Selected;
All other inputs
VIH or VIL
Output open
(x36)
Test Conditions
Parameter
Operating Currents
100
100
55
55
225
20
265
25
240
40
295
50
0
to
70°C
120
120
75
75
245
20
285
25
260
40
315
50
–40
to
85°C
-250
100
100
55
55
195
15
230
20
215
35
250
40
0
to
70°C
120
120
75
75
215
15
250
20
235
35
270
40
–40
to
85°C
-200
100
100
55
55
185
15
200
15
200
30
210
30
0
to
70°C
120
120
75
75
205
15
220
15
220
30
230
30
–40
to
85°C
-150
mA
mA
mA
mA
mA
mA
mA
mA
Unit
GS8320Z18/36AGT-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/22
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
AC Electrical Characteristics
Pipeline
Flow
Through
Parameter
Symbol
Clock Cycle Time
-333
-250
-200
-150
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tKC
3.0
—
4.0
—
5.0
—
6.7
—
ns
Clock to Output Valid
tKQ
—
3.0
—
3.0
—
3.0
—
3.8
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.0
—
1.2
—
1.4
—
1.5
—
ns
Hold time
tH
0.1
—
0.2
—
0.4
—
0.5
—
ns
Clock Cycle Time
tKC
5.0
—
5.5
—
6.5
—
7.5
—
ns
Clock to Output Valid
tKQ
—
5.0
—
5.5
—
6.5
—
7.5
ns
Clock to Output Invalid
tKQX
2.0
—
2.0
—
2.0
—
2.0
—
ns
Clock to Output in Low-Z
tLZ1
2.0
—
2.0
—
2.0
—
2.0
—
ns
Setup time
tS
1.3
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.3
—
0.5
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
1.0
—
1.3
—
1.3
—
1.5
—
ns
Clock LOW Time
tKL
1.2
—
1.5
—
1.5
—
1.7
—
ns
Clock to Output in
High-Z
tHZ1
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.8
ns
G to Output Valid
tOE
—
3.0
—
3.0
—
3.0
—
3.8
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ1
—
3.0
—
3.0
—
3.0
—
3.8
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.03 8/2013
17/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Pipeline Mode Timing (NBT)
Write A
Read B
Suspend
Read C
tKH
Write D
Write No-op
Read E
Deselect
tKC
tKL
CK
tH
tS
A
A
B
C
D
E
tH
tS
CKE
tH
tS
E*
tH
tS
ADV
tH
tS
W
tH
tH
tS
tS
Bn
tH
tLZ
tKQ
tS
DQ
Rev: 1.03 8/2013
D(A)
Q(B)
Q(C)
D(D)
18/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tHZ
tKQX
Q(E)
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
tKL
tKH
tKC
CK
tH
tS
CKE
tH
tS
E
tH
tS
ADV
tH
tS
W
tH
tS
Bn
tH
tS
A0–An
A
B
C
D
E
F
G
tKQ
tH
tKQ
tLZ
tS
DQ
D(A)
D(B)
D(B+1)
tKQX
tHZ
Q(C)
Q(D)
tLZ
D(E)
tKQX
Q(F)
D(G)
tOLZ
tOE
tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.03 8/2013
19/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Description
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity

Lead Angle
D
D1
Symbol
Pin 1
TQFP Package Drawing (Package T)

L
c
L1
Min. Nom. Max
e
b
A1
A2
0.10
Y
0
—
7
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.03 8/2013
20/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
Ordering Information—GSI NBT Synchronous SRAM
Org
Part Number1
Type
Voltage
Option
Package
Speed2
(MHz/ns)
TJ3
2M x 18
GS8320Z18AGT-333V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
333/5.0
C
2M x 18
GS8320Z18AGT-250V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
250/5.5
C
2M x 18
GS8320Z18AGT-200V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
200/6.5
C
2M x 18
GS8320Z18AGT-150V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
150/7.5
C
1M x 36
GS8320Z36AGT-333V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
333/5.0
C
1M x 36
GS8320Z36AGT-250V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
250/5.5
C
1M x 36
GS8320Z36AGT-200V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
200/6.5
C
1M x 36
GS8320Z36AGT-150V
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
150/7.5
C
2M x 18
GS8320Z18AGT-333IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
333/5.0
I
2M x 18
GS8320Z18AGT-250IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
250/5.5
I
2M x 18
GS8320Z18AGT-200IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
200/6.5
I
2M x 18
GS8320Z18AGT-150IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
150/7.5
I
1M x 36
GS8320Z36AGT-333IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
333/5.0
I
1M x 36
GS8320Z36AGT-250IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
250/5.5
I
1M x 36
GS8320Z36AGT-200IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
200/6.5
I
1M x 36
GS8320Z36AGT-150IV
NBT
1.8 V or 2.5 V
RoHS-compliant TQFP
150/7.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. 
Example: GS8320Z36AGT-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. C = Commercial Temperature Range. I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03 8/2013
21/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8320Z18/36AGT-xxxV
36Mb Sync SRAM Datasheet Revision History
File Name
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8320ZxxA_V_r1
8320ZxxA_V_r1_01
Content
• Updated Absolute Maximum Ratings
• Added thermal information
8320ZxxA_V_r1_02
Content
• Updated to reflect MP status
8320ZxxA_V_r1_03
Content
• Updated Op current numbers
• Updated tHZ, tOE, and tOHZ to 3.0 ns for 333 and 300 MHz
Rev: 1.03 8/2013
22/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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