IBM z/Architecture 参考摘要

SA22-7871-08.book Page i Thursday, February 19, 2015 3:46 PM
z/Architecture
IBMr
Reference Summary
SA22-7871-08
SA22-7871-08.book Page ii Thursday, February 19, 2015 3:46 PM
.
SA22-7871-08.book Page i Thursday, February 19, 2015 3:46 PM
z/Architecture
IBMr
Reference Summary
SA22-7871-08
SA22-7871-08.book Page ii Thursday, February 19, 2015 3:46 PM
Ninth Edition (March, 2015)
This revision differs from the previous edition by containing instructions related to the
facilities marked by a bar under “Facility” in “Preface” and minor corrections and clarifications. Changes are indicated by a bar in the margin.
References in this publication to IBM® products, programs, or services do not imply
that IBM intends to make these available in all countries in which IBM operates. Any
reference to an IBM program product in this publication is not intended to state or
imply that only IBM’s program product may be used. Any functionally equivalent program may be used instead.
Additional copies of this and other IBM publications may be ordered or downloaded
from the IBM publications web site at http://www.ibm.com/support/documentation.
Please direct any comments on the contents of this publication to:
IBM Corporation
Department E57A
2455 South Road
Poughkeepsie, NY
12601-5400
USA
IBM may use or distribute whatever information you supply in any way it believes
appropriate without incurring any obligation to you.
© Copyright International Business Machines Corporation 2001-2015. All rights
reserved.
US Government Users Restricted Rights — Use, duplication, or disclosure restricted
by GSA ADP Schedule Contract with IBM Corp.
ii
z/Architecture Reference Summary
SA22-7871-08.book Page iii Thursday, February 19, 2015 3:46 PM
Preface
This publication is intended primarily for use by z/Architecture™ assembler-language
application programmers. It contains basic machine information summarized from the
IBM z/Architecture Principles of Operation (SA22-7832), about the IBM z Systems™
processors. It also contains frequently used information from IBM ESA/390 Common
I/O-Device Commands and Self Description (SA22-7204), IBM System/370 Extended
Architecture Interpretive Execution (SA22-7095), The Load-Program-Parameter and
the CPU-Measurement Facilities (SC23-2260), and IBM High Level Assembler for
z/OS, z/VM & z/VSE Language Reference (SC26-4940). This publication will be
updated from time to time. However, the above publications and others cited in this
publication are the authoritative reference sources and will be first to reflect changes.
The following instructions may be uninstalled or not available on a particular model:
Facility
Instruction
ASN-and-LX-reuse
EPAIR, ESAIR, PTI, SSAIR
Compare-and-swap-and-store
CSST
Configuration-topology
PTF
Constrained-transactional-execution
TBEGINC
DAT-enhancement 1
CSPG, IDTE
DAT-enhancement 2
LPTEA
Decimal-floating-point
ADTR, AXTR, CDGTR, CDSTR, CDTR, CDUTR, CEDTR,
CEXTR, CGDTR, CGXTR, CSDTR, CSXTR, CUDTR,
CUXTR, CXGTR, CXSTR, CXTR, CXUTR, DDTR, DXTR,
EEDTR, EEXTR, ESDTR, ESXTR, FIDTR, FIXTR,
IEDTR, IEXTR, KDTR, KXTR, LDETR, LDXTR, LEDTR,
LTDTR, LTXTR, LXDTR, MDTR, MXTR, QADTR, QAXTR,
RRDTR, RRXTR, SDTR, SLDT, SLXT, SRDT, SRXT,
SXTR, TDCDT, TDCET, TDCXT, TDGDT, TDGET, TDGXT
DFP-rounding
SRNMT
DFP-packed-conversion
CDPT, CPDT, CPXT, CXPT
DFP-zoned-conversion
CDZT, CXZT, CZDT, CZXT
Distinct-operands
AGHIK, AGRK, AHIK, ALGHSIK, ALGRK, ALHSIK, ALRK,
ARK, NGRK, NRK, OGRK, ORK, SGRK, SLAK, SLGRK,
SLLK, SLRK, SRAK, SRK, SRLK, XGRK, XRK
Enhanced-DAT 1
PFMF
Enhanced-DAT 2
CRDTE
Execute-extensions
EXRL
Execution-hint
BPP, BPRP, NIAI
Expanded-storage
PGIN, PGOUT
Extended-immediate
AFI, AGFI, ALFI, ALGFI, CFI, CGFI, CLFI, CLGFI,
FLOGR, IIHF, IILF, LBR, LGBR, LGHR, LGFI, LHR, LLC,
LLCR, LLGCR, LLGHR, LLH, LLHR, LLIHF, LLILF, LT,
LTG, NIHF, NILF, OIHF, OILF, SLFI, SLGFI, XIHF, XILF
Extended-translation 2
CLCLU, MVCLU, PKA, PKU, TP, TROO, TROT, TRTO,
TRTT, UNPKA, UNPKU
Extended-translation 3
CU14, CU24, CU41, CU42, SRSTU, TRTR
Extract-CPU-time
ECTG
Floating-point-extension
ADTRA, AXTRA, CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,
CEGBRA, CELFBR, CELGBR, CFDBRA, CFDTR,
CFEBRA, CFXBRA, CFXTR, CGDBRA, CGDTRA, CGEBRA, CGXBRA, CGXTRA, CLFDBR, CLFDTR, CLFEBR,
CLFXBR, CLFXTR, CLGDBR, CLGDTR, CLGEBR,
CLGXBR, CLGXTR, CXFBRA, CXFTR, CXGBRA, CXGTRA, CXLFBR, CXLFTR, CXLGBR, CXLGTR, DDTRA,
DXTRA, FIDBRA, FIEBRA, FIXBRA, LDXBRA, LEDBRA,
LEXBRA, MDTRA, MXTRA, SDTRA, SRNMB, SXTRA
Floating-point-support-sign-handling
CPSDR, LCDFR, LNDFR, LPDFR
FPR-GR-transfer
LDGR, LGDR
iii
SA22-7871-08.book Page iv Thursday, February 19, 2015 3:46 PM
Facility
Instruction
General-instructions-extension
ASI, AGSI, ALSI, ALGSI, CRB, CGRB, CRJ, CGRJ, CRT,
CGRT, CGH, CHHSI, CHSI, CGHSI, CHRL, CGHRL, CIB,
CGIB, CIJ, CGIJ, CIT, CGIT, CLRB, CLGRB, CLRJ,
CLGRJ, CLRT, CLGRT, CLHHSI, CLFHSI, CLGHSI, CLIB,
CLGIB, CLIJ, CLGIJ, CLFIT, CLGIT, CLRL, CLHRL,
CLGRL, CLGHRL, CLGFRL, CRL, CGRL, CGFRL,
ECAG, LAEY, LTGF, LHRL, LGHRL, LLHRL, LLGHRL,
LLGFRL, LRL, LGRL, LGFRL, MVHHI, MVHI, MVGHI,
MFY, MHY, MSFI, MSGFI, PFD, PFDRL, RNSBG,
RXSBG, RISBG, ROSBG, STHRL, STRL, STGRL
HFP-multiply-and-add/subtract
MAD, MADR, MAE, MAER, MSD, MSDR, MSE, MSER
HFP-unnormalized extensions
MAY, MAYR, MAYH, MAYHR, MAYL, MAYLR, MY, MYH,
MYL, MYR, MYHR, MYLR
High-word
AHHHR, AHHLR, AIH, ALHHHR, ALHHLR, ALSIH,
ALSIHN, BRCTH, CHF, CHHR, CHLR, CIH, CLHF,
CLHHR, CLHLR, CLIH, LBH, LHH, LFH, LLCH, LLHH,
RISBHG, RISBLG, SHHHR, SHHLR, SLHHHR, SLHHLR,
STCH, STHH, STFH
IEEE-exception-simulation
LFAS, SFASR
Interlocked-access
LAA, LAAG, LAAL, LAALG, LAN, LANG, LAO, LAOG,
LAX, LAXG, LPD, LPDG
Load-and-trap
LAT, LFHAT, LGAT, LLGFAT, LLGTAT
Load-and-zero-rightmost-byte
LLZRGF, LZRF, LZRG
Load/store-on-condition facility 1
LOC, LOCG, LOCGR, LOCR, STOC, STOCG
Load/store-on-condition facility 2
LOCFH, LOCFHR, LOCGHI, LOCHHI, LOCHI, STOCFH
Long displacement
AHY, ALY, AY, CDSY, CHY, CLIY, CLMY, CLY, CSY, CVBY,
CVDY, CY, ICMY, ICY, LAMY, LAY, LB, LDY, LEY, LGB,
LHY, LMY, LRAY, LY, MSY, MVIY, NIY, NY, OIY, OY, SHY,
SLY, STAMY, STCMY, STCY, STDY, STEY, STHY, STMY,
STY, SY, TMY, XIY, XY
Message-security-assist
KM, KMC, KIMD, KLMD, KMAC
Message-security-assist extension 3
PCKMO
Message-security-assist extension 4
KMCTR, KMF, KMO, PCC
Message-security-assist extension 5
PPNO
Miscellaneous-general-instructions
CLT, CLGT, RISBGN
Move-with-optional-specifications
MVCOS
Parsing-enhancement
TRTE, TRTRE
Perform-floating-point-operation
PFPO
Population-count
POPCNT
Processor-assist
PPA
Reset-reference-bits-multiple
RRBM
Store-clock fast
STCKF
Store-facility-list extended
STFLE
TOD-clock steering
PTFF
Transactional-execution
ETND, NTSTG, TABORT, TBEGIN, TEND
Vector-facility-for-z/Architecture
LCBB, VA, VAC, VACC, VACCC, VAVG, VAVGL, VCDG,
VCDLG, VCEQ, VCGD, VCH, VCHL, VCKSM, VCLGD,
VCLZ, VCTZ, VEC, VECL, VERIM, VERLL, VERLLV,
VESL, VESLV, VESRA, VESRAV, VESRL, VESRLV, VFA,
VFAE, VFCE, VFCH, VFCHE, VFD, VFEE, VFENE, VFI,
VFM, VFMA, VFMS, VFPSO, VFS, VFSQ, VFTCI, VGBM,
VGEF, VGEG, VGFM, VGFMA, VGM, VISTR, VL, VLBB,
VLC, VLDE, VLEB, VLED, VLEF, VLEG, VLEH, VLEIB,
VLEIF, VLEIG, VLEIH, VLGV, VLL, VLLEZ, VLM, VLP,
VLR, VLREP, VLVG, VLVGP, VMAE, VMAH, VMAL,
VMALE, VMALH, VMALO, VMAO, VME, VMH, VML,
VMLE, VMLH, VMLO, VMN, VMNL, VMO, VMRH, VMRL,
VMX, VMXL, VN, VNC, VNO, VO, VPDI, VPERM, VPK,
VPKLS, VPKS, VPOPCT, VREP, VREPI, VS, VSBCBI,
VSBI, VSCBI, VSCEF, VSCEG, VSEG, VSEL, VSL,
VSLB, VSLDB, VSRA, VSRAB, VSRL, VSRLB, VST,
VSTEB, VSTEF, VSTEG, VSTEH, VSTL, VSTM, VSTRC,
VSUM, VSUMG, VSUMQ, VTM, VUPH, VUPL, VUPLH,
VUPLL, VX, WFC, WFK
iv
z/Architecture Reference Summary
SA22-7871-08.book Page v Thursday, February 19, 2015 3:46 PM
For information about Enterprise Systems Architecture/390® (ESA/390™) architecture, refer to IBM Enterprise Systems Architecture/390 Principles of Operation,
SA22-7201, and IBM Enterprise Systems Architecture/390 Reference Summary,
SA22-7209.
Note: IBM, z/Architecture, zSeries, IBM z Systems, Enterprise Systems Architecture/390, and ESA/390 are trademarks of the International Business Machines Corporation in the United States, other countries, or both.
v
SA22-7871-08.book Page vi Thursday, February 19, 2015 3:46 PM
vi
z/Architecture Reference Summary
SA22-7871-08.book Page vii Thursday, February 19, 2015 3:46 PM
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Machine Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Machine Instructions by Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Machine Instructions by Operation Code. . . . . . . . . . . . . . . . . . . . . . . . . 26
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Assembler Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Extended-Mnemonic Instructions for Branch on Condition . . . . . . 38
Extended-Mnemonic Instructions for Relative-Branch Instructions 38
Extended-Mnemonic Suffixes for Compare-and-Branch, and
Compare-and-Trap Instructions . . . . . . . . . . . . . . . . . . . . . . . . 39
Extended-Mnemonic Suffixes for Load/Store-on-Condition
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Extended-Mnemonic Suffixes for Rotate-Then-Insert / AND / OR /
Exclusive OR-Selected-Bits Instructions . . . . . . . . . . . . . . . . . 39
Extended-Mnemonics for Vector-Facility Instructions . . . . . . . . . . 40
CNOP Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Summary of Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Assigned Storage Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
External-Interruption Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Program-Interruption Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Data-Exception Code (DXC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Vector-Exception Code (VXC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PER Code, ATMID, and AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Translation-Exception Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Machine-Check Interruption Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
External-Damage Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Facility Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Floating-Point-Control (FPC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Program-Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
z/Architecture PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ESA/390 PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Dynamic Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Virtual-Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Address-Space-Control Element (ASCE) . . . . . . . . . . . . . . . . . . . 52
Region-Table or Segment-Table Designation (RTD or STD) . . . . 52
Real-Space Designation (RSD) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Region-Table Entry (RTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Segment-Table Entry (STE, FC=0) . . . . . . . . . . . . . . . . . . . . . . . . 53
Segment-Table Entry (STE, FC=1) . . . . . . . . . . . . . . . . . . . . . . . . 53
Page-Table Entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ASN Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Address-Space Number (ASN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ASN-First-Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ASN-Second-Table Entry (ASTE) . . . . . . . . . . . . . . . . . . . . . . . . . 54
PC-Number Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Program-Call Number (20-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Program-Call Number (32-Bit, Bit 44=0) . . . . . . . . . . . . . . . . . . . . 55
Program-Call Number (32-Bit, Bit 44=1) . . . . . . . . . . . . . . . . . . . . 55
Linkage-Table Entry (LTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
vii
SA22-7871-08.book Page viii Thursday, February 19, 2015 3:46 PM
Linkage-First-Table Entry (LFTE) . . . . . . . . . . . . . . . . . . . . . . . . . 56
Linkage-Second-Table Entry (LSTE) . . . . . . . . . . . . . . . . . . . . . . 56
Entry-Table Entry (ETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Access-Register Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Access-List-Entry Token (ALET) . . . . . . . . . . . . . . . . . . . . . . . . . 57
Dispatchable-Unit-Control Table (DUCT) . . . . . . . . . . . . . . . . . . . 57
Access-List Entry (ALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Linkage-Stack Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Entry Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Header Entry (Entry Type 0001001) . . . . . . . . . . . . . . . . . . . . . . . 59
Trailer Entry (Entry Type 0001010) . . . . . . . . . . . . . . . . . . . . . . . 59
Branch State Entry (Entry Type 0001100) and
Program-Call State Entry (Entry Type 0001101) . . . . . . . . . . . 59
Trapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Trap Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Trap Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Trace-Entry Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Identification of Trace Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Branch in Subspace Group (if ASN Tracing on) . . . . . . . . . . . . . . 63
Mode Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mode-Switching Branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Program Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Program Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Program Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Set Secondary ASN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operand of Store Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operand of Store Clock Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Transaction Diagnostic Block (TDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Operation-Request Block (ORB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Command-Mode ORB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Transport-Mode ORB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Channel-Command Word (CCW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Format-0 CCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Format-1 CCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Indirect-Data-Address Word (IDAW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Format-1 IDAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Format-2 IDAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Modified-CCW-Indirect-Data-Address Word (MIDAW) . . . . . . . . . 73
Transport Control Word (TCW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Transport-Indirect-Data-Address Word (TIDAW) . . . . . . . . . . . . . 74
Transport Command Control Block (TCCB) . . . . . . . . . . . . . . . . . . . . . . 74
Transport Command Area Header (TCAH) . . . . . . . . . . . . . . . . . 74
Device-Command Word (DCW) . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Transport Command Area Trailer (TCAT) . . . . . . . . . . . . . . . . . . 76
CBC-Offset Block (COB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Transport Status Block (TSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Transport Status Header (TSH) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O-Status TSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Device-Detected-Program-Check TSA . . . . . . . . . . . . . . . . . . . . . 78
Interrogate TSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Subchannel-Information Block (SCHIB) . . . . . . . . . . . . . . . . . . . . . . . . . 80
Path-Management-Control Word (PMCW) . . . . . . . . . . . . . . . . . . 80
viii
z/Architecture Reference Summary
SA22-7871-08.book Page ix Thursday, February 19, 2015 3:46 PM
Interruption-Response Block (IRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Command-Mode Subchannel-Status Word (SCSW) . . . . . . . . . . 81
Transport-Mode Subchannel-Status Word (SCSW) . . . . . . . . . . . 82
Extended-Status Word (ESW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Format-0 ESW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Format-0 ESW Word 0 (Subchannel Logout) . . . . . . . . . . . . . . . . 84
Format-0 ESW Word 1 (Extended-Report Word) . . . . . . . . . . . . . 84
Format-1 ESW Word 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Format-2 ESW Word 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Format-3 ESW Word 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Information Stored in ESW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Extended-Control Word (ECW) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Extended-Measurement Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Format 0 Measurement Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Format 1 Measurement Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Channel-Report Word (CRW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Error-Recovery Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reporting Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I/O Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Standard Command-Code Assignments (CCW and DCW
Bits 0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Standard Meanings of Bits of First Sense Byte . . . . . . . . . . . . . . . 88
Character Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Control Character Representations . . . . . . . . . . . . . . . . . . . . . . . 91
Additional ISO-8 Control Character Representations . . . . . . . . . . 91
Formatting Character Representations . . . . . . . . . . . . . . . . . . . . . 91
Two-Character BSC Data Link Controls . . . . . . . . . . . . . . . . . . . . 91
Commonly Used Editing Pattern Characters . . . . . . . . . . . . . . . . 91
ANSI-Defined Printer Control Characters . . . . . . . . . . . . . . . . . . . 92
Hexadecimal and Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Powers of 2 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ix
SA22-7871-08.book Page x Thursday, February 19, 2015 3:46 PM
x
z/Architecture Reference Summary
SA22-7871-08.book Page 1 Thursday, February 19, 2015 3:46 PM
Machine Instruction Formats
E
Op Code
0
I
15
Op Code
0
IE
I
8
15
Op Code
MII
16
M1
Op Code
0
RI-a
8
RI-b
8
RI-c
8
0
RIE-a
8
RIE-b
R1
Op Code
RIE-c
8
RIE-d
8
RIE-e
8
RIE-f
8
RIE-g
8
16
31
8
16
32
RI4
32
RI4
32
I2
32
RI2
32
I4
24
I2
47
I5
////////
47
Op Code
47
Op Code
47
Op Code
40
32
32
40
40
////////
16
I3
40
40
////////
16
16
36
I2
16
16
36
M3 / / / / Op Code
16
M3
12
M3 / / / / Op Code
I2
R2
12
R1
Op Code
0
RI2 ‡
R3
12
R1
Op Code
0
31
R3
12
R1
Op Code
0
RI2
16
M3
12
R1
Op Code
0
31
R2
12
R1
Op Code
0
I2 ‡
Op
12
47
16
Op
12
8
0
24
R1 / / / /
Op Code
0
RI3
Op
12
M1
Op Code
28 31
RI2
12
R1
Op Code
0
24
12
R1
Op Code
0
I2
I1
////////
0
47
Op Code
40
47
Op Code
40
47
1
SA22-7871-08.book Page 2 Thursday, February 19, 2015 3:46 PM
RIL-a
R1
Op Code
0
RIL-b
8
R1
Op Code
0
RIL-c
8
RIS
0
8
RRD
M3
12
8
16
0
16
8
8
8
8
////
12
L1
Op Code
0
2
8
8
I2
20
32
20
24
24
M4‡
20
20
R1
24
R1
24
B4
16
Op Code
40
47
R2
28 31
R2
28 31
M3 / / / / Op Code
32
36
40
47
D2
20
31
B2
16
R2
28 31
D4
B2
16
28 31
20
D2
20
R3
12
L1
Op Code
0
M3
12
R1
Op Code
0
R3‡
12
R1
Op Code
0
RSL-b
12
R1
Op Code
0
R2
R1
Op Code
0
RSL-a
D4
M3‡ M4‡
Op Code
RSI
16
R3
Op Code
RS-b
B4
16
0
RS-a
47
/ / / / / / / / R1‡ R2‡
Op Code
RRS
RI2
16
16
0
RRF-c-e
47
R1 / / / / R3
Op Code
RRF-a,b
16
12 15
0
RRE
RI2
R2‡
R1
Op Code
0
47
Op
12
R1
Op Code
RR
12
8
16
Op
M1
Op Code
0
I2
Op
12
31
RI2
16
31
D2
B2
16
20
B2
16
D2
20
////////
32
////////
32
z/Architecture Reference Summary
Op Code
40
47
Op Code
40
47
SA22-7871-08.book Page 3 Thursday, February 19, 2015 3:46 PM
RSY-a
RSY-b
8
RX-a
8
8
RXF
8
RXY-a
8
RXY-b
X2
12
X2
M1
Op Code
S
12
8
0
X2
R1
Op Code
0
X2
12
R3
Op Code
0
X2
12
R1
Op Code
0
X2
12
M1
Op Code
RXE
12
8
0
M3
R1
Op Code
0
RX-b
12
R1
Op Code
0
R3
R1
Op Code
0
8
12
8
16
SMI
8
M1 / / / /
Op Code
0
SS-a
8
8
8
L2
12
32
DL2
40
36
40
DH2
20
32
DL2
47
32
47
Op Code
40
DH2
20
47
Op Code
40
47
D2‡
20
31
D1
20
31
D1
20
I2
32
DL1
20
47
DH1
32
D1
47
B2
32
D1
20
47
RI2
32
20
B1
Op Code
40
D3
20
B1
16
36
R1 / / / / Op Code
20
B3
16
16
L1
Op Code
0
12
L or L1
Op Code
0
SS-b
16
M3‡ / / / / Op Code
32
D2
B1
I2
Op Code
0
D2
B1
Op Code
31
20
B2
16
47
D2
B2
16
Op Code
40
31
20
B2
16
47
D2
B2
16
32
20
B2
16
Op Code
40
DH2
20
B2
16
16
0
SIY
16
DH2
32
DL2
B1
I2
Op Code
SIL
B2
16
0
DL2
20
B2‡
Op Code
0
SI
B2
16
D2
36
B2
32
47
D2
36
47
3
SA22-7871-08.book Page 4 Thursday, February 19, 2015 3:46 PM
SS-c
SS-d
8
SS-e
8
12
8
SSE
R3
12
8
8
VRI-b
8
0
VRI-c
8
0
VRI-d
8
VRI-e
8
0
VRR-a
8
VRR-b
8
0
VRR-c
8
8
V2
V2
12
V1
Op Code
0
D1
D1
32
16
32
I3
24
V2
12
32
32
24
I3
D2
36
47
D2
36
47
36
40
47
36
40
47
36
40
47
M5‡ RXB Op Code
I4
////
20
47
M4 RXB Op Code
16
V3
D2
36
M4 RXB Op Code
I2
16
47
M3‡ RXB Op Code
I2
16
D4
B2
20
47
36
B2
32
I2
36
B2
32
20
V2
12
V1
Op Code
D1
20
47
D2
B4
32
32
M5
12
V1
Op Code
0
V2
12
V1
Op Code
D2
20
V3
12
V1
Op Code
0
16
////
12
V1
Op Code
32
B1
D2
36
B2
20
////
12
V1
Op Code
Op
12
V1
Op Code
0
4
R3
D1
B2
16
16
0
VRI-a
16
B2
32
B1
Op Code
Op Code
D1
20
B1
16
0
SSF
B1
16
B1
L2
Op Code
0
R3
R1
Op Code
0
SS-f
12
R1
Op Code
0
I3
L1
Op Code
0
28
36
40
47
M4 RXB Op Code
32
36
40
47
/ / / / / / / / M5‡ M4‡ M3‡ RXB Op Code
16
V3
16
V3
16
24
28
32
36
40
47
/ / / / M5‡ / / / / M4‡ RXB Op Code
20
24
28
32
36
40
47
/ / / / M6‡ M5‡ M4‡ RXB Op Code
20
24
28
32
z/Architecture Reference Summary
36
40
47
SA22-7871-08.book Page 5 Thursday, February 19, 2015 3:46 PM
VRR-d
V1
Op Code
0
VRR-e
8
0
VRR-f
8
8
0
VRS-b
8
VRS-c
8
0
VRV
8
VRX
8
0
8
V2
12
V1
Op Code
V3
12
V1
Op Code
0
R3
12
R1
Op Code
V3
12
V1
Op Code
0
R2
12
V1
Op Code
V2
12
V1
Op Code
0
VRS-a
12
V1
Op Code
V2
X2
12
V3
16
V3
16
M5‡ M6‡ / / / /
20
20
20
D2
20
D2
B2
16
40
47
RXB Op Code
40
47
36
40
47
36
40
47
36
40
47
M3‡ RXB Op Code
32
D2
20
36
M4 RXB Op Code
32
20
47
M4‡ RXB Op Code
32
D2
40
M4‡ RXB Op Code
32
20
B2
16
32
36
D2
B2
16
28
36
V4 RXB Op Code
////////////////
B2
16
24
32
20
B2
16
28
M6‡ / / / / M5‡
R3
16
24
V4 RXB Op Code
36
40
47
M3‡ RXB Op Code
32
36
40
47
Denotes association with first, second, third, fourth, fifth, or sixth
operand
a, b, c, d, e, f
Distinguishes among instances of the same basic instruction
format
Base register designation field
B1, B2, B3, B4
D1, D2, D3, D4
Displacement field (including DH and DL for long-displacement
forms)
Immediate operand field
I, I2, I3, I4, I5
L, L1, L2
Length field
M1, M3, M4, M5, M6 Mask field
R1, R2, R3
Register designation field
Relative-immediate operand field
RI2, RI3, RI4
RXB
Most significant bits of vector registers designated by the V1, V2,
V3, V4 fields, respectively
X2
Index register designation field
‡
For certain instructions, this operand is not defined
1, 2, 3, 4, 5, 6
5
SA22-7871-08.book Page 6 Thursday, February 19, 2015 3:46 PM
Machine Instructions by Mnemonic
Mnemonic
A
AD
ADB
ADBR
ADR
ADTR
ADTRA
AE
AEB
AEBR
AER
AFI
AG
AGF
AGFI
AGFR
AGHI
AGHIK
AGR
AGRK
AGSI
AH
AHHHR
AHHLR
AHI
AHIK
AHY
AIH
AL
ALC
ALCG
ALCGR
ALCR
ALFI
ALG
ALGF
ALGFI
ALGFR
ALGHSIK
Name
Add (32)
Add Normalized (LH)
Add (LB)
Add (LB)
Add Normalized (LH)
Add (LD)
ADD (LD)
Add Normalized (SH)
Add (SB)
Add (SB)
Add Normalized (SH)
Add Immediate (32)
Add (64)
Add (6432)
Add Immediate (6432)
Add (6432)
Add Halfword Immediate (6416)
Add Immediate (6416)
Add (64)
Add (64)
Add Immediate (648)
Add Halfword (3216)
Add High (32)
Add High (32)
Add Halfword Immediate (3216)
Add Immediate (3216)
Add Halfword (3216)
Add Immediate High (32)
Add Logical (32)
Add Logical with Carry (32)
Add Logical with Carry (64)
Add Logical with Carry (64)
Add Logical with Carry (32)
Add Logical Immediate (32)
Add Logical (64)
Add Logical (6432)
Add Logical Immediate (6432)
Add Logical (6432)
Add Logical with Signed Immediate
(6416)
ALGR
R1,R2
Add Logical (64)
ALGRK R1,R2,R3
Add Logical (64)
Add Logical with Signed Immediate (648)
ALGSI
D1(B1),I2
ALHHHR R1,R2,R3
Add Logical High (32)
ALHHLR R1,R2,R3
Add Logical High (32)
ALHSIK R1,R3,I2
Add Logical with Signed Immediate
(3216)
Add Logical (32)
ALR
R1,R2
ALRK
R1,R2,R3
Add Logical (32)
ALSI
D1(B1),I2
Add Logical with Signed Immediate (328)
ALSIH
R1,I2
Add Logical with Signed Immediate High
(32)
Add Logical with Signed Immediate High
ALSIHN R1,I2
(32)
ALY
R1,D2(X2,B2)
Add Logical (32)
AP
D1(L1,B1),D2(L2,B2) Add Decimal
AR
R1,R2
Add (32)
Add (32)
ARK
R1,R2,R3
ASI
D1(B1),I2
Add Immediate (328)
6
Operands
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2,R3
R1,R2,R3,M4
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,I2
R1,R2
R1,I2
R1,R3,I2
R1,R2
R1,R2,R3
D1(B1),I2
R1,D2(X2,B2)
R1,R2,R3
R1,R2,R3
R1,I2
R1,R3,I2
R1,D2(X2,B2)
R1,I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,I2
R1,R2
R1,R3,I2
z/Architecture Reference Summary
Format
RX-a
RX-a
RXE
RRE
RR
RRF-a
RRF-a
RX-a
RXE
RRE
RR
RIL-a
RXY-a
RXY-a
RIL-a
RRE
RI-a
RIE-d
RRE
RRF-a
SIY
RX-a
RRF-a
RRF-a
RI-a
RIE-d
RXY-a
RIL-a
RX-a
RXY-a
RXY-a
RRE
RRE
RIL-a
RXY-a
RXY-a
RIL-a
RRE
RIE-d
Opcode
5A
6A
ED1A
B31A
2A
B3D2
B3D2
7A
ED0A
B30A
3A
C29
E308
E318
C28
B918
A7B
ECD9
B908
B9E8
EB7A
4A
B9C8
B9D8
A7A
ECD8
E37A
CC8
5E
E398
E388
B988
B998
C2B
E30A
E31A
C2A
B91A
ECDB
Class
&
Notes
c
¤c
¤c
¤c
¤c
¤ c TF
¤cF
¤c
¤c
¤c
¤c
c EI
cN
cN
c EI
cN
cN
c DO
cN
c DO
c GE
c
c HW
c HW
c
c DO
c LD
c HW
c
c N3
cN
cN
c N3
c EI
cN
cN
c EI
cN
c DO
RRE
RRF-a
SIY
RRF-a
RRF-a
RIE-d
B90A
B9EA
EB7E
B9CA
B9DA
ECDA
cN
c DO
c GE
c HW
c HW
c DO
RR
RRF-a
SIY
RIL-a
1E
B9FA
EB6E
CCA
c
c DO
c GE
c HW
RIL-a CCB HW
RXY-a
SS-b
RR
RRF-a
SIY
E35E
FA
1A
B9F8
EB6A
c LD
¤c
c
c DO
c GE
SA22-7871-08.book Page 7 Thursday, February 19, 2015 3:46 PM
Mnemonic
AU
AUR
AW
AWR
AXBR
AXR
AXTR
AXTRA
AY
BAKR
BAL
BALR
BAS
BASR
BASSM
BC
BCR
BCT
BCTG
BCTGR
BCTR
BPP
BPRP
BRAS
BRASL
BRC
BRCL
BRCT
BRCTG
BRCTH
BRXH
BRXHG
BRXLE
BRXLG
BSA
BSG
BSM
BXH
BXHG
BXLE
BXLEG
C
CD
CDB
CDBR
CDFBR
CDFBRA
CDFR
CDFTR
CDGBR
CDGBRA
CDGR
CDGTR
CDGTRA
CDLFBR
CDLFTR
CDLGBR
CDLGTR
CDPT
CDR
Operands
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2,R3
R1,R2,R3,M4
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,R2
R1,R2
M1,D2(X2,B2)
M1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
M1,RI2,D3(B3)
M1,RI2,RI3
R1,RI2
R1,RI2
M1,RI2
M1,RI2
R1,RI2
R1,RI2
R1,RI2
R1,R3,RI2
R1,R3,RI2
R1,R3,RI2
R1,R3,RI2
R1,R2
R1,R2
R1,R2
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,D2(X2,B2)
R1,D2(X2B2),M3
R1,D2(X2,B2)
R1,R2
R1,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,R2
R1,R2
R1,M3,R2,M4
R1,M3,R2,M4
R1,M3,R2,M4
R1,M3,R2,M4
R1,M3,R2,M4
R1,D2(L2,B2),M3
R1,R2
ForName
mat
Add Unnormalized (SH)
RX-a
Add Unnormalized (SH)
RR
Add Unnormalized (LH)
RX-a
Add Unnormalized (LH)
RR
Add (EB)
RRE
Add Normalized (EH)
RR
Add (ED)
RRF-a
ADD (ED)
RRF-a
Add (32)
RXY-a
Branch and Stack
RRE
Branch and Link
RX-a
Branch and Link
RR
Branch and Save
RX-a
Branch and Save
RR
Branch and Save and Set Mode
RR
Branch on Condition
RX-b
Branch on Condition
RR
Branch on Count (32)
RX-a
Branch on Count (64)
RXY-a
Branch on Count (64)
RRE
Branch on Count (32)
RR
Branch Prediction Preload
SMI
Branch Prediction Relative Preload
MII
Branch Relative and Save
RI-b
Branch Relative and Save Long
RIL-b
Branch Relative on Condition
RI-c
Branch Relative on Condition Long
RIL-c
Branch Relative on Count (32)
RI-b
Branch Relative on Count (64)
RI-b
Branch Relative on Count High (32)
RIL-b
Branch Relative on Index High (32)
RSI
Branch Relative on Index High (64)
RIE-e
Branch Relative on Index Low or Equal (32) RSI
Branch Relative on Index Low or Equal (64) RIE-e
Branch and Set Authority
RRE
Branch in Subspace Group
RRE
Branch and Set Mode
RR
Branch on Index High (32)
RS-a
Branch on Index High (64)
RSY-a
Branch on Index Low or Equal (32)
RS-a
Branch on Index Low or Equal (64)
RSY-a
Compare (32)
RX-a
Compare (LH)
RX-a
Compare (LB)
RXE
Compare (LB)
RRE
Convert from Fixed (LB32)
RRE
Convert from Fixed (LB32)
RRF-e
Convert from Fixed (LH32)
RRE
Convert from Fixed (LD32)
RRE
Convert from Fixed (LB64)
RRE
Convert from Fixed (LB64)
RRF-e
Convert from Fixed (LH64)
RRE
Convert from Fixed (LD64)
RRE
Convert from Fixed (LD64)
RRF-e
Convert from Logical (LB32)
RRF-e
Convert from Logical (LD32)
RRF-e
Convert from Logical (LB64)
RRF-e
Convert from Logical (LD64)
RRF-e
Convert from Packed (To Long DFP)
RSL-b
Compare (LH)
RR
Opcode
7E
3E
6E
2E
B34A
36
B3DA
B3DA
E35A
B240
45
05
4D
0D
0C
47
07
46
E346
B946
06
C7
C5
A75
C05
A74
C04
A76
A77
CC6
84
EC44
85
EC45
B25A
B258
0B
86
EB44
87
EB45
59
69
ED19
B319
B395
B395
B3B5
B951
B3A5
B3A5
B3C5
B3F1
B3F1
B391
B953
B3A1
B952
EDAE
29
Class
&
Notes
¤c
¤c
¤c
¤c
¤c
¤c
¤ c TF
¤cF
c LD
¤
¤
¤
¤
¤
¤
¤
¤
¤
¤N
¤N
¤
¤ EH
¤ EH
¤
¤ N3
¤
¤ N3
¤
¤N
¤ HW
¤
¤N
¤
¤N
q
¤
¤
¤
¤N
¤
¤N
c
c
¤c
¤c
¤
¤F
¤
¤F
¤N
¤F
¤N
¤ TF
¤F
¤F
¤F
¤F
¤F
PC
¤c
7
SA22-7871-08.book Page 8 Thursday, February 19, 2015 3:46 PM
Mnemonic
CDS
CDSG
CDSTR
CDSY
CDTR
CDUTR
CDZT
CE
CEB
CEBR
CEDTR
CEFBR
CEFBRA
CEFR
CEGBR
CEGBRA
CEGR
CELFBR
CELGBR
CER
CEXTR
CFC
CFDBR
CFDBRA
CFDR
CFDTR
CFEBR
CFEBRA
CFER
CFI
CFXBR
CFXBRA
CFXR
CFXTR
CG
CGDBR
CGDBRA
CGDR
CGDTR
CGDTRA
CGEBR
CGEBRA
CGER
CGF
CGFI
CGFR
CGFRL
CGH
CGHI
CGHRL
CGHSI
CGIB
CGIJ
Operands
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R2
R1,R3,D2(B2)
R1,R2
R1,R2
R1,D2(L2,B2),M3
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,M3,R2,M4
R1,R2
R1,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,M3,R2,M4
R1,R2
R1,R2
D2(B2)
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,I2
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2,M4
R1,D2(X2,B2)
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,D2(X2,B2)
R1,I2
R1,R2
R1,RI2
R1,D2(X2,B2)
R1,I2
R1,RI2
D1(B1),I2
R1,I2,M3,D4(B4)
R1,I2,M3,RI4
CGIT
CGR
CGRB
CGRJ
CGRL
CGRT
R1,I2,M3
R1,R2
R1,R2,M3,D4(B4)
R1,R2,M3,RI4
R1,RI2
R1,R2,M3
8
ForName
mat
Compare Double and Swap (32)
RS-a
Compare Double and Swap (64)
RSY-a
Convert from Signed Packed (LD64)
RRE
Compare Double and Swap (32)
RSY-a
Compare (LD)
RRE
Convert from Unsigned Packed (LD64) RRE
Comvert from Zoned (to long DFP)
RSL-b
Compare (SH)
RX-a
Compare (SB)
RXE
Compare (SB)
RRE
Compare Biased Exponent (LD)
RRE
Convert from Fixed (SB32)
RRE
Convert from Fixed (SB32)
RRF-e
Convert from Fixed (SH32)
RRE
Convert from Fixed (SB64)
RRE
Convert from Fixed (SB64)
RRF-e
Convert from Fixed (SH64)
RRE
Convert from Logical (SB32)
RRF-e
Convert from Logical (SB64)
RRF-e
Compare (SH)
RR
Compare Biased Exponent (ED)
RRE
Compare and Form Codeword
S
Convert to Fixed (32LB)
RRF-e
Convert to Fixed (32LB)
RRF-e
Convert to Fixed (32LH)
RRF-e
Convert to Fixed (32LD)
RRF-e
Convert to Fixed (32SB)
RRF-e
Convert to Fixed (32SB)
RRF-e
Convert to Fixed (32SH)
RRF-e
Compare Immediate (32)
RIL-a
Convert to Fixed (32EB)
RRF-e
Convert to Fixed (32EB)
RRF-e
Convert to Fixed (32EH)
RRF-e
Convert to Fixed (32ED)
RRF-e
Compare (64)
RXY-a
Convert to Fixed (64LB)
RRF-e
Convert to Fixed (64LB)
RRF-e
Convert to Fixed (64LH)
RRF-e
Convert to Fixed (64LD)
RRF-e
Convert to Fixed (64LD)
RRF-e
Convert to Fixed (64SB)
RRF-e
Convert to Fixed (64SB)
RRF-e
Convert to Fixed (64SH)
RRF-e
Compare (6432)
RXY-a
Compare Immediate (6432)
RIL-a
Compare (6432)
RRE
Compare Relative Long (6432)
RIL-b
Compare Halfword (6416)
RXY-a
Compare Halfword Immediate (6416)
RI-a
Compare Halfword Relative Long (6416) RIL-b
Compare Halfword Immediate (6416)
SIL
Compare Immediate and Branch (648) RIS
Compare Immediate and Branch Relative RIE-c
(648)
Compare Immediate and Trap (6416)
RIE-a
Compare (64)
RRE
Compare and Branch (64)
RRS
Compare and Branch Relative (64)
RIE-b
Compare Relative Long (64)
RIL-b
Compare and Trap (64)
RRF-c
z/Architecture Reference Summary
Opcode
BB
EB3E
B3F3
EB31
B3E4
B3F2
EDAA
79
ED09
B309
B3F4
B394
B394
B3B4
B3A4
B3A4
B3C4
B390
B3A0
39
B3FC
B21A
B399
B399
B3B9
B941
B398
B398
B3B8
C2D
B39A
B39A
B3BA
B949
E320
B3A9
B3A9
B3C9
B3E1
B3E1
B3A8
B3A8
B3C8
E330
C2C
B930
C6C
E334
A7F
C64
E558
ECFC
EC7C
Class
&
Notes
¤c
¤cN
¤ TF
¤ c LD
¤ c TF
¤ TF
¤ ZF
¤c
¤c
¤c
¤ c TF
¤
¤F
¤
¤N
¤F
¤N
¤F
¤F
¤c
¤ c TF
i¤c
¤c
¤cF
¤c
¤cF
¤c
¤cF
¤c
c EI
¤c
¤cF
¤c
¤cF
cN
¤cN
¤cF
¤cN
¤ c TF
¤cF
¤cN
¤cF
¤cN
cN
c EI
cN
c GE
c GE
cN
c GE
c GE
¤ GE
¤ GE
EC70
B920
ECE4
EC64
C68
B960
GE
cN
¤ GE
¤ GE
c GE
GE
SA22-7871-08.book Page 9 Thursday, February 19, 2015 3:46 PM
Mnemonic
CGXBR
CGXBRA
CGXR
CGXTR
CGXTRA
CH
CHF
CHHR
CHHSI
CHI
CHLR
CHRL
CHSI
CHY
CIB
CIH
CIJ
Operands
R1,M3,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2
R1,M3,R2,M4
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
D1(B1),I2
R1,I2
R1,R2
R1,RI2
D1(B1),I2
R1,D2(X2,B2)
R1,I2,M3,D4(B4)
R1,I2
R1,I2,M3,RI4
CIT
CKSM
CL
CLC
CLCL
CLCLE
CLCLU
CLFDBR
CLFDTR
CLFEBR
CLFHSI
CLFI
CLFIT
R1,I2,M3
R1,R2
R1,D2(X2,B2)
D1(L,B1),D2(B2)
R1,R2
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,M3,R2,M4
R1,M3,R2,M4
R1,M3,R2,M4
D1(B1),I2
R1,I2
R1,I2,M3
CLFXBR
CLFXTR
CLG
CLGDBR
CLGDTR
CLGEBR
CLGF
CLGFI
CLGFR
CLGFRL
CLGHRL
CLGHSI
CLGIB
R1,M3,R2,M4
R1,M3,R2,M4
R1,D2(X2,B2)
R1,M3,R2,M4
R1,M3,R2,M4
R1,M3,R2,M4
R1,D2(X2,B2)
R1,I2
R1,R2
R1,RI2
R1,RI2
D1(B1),I2
R1,I2,M3,D4(B4)
CLGIJ
R1,I2,M3,RI4
CLGIT
R1,I2,M3
CLGR
CLGRB
CLGRJ
CLGRL
CLGRT
CLGT
CLGXBR
CLGXTR
CLHF
CLHHR
CLHHSI
R1,R2
R1,R2,M3,D4(B4)
R1,R2,M3,RI4
R1,RI2
R1,R2,M3
R1,M3,D2(B2)
R1,M3,R2,M4
R1,M3,R2,M4
R1,D2(X2,B2)
R1,R2
D1(B1),I2
ForName
mat
Convert to Fixed (64EB)
RRF-e
Convert to Fixed (64EB)
RRF-e
Convert to Fixed (64EH)
RRF-e
Convert to Fixed (64ED)
RRF-e
Convert to Fixed (64ED)
RRF-e
Compare Halfword (3216)
RX-a
Compare High (32)
RXY-a
Compare High (32)
RRE
Compare Halfword Immediate (1616)
SIL
Compare Halfword Immediate (3216)
RI-a
Compare High (32)
RRE
Compare Halfword Relative Long (3216) RIL-b
Compare Halfword Immediate (3216)
SIL
Compare Halfword (3216)
RXY-a
Compare Immediate and Branch (328) RIS
Compare Immediate High (32)
RIL-a
Compare Immediate and Branch Relative RIE-c
(328)
Compare Immediate and Trap (3216)
RIE-a
Checksum
RRE
Compare Logical (32)
RX-a
Compare Logical (character)
SS-a
Compare Logical Long
RR
Compare Logical Long Extended
RS-a
Compare Logical Long Unicode
RSY-a
Convert to Logical (32LB)
RRF-e
Convert to Logical (32LD)
RRF-e
Convert to Logical (32SB)
RRF-e
Compare Logical Immediate (3216)
SIL
Compare Logical Immediate (32)
RIL-a
Compare Logical Immediate and Trap
RIE-a
(3216)
Convert to Logical (32EB)
RRF-e
Convert to Logical (32ED)
RRF-e
Compare Logical (64)
RXY-a
Convert to Logical (64LB)
RRF-e
Convert to Logical (64LD)
RRF-e
Convert to Logical (64SB)
RRF-e
Compare Logical (6432)
RXY-a
Compare Logical Immediate (6432)
RIL-a
Compare Logical (6432)
RRE
Compare Logical Relative Long (6432) RIL-b
Compare Logical Relative Long (6416) RIL-b
Compare Logical Immediate (6416)
SIL
Compare Logical Immediate and Branch RIS
(648)
Compare Logical Immediate and Branch RIE-c
Relative (648)
Compare Logical Immedical and Trap
RIE-a
(6416)
Compare Logical (64)
RRE
Compare Logical and Branch (64)
RRS
Compare Logical and Branch Relative (64) RIE-b
Compare Logical Relative Long (64)
RIL-b
Compare Logical and Trap (64)
RRF-c
Compare Logical and Trap (64)
RSY-b
Convert to Logical (64EB)
RRF-e
Convert to Logical (64ED)
RRF-e
Compare Logical High (32)
RXY-a
Compare Logical High (32)
RRE
Compare Logical Immediate (1616)
SIL
Opcode
B3AA
B3AA
B3CA
B3E9
B3E9
49
E3CD
B9CD
E554
A7E
B9DD
C65
E55C
E379
ECFE
CCD
EC7E
Class
&
Notes
¤cN
¤cF
¤cN
¤ c TF
¤cF
c
c HW
c HW
c GE
c
c HW
c GE
c GE
c LD
¤ GE
c HW
¤ GE
EC72
B241
55
D5
0F
A9
EB8F
B39D
B943
B39C
E55D
C2F
EC73
GE
¤c
c
¤c
ic
¤c
¤ c E2
¤cF
¤cF
¤cF
c GE
c EI
GE
B39E
B94B
E321
B3AD
B942
B3AC
E331
C2E
B931
C6E
C66
E559
ECFD
¤cF
¤cF
cN
¤cF
¤cF
¤cF
cN
c EI
cN
c GE
c GE
c GE
¤ GE
EC7D ¤ GE
EC71 GE
B921
ECE5
EC65
C6A
B961
EB2B
B3AE
B94A
E3CF
B9CF
E555
cN
¤ GE
¤ GE
c GE
GE
MI
¤cF
¤cF
c HW
c HW
c GE
9
SA22-7871-08.book Page 10 Thursday, February 19, 2015 3:46 PM
Mnemonic
CLHLR
CLHRL
CLI
CLIB
CLIH
CLIJ
CLIY
CLM
CLMH
CLMY
CLR
CLRB
CLRJ
CLRL
CLRT
CLST
CLT
CLY
CMPSC
CP
CPDT
CPSDR
CPXT
CPYA
CR
CRB
CRDTE
CRJ
CRL
CRT
CS
CSCH
CSDTR
CSG
CSP
CSPG
CSST
CSXTR
CSY
CU12
CU14
CU21
CU24
CU41
CU42
CUDTR
CUSE
CUTFU
CUUTF
CUXTR
CVB
CVBG
CVBY
CVD
CVDG
CVDY
CXBR
CXFBR
10
Operands
R1,R2
R1,RI2
D1(B1),I2
R1,I2,M3,D4(B4)
Name
Compare Logical High (32)
Compare Logical Relative Long (3216)
Compare Logical Immediate
Compare Logical Immediate and Branch
(328)
R1,I2
Compare Logical Immediate High (32)
R1,I2,M3,RI4
Compare Logical Immediate and Branch
Relative (328)
D1(B1),I2
Compare Logical Immediate
R1,M3,D2(B2)
Compare Logical Char. under Mask (low)
R1,M3,D2(B2)
Compare Logical Char. under Mask (high)
R1,M3,D2(B2)
Compare Logical Char. under Mask (low)
Compare Logical (32)
R1,R2
R1,R2,M3,D4(B4) Compare Logical and Branch (32)
R1,R2,M3,RI4
Compare Logical and Branch Relative (32)
R1,RI2
Compare Logical Relative Long (32)
R1,R2,M3
Compare Logical and Trap (32)
R1,R2
Compare Logical String
R1,M3,D2(B2)
Compare Logical and Trap (32)
R1,D2(X2,B2)
Compare Logical (32)
R1,R2
Compression Call
D1(L1,B1),D2(L2,B2) Compare Decimal
R1,D2(L2,B2),M3
Convert to Packed (From Long DFP)
R1,R3,R2
Copy Sign (L)
R1,D2(L2,B2),M3
Convert to Packed (From Extended DFP)
R1,R2
Copy Access
R1,R2
Compare (32)
R1,R2,M3,D4(B4) Compare and Branch (32)
R1,R3,R2[,M4]
Compare and Replace DAT Table Entry
R1,R2,M3,RI4
R1,RI2
R1,R2,M3
R1,R3,D2(B2)
R1,R2,M4
R1,R3,D2(B2)
R1,R2
R1,R2
D1(B1),D2(B2),R3
R1,R2,M4
R1,R3,D2(B2)
R1,R2[,M3]
R1,R2[,M3]
R1,R2[,M3]
R1,R2[,M3]
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2[,M3]
R1,R2[,M3]
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
Compare and Branch Relative (32)
Compare Relative Long (32)
Compare and Trap (32)
Compare and Swap (32)
Clear Subchannel
Convert to Signed Packed (64LD)
Compare and Swap (64)
Compare and Swap and Purge (32)
Compare and Swap and Purge (64)
Compare and Swap and Store
Convert to Signed Packed (128ED)
Compare and Swap (32)
Convert UTF-8 to UTF-16
Convert UTF-8 to UTF-32
Convert UTF-16 to UTF-8
Convert UTF-16 to UTF-32
Convert UTF-32 to UTF-8
Convert UTF-32 to UTF-16
Convert to Unsigned Packed (64LD)
Compare until Substring Equal
Convert UTF-8 to Unicode
Convert Unicode to UTF-8
Convert to Unsigned Packed (128ED)
Convert to Binary (32)
Convert to Binary (64)
Convert to Binary (32)
Convert to Decimal (32)
Convert to Decimal (64)
Convert to Decimal (32)
Compare (EB)
Convert from Fixed (EB32)
z/Architecture Reference Summary
Format
RRE
RIL-b
SI
RIS
Opcode
B9DF
C67
95
ECFF
Class
&
Notes
c HW
c GE
c
¤ GE
RIL-a CCF c HW
RIE-c EC7F ¤ GE
SIY
RS-b
RSY-b
RSY-b
RR
RRS
RIE-b
RIL-b
RRF-c
RRE
RSY-b
RXY-a
RRE
SS-b
RSL-b
RRF-b
RSL-b
RRE
RR
RRS
RRF-b
EB55
BD
EB20
EB21
15
ECF7
EC77
C6F
B973
B25D
EB23
E355
B263
F9
EDAC
B372
EDAD
B24D
19
ECF6
B98F
RIE-b
RIL-b
RRF-c
RS-a
S
RRF-d
RSY-a
RRE
RRE
SSF
RRF-d
RSY-a
RRF-c
RRF-c
RRF-c
RRF-c
RRE
RRE
RRE
RRE
RRF-c
RRF-c
RRE
RX-a
RXY-a
RXY-a
RX-a
RXY-a
RXY-a
RRE
RRE
EC76
C6D
B972
BA
B230
B3E3
EB30
B250
B98A
C82
B3EB
EB14
B2A7
B9B0
B2A6
B9B1
B9B2
B9B3
B3E2
B257
B2A7
B2A6
B3EA
4F
E30E
E306
4E
E32E
E326
B349
B396
c LD
c
cN
c LD
c
¤ GE
¤ GE
c GE
GE
¤c
MI
c LD
i¤c
¤c
c PC
¤ FS
c PC
¤
c
¤ GE
ED2
pc
¤ GE
c GE
GE
¤c
pc
¤ TF
¤cN
pc
p c DE
¤c
¤ TF
¤ c LD
¤c
¤ c E3
¤c
¤ c E3
¤ c E3
¤ c E3
¤ TF
ic
¤c
¤c
¤ TF
¤
¤N
¤ LD
¤
¤N
¤ LD
¤c
¤
SA22-7871-08.book Page 11 Thursday, February 19, 2015 3:46 PM
Mnemonic
CXFBRA
CXFR
CXFTR
CXGBR
CXGBRA
CXGR
CXGTR
CXGTRA
CXLFBR
CXLFTR
CXLGBR
CXLGTR
CXPT
CXR
CXSTR
CXTR
CXUTR
CXZT
CY
CZDT
CZXT
D
DD
DDB
DDBR
DDR
DDTR
DDTRA
DE
DEB
DEBR
DER
DIDBR
DIEBR
DL
DLG
DLGR
DLR
DP
DR
DSG
DSGF
DSGFR
DSGR
DXBR
DXR
DXTR
DXTRA
EAR
ECAG
ECTG
ED
EDMK
EEDTR
EEXTR
EFPC
EPAIR
EPAR
EPSW
EREG
ForOperands
Name
mat
R1,M3,R2,M4
Convert from Fixed (EB32)
RRF-e
R1,R2
Convert from Fixed (EH32)
RRE
R1,M3,R2,M4
Convert from Fixed (ED32)
RRE
Convert from Fixed (EB64)
RRE
R1,R2
R1,M3,R2,M4
Convert from Fixed (EB64)
RRF-e
R1,R2
Convert from Fixed (EH64)
RRE
R1,R2
Convert from Fixed (ED64)
RRE
R1,M3,R2,M4
Convert from Fixed (ED64)
RRF-e
Convert from Logical (EB32)
RRF-e
R1,M3,R2,M4
R1,M3,R2,M4
Convert from Logical (ED32)
RRF-e
R1,M3,R2,M4
Convert from Logical (EB64)
RRF-e
R1,M3,R2,M4
Convert from Logical (ED64)
RRF-e
Convert from Packed (To Extended DFP) RSL-b
R1,D2(L2,B2),M3
R1,R2
Compare (EH)
RRE
Convert from Signed Packed (ED128) RRE
R1,R2
R1,R2
Compare (ED)
RRE
R1,R2
Convert from Unsigned Packed (ED128) RRE
R1,D2(L2,B2),M3
Comvert from Zoned (to extended DFP)
RSL-b
R1,D2(X2,B2)
Compare (32)
RXY-a
R1,D2(L2,B2),M3
Comvert to Zoned (from long DFP)
RSL-b
R1,D2(L2,B2),M3
Comvert to Zoned (from extended DFP)
RSL-b
R1,D2(X2,B2)
Divide (3264)
RX-a
R1,D2(X2,B2)
Divide (LH)
RX-a
R1,D2(X2,B2)
Divide (LB)
RXE
R1,R2
Divide (LB)
RRE
R1,R2
Divide (LH)
RR
R1,R2,R3
Divide (LD)
RRF-a
R1,R2,R3,M4
Divide (LD)
RRF-a
R1,D2(X2,B2)
Divide (SH)
RX-a
R1,D2(X2,B2)
Divide (SB)
RXE
R1,R2
Divide (SB)
RRE
R1,R2
Divide (SH)
RR
R1,R3,R2,M4
Divide to Integer (LB)
RRF-b
R1,R3,R2,M4
Divide to Integer (SB)
RRF-b
R1,D2(X2,B2)
Divide Logical (3264)
RXY-a
R1,D2(X2,B2)
Divide Logical (64128)
RXY-a
R1,R2
Divide Logical (64128)
RRE
R1,R2
Divide Logical (3264)
RRE
D1(L1,B1),D2(L2,B2) Divide Decimal
SS-b
R1,R2
Divide (3264)
RR
Divide Single (64)
RXY-a
R1,D2(X2,B2)
R1,D2(X2,B2)
Divide Single (6432)
RXY-a
Divide Single (6432)
RRE
R1,R2
R1,R2
Divide Single (64)
RRE
Divide (EB)
RRE
R1,R2
R1,R2
Divide (EH)
RRE
R1,R2,R3
Divide (ED)
RRF-a
R1,R2,R3,M4
Divide (ED)
RRF-a
R1,R2
Extract Access
RRE
R1,R3,D2(B2)
Extract CPU Attribute
RSY-a
D1(B1),D2(B2),R3
Extract CPU Time
SSF
D1(L,B1),D2(B2)
Edit
SS-a
D1(L,B1),D2(B2)
Edit and Mark
SS-a
R1,R2
Extract Biased Exponent (64LD)
RRE
Extract Biased Exponent (64ED)
RRE
R1,R2
R1
Extract FPC
RRE
Extract Primary ASN and Instance
RRE
R1
R1
Extract Primary ASN
RRE
R1,R2
Extract PSW
RRE
Extract Stacked Registers (32)
RRE
R1,R2
Opcode
B396
B3B6
B959
B3A6
B3A6
B3C6
B3F9
B3F9
B392
B95B
B3A2
B95A
EDAF
B369
B3FB
B3EC
B3FA
EDAB
E359
EDA8
EDA9
5D
6D
ED1D
B31D
2D
B3D1
B3D1
7D
ED0D
B30D
3D
B35B
B353
E397
E387
B987
B997
FD
1D
E30D
E31D
B91D
B90D
B34D
B22D
B3D9
B3D9
B24F
EB4C
C81
DE
DF
B3E5
B3ED
B38C
B99A
B226
B98D
B249
Class
&
Notes
¤F
¤
¤F
¤N
¤F
¤N
¤ TF
¤F
¤F
¤F
¤F
¤F
PC
¤c
¤ TF
¤ c TF
¤ TF
¤ ZF
c LD
¤ ZF
¤ ZF
¤
¤
¤
¤
¤
¤ TF
¤F
¤
¤
¤
¤
¤c
¤c
¤ N3
¤N
¤N
¤ N3
¤
¤
¤N
¤N
¤N
¤N
¤
¤
¤ TF
¤F
¤ GE
¤ ET
¤c
¤c
¤ TF
¤ TF
¤
q RA
q
¤ N3
¤
11
SA22-7871-08.book Page 12 Thursday, February 19, 2015 3:46 PM
Mnemonic
EREGG
ESAIR
ESAR
ESDTR
ESEA
ESTA
ESXTR
ETND
EX
EXRL
FIDBR
FIDBRA
FIDR
FIDTR
FIEBR
FIEBRA
FIER
FIXBR
FIXBRA
FIXR
FIXTR
FLOGR
HDR
HER
HSCH
IAC
IC
ICM
ICMH
ICMY
ICY
IDTE
IEDTR
IEXTR
IIHF
IIHH
IIHL
IILF
IILH
IILL
IPK
IPM
IPTE
ISKE
IVSK
KDB
KDBR
KDTR
KEB
KEBR
KIMD
KLMD
KM
KMAC
KMC
KMCTR
KMF
KMO
KXBR
KXTR
12
Operands
R1,R2
R1
R1
R1,R2
R1,R2
R1,R2
R1,R2
R1
R1,D2(X2,B2)
R1,RI2
R1,M3,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,M3,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,R2
R1,R2
R1,R2
R1
R1,D2(X2,B2)
R1,M3,D2(B2)
R1,M3,D2(B2)
R1,M3,D2(B2)
R1,D2(X2,B2)
R1,R3,R2
R1,R3,R2
R1,R3,R2
R1,I2
R1,I2
R1,I2
R1,I2
R1,I2
R1,I2
R1
R1,R2
R1,R2
R1,R2
R1,D2(X2,B2)
R1,R2
R1,R2
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R3,R2
R1,R2
R1,R2
R1,R2
R1,R2
Name
Extract Stacked Registers (64)
Extract Secondary ASN and Instance
Extract Secondary ASN
Extract Significance (64LD)
Extract and Set Extended Authority
Extract Stacked State
Extract Significance (64ED)
Extract Transaction Nesting Depth
Execute
Execute Relative Long
Load FP Integer (LB)
Load FP Integer (LB)
Load FP Integer (LH)
Load FP Integer (LD)
Load FP Integer (SB)
Load FP Integer (SB)
Load FP Integer (SH)
Load FP Integer (EB)
Load FP Integer (EB)
Load FP Integer (EH)
Load FP Integer (ED)
Find Leftmost One
Halve (LH)
Halve (SH)
Halt Subchannel
Insert Address Space Control
Insert Character
Insert Characters under Mask (low)
Insert Characters under Mask (high)
Insert Characters under Mask (low)
Insert Character
Invalidate DAT Table Entry
Insert Biased Exponent (LD64&LD)
Insert Biased Exponent (ED64&ED)
Insert Immediate (high)
Insert Immediate (high high)
Insert Immediate (high low)
Insert Immediate (low)
Insert Immediate (low high)
Insert Immediate (low low)
Insert PSW Key
Insert Program Mask
Invalidate Page Table Entry
Insert Storage Key Extended
Insert Virtual Storage Key
Compare and Signal (LB)
Compare and Signal (LB)
Compare and Signal (LD)
Compare and Signal (SB)
Compare and Signal (SB)
Compute Intermediate Message Digest
Compute Last Message Digest
Cipher Message
Compute Message Authentication Code
Cipher Message with Chaining
Cipher Message with Counter
Cipher Message with Cipher Feedback
Cipher Message with Output Feedback
Compare and Signal (EB)
Compare and Signal (ED)
z/Architecture Reference Summary
Format
RRE
RRE
RRE
RRE
RRE
RRE
RRE
RRE
RX-a
RIL-b
RRF-e
RRF-e
RRE
RRF-e
RRF-e
RRF-e
RRE
RRF-e
RRF-e
RRE
RRF-e
RRE
RR
RR
S
RRE
RX-a
RS-b
RSY-b
RSY-b
RXY-a
RRF-b
RRF-b
RRF-b
RIL-a
RI-a
RI-a
RIL-a
RI-a
RI-a
S
RRE
RRF-a
RRE
RRE
RXE
RRE
RRE
RXE
RRE
RRE
RRE
RRE
RRE
RRE
RRF-b
RRE
RRE
RRE
RRE
Opcode
B90E
B99B
B227
B3E7
B99D
B24A
B3EF
B2EC
44
C60
B35F
B35F
B37F
B3D7
B357
B357
B377
B347
B347
B367
B3DF
B983
24
34
B231
B224
43
BF
EB80
EB81
E373
B98E
B3F6
B3FE
C08
A50
A51
C09
A52
A53
B20B
B222
B221
B229
B223
ED18
B318
B3E0
ED08
B308
B93E
B93F
B92E
B91E
B92F
B92D
B92A
B92B
B348
B3E8
Class
&
Notes
¤N
q RA
q
¤ TF
pN
¤c
¤ TF
¤ TX
¤
¤ XX
¤
¤F
¤
¤ TF
¤
¤F
¤
¤
¤F
¤
¤ TF
c EI
¤
¤
pc
qc
c
cN
c LD
LD
p u DE
¤ TF
¤ TF
EI
N
N
EI
N
N
q
p
p
q
¤c
¤c
¤ c TF
¤c
¤c
¤ c MS
¤ c MS
¤ c MS
¤ c MS
¤ c MS
¤ c M4
¤ c M4
¤ c M4
¤c
¤ cTF
SA22-7871-08.book Page 13 Thursday, February 19, 2015 3:46 PM
Mnemonic
L
LA
LAA
LAAG
LAAL
LAALG
LAE
LAEY
LAM
LAMY
LAN
LANG
LAO
LAOG
LARL
LASP
LAT
LAX
LAXG
LAY
LB
LBH
LBR
LCBB
LCDBR
LCDFR
LCDR
LCEBR
LCER
LCGFR
LCGR
LCR
LCTL
LCTLG
LCXBR
LCXR
LD
LDE
LDEB
LDEBR
LDER
LDETR
LDGR
LDR
LDXBR
LDXBRA
LDXR
LDXTR
LDY
LE
LEDBR
LEDBRA
LEDR
LEDTR
LER
LEXBR
LEXBRA
LEXR
LEY
LFAS
Operands
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,RI2
D1(B1),D2(B2)
R1,D2(X2,B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2),M3
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R2
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2,M4
R1,R2
R1,R2
R1,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,M3,R2,M4
R1,R2
R1,M3,R2,M4
R1,R2
R1,R2
R1,M3,R2,M4
R1,R2
R1,D2(X2,B2)
D2(B2)
Name
Load (32)
Load Address
Load and Add (32)
Load and Add (64)
Load and Add Logical (32)
Load and Add Logical (64)
Load Address Extended
Load Address Extended
Load Access Multiple
Load Access Multiple
Load and AND (32)
Load and AND (64)
Load and OR (32)
Load and OR (64)
Load Address Relative Long
Load Address Space Parameters
Load and Trap (32)
Load and Exclusive OR (32)
Load and Exclusive OR (64)
Load Address
Load Byte (328)
Load Byte High (328)
Load Byte (328)
Load Count to Block Boundary
Load Complement (LB)
Load Complement (L)
Load Complement (LH)
Load Complement (SB)
Load Complement (SH)
Load Complement (6432)
Load Complement (64)
Load Complement (32)
Load Control (32)
Load Control (64)
Load Complement (EB)
Load Complement (EH)
Load (L)
Load Lengthened (LHSH)
Load Lengthened (LBSB)
Load Lengthened (LBSB)
Load Lengthened (LHSH)
Load Lengthened (LDSD)
Load FPR from GR (L64)
Load (L)
Load Rounded (LBEB)
Load Rounded (LBEB)
Load Rounded (LHEH)
Load Rounded (LDED)
Load (L)
Load (S)
Load Rounded (SBLB)
Load Rounded (SBLB)
Load Rounded (SHLH)
Load Rounded (SDLD)
Load (S)
Load Rounded (SBEB)
Load Rounded (SBEB)
Load Rounded (SHEH)
Load (S)
Load FPC and Signal
Format
RX-a
RX-a
RSY-a
RSY-a
RSY-a
RSY-a
RX-a
RXY-a
RS-a
RSY-a
RSY-a
RSY-a
RSY-a
RSY-a
RIL-b
SSE
RXY-a
RSY-a
RSY-a
RXY-a
RXY-a
RXY-a
RRE
RXE
RRE
RRE
RR
RRE
RR
RRE
RRE
RR
RS-a
RSY-a
RRE
RRE
RX-a
RXE
RXE
RRE
RRE
RRF-d
RRE
RR
RRE
RRF-e
RR
RRF-e
RXY-a
RX-a
RRE
RRF-e
RR
RRF-e
RR
RRE
RRF-e
RRE
RXY-a
S
Opcode
58
41
EBF8
EBE8
EBFA
EBEA
51
E375
9A
EB9A
EBF4
EBE4
EBF6
EBE6
C00
E500
E39F
EBF7
EBE7
E371
E376
E3C0
B926
E727
B313
B373
23
B303
33
B913
B903
13
B7
EB2F
B343
B363
68
ED24
ED04
B304
B324
B3D4
B3C1
28
B345
B345
25
B3DD
ED65
78
B344
B344
35
B3D5
38
B346
B346
B366
ED64
B2BD
Class
&
Notes
¤ c IA
¤ c IA
¤ c IA
¤ c IA
¤
¤ GE
¤
¤ LD
¤ c IA
¤ c IA
¤ c IA
¤ c IA
N3
pc
LT
¤ c IA
¤ c IA
LD
LD
HW
EI
¤ c VF
¤c
¤ FS
¤c
¤c
¤c
cN
cN
c
p
pN
¤c
¤c
¤
¤
¤
¤
¤
¤ TF
¤ FG
¤
¤
¤F
¤
¤ TF
¤ LD
¤
¤
¤F
¤
¤ TF
¤
¤
¤F
¤
¤ LD
¤ XF
13
SA22-7871-08.book Page 14 Thursday, February 19, 2015 3:46 PM
Mnemonic
LFH
LFHAT
LFPC
LG
LGAT
LGB
LGBR
LGDR
LGF
LGFI
LGFR
LGFRL
LGH
LGHI
LGHR
LGHRL
LGR
LGRL
LH
LHH
LHI
LHR
LHRL
LHY
LLC
LLCH
LLCR
LLGC
LLGCR
LLGF
LLGFAT
LLGFR
LLGFRL
LLGH
LLGHR
LLGHRL
Name
Load High (32)
Load and Trap (32H32)
Load FPC
Load (64)
Load and Trap (64)
Load Byte (648)
Load Byte (648)
Load GR from FPR (64L)
Load (6432)
Load Immediate (6432)
Load (6432)
Load Relative Long (6432)
Load Halfword (6416)
Load Halfword Immediate (6416)
Load Halfword (6416)
Load Halfword Relative Long (6416)
Load (64)
Load Relative Long (64)
Load Halfword (3216)
Load Halfword High (3216)
Load Halfword Immediate (3216)
Load Halfword (3216)
Load Halfword Relative Long (3216)
Load Halfword (3216)
Load Logical Character (328)
Load Logical Character High (328)
Load Logical Character (328)
Load Logical Character (648)
Load Logical Character (648)
Load Logical (6432)
Load and Trap (6432)
Load Logical (6432)
Load Logical Relative Long (6432)
Load Logical Halfword (6416)
Load Logical Halfword (6416)
Load Logical Halfword Relative Long
(6416)
LLGT
R1,D2(X2,B2)
Load Logical Thirty One Bits (6431)
LLGTAT R1,D2(X2,B2)
Load Logical Thirty One Bits and Trap
(6431)
Load Logical Thirty One Bits (6431)
LLGTR R1,R2
LLH
R1,D2(X2,B2)
Load Logical Halfword (3216)
LLHH
R1,D2(X2,B2)
Load Logical Halfword High (3216)
LLHR
R1,R2
Load Logical Halfword (3216)
Load Logical Halfword Relative Long
LLHRL R1,RI2
(3216)
LLIHF
R1,I2
Load Logical Immediate (high)
Load Logical Immediate (high high)
LLIHH
R1,I2
LLIHL
R1,I2
Load Logical Immediate (high low)
Load Logical Immediate (low)
LLILF
R1,I2
LLILH
R1,I2
Load Logical Immediate (low high)
LLILL
R1,I2
Load Logical Immediate (low low)
LLZRGF R1,D2(X2,B2)
Load Logical and Zero Rightmost Byte (32)
LM
R1,R3,D2(B2)
Load Multiple (32)
LMD
R1,R3,D2(B2),D4(B4) Load Multiple Disjoint (6432&32)
LMG
R1,R3,D2(B2)
Load Multiple (64)
LMH
R1,R3,D2(B2)
Load Multiple High
LMY
R1,R3,D2(B2)
Load Multiple (32)
LNDBR R1,R2
Load Negative (LB)
Load Negative (L)
LNDFR R1,R2
LNDR
R1,R2
Load Negative (LH)
14
Operands
R1,D2(X2,B2)
R1,D2(X2,B2)
D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,D2(X2,B2)
R1,I2
R1,R2
R1,RI2
R1,D2(X2,B2)
R1,I2
R1,R2
R1,RI2
R1,R2
R1,RI2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,I2
R1,R2
R1,RI2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,RI2
R1,D2(X2,B2)
R1,R2
R1,RI2
z/Architecture Reference Summary
Format
RXY-a
RXY-a
S
RXY-a
RXY-a
RXY-a
RRE
RRE
RXY-a
RIL-a
RRE
RIL-b
RXY-a
RI-a
RRE
RIL-b
RRE
RIL-b
RX-a
RXY-a
RI-a
RRE
RIL-b
RXY-a
RXY-a
RXY-a
RRE
RXY-a
RRE
RXY-a
RXY-a
RRE
RIL-b
RXY-a
RRE
RIL-b
Opcode
E3CA
E3C8
B29D
E304
E385
E377
B906
B3CD
E314
C01
B914
C4C
E315
A79
B907
C44
B904
C48
48
E3C4
A78
B927
C45
E378
E394
E3C2
B994
E390
B984
E316
E39D
B916
C4E
E391
B985
C46
Class
&
Notes
HW
LT
¤
N
LT
LD
EI
¤ FG
N
EI
N
GE
N
N
EI
GE
N
GE
HW
EI
GE
LD
EI
HW
EI
N
EI
N
LT
N
GE
N
EI
GE
RXY-a E317 N
RXY-a E39C LT
RRE
RXY-a
RXY-a
RRE
RIL-b
B917
E395
E3C6
B995
C42
N
EI
HW
EI
GE
RIL-a
RI-a
RI-a
RIL-a
RI-a
RI-a
RXY-a
RS-a
SS-e
RSY-a
RSY-a
RSY-a
RRE
RRE
RR
C0E
A5C
A5D
C0F
A5E
A5F
E33A
98
EF
EB04
EB96
EB98
B311
B371
21
EI
N
N
EI
N
N
LZ
¤N
N
N
LD
¤c
¤ FS
¤c
SA22-7871-08.book Page 15 Thursday, February 19, 2015 3:46 PM
Mnemonic
LNEBR
LNER
LNGFR
LNGR
LNR
LNXBR
LNXR
LOC
LOCFH
LOCFHR
LOCG
LOCGHI
Operands
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,D2(B2),M3
R1,D2(B2),M3
R1,R2,M3
R1,D2(B2),M3
R1,I2,M3
LOCGR R1,R2,M3
LOCHHI R1,I2,M3
LOCHI
R1,I2,M3
LOCR
LPD
LPDBR
LPDFR
LPDG
LPDR
LPEBR
LPER
LPGFR
LPGR
LPQ
LPR
LPSW
LPSWE
LPTEA
LPXBR
LPXR
LR
LRA
LRAG
LRAY
LRDR
LRER
LRL
LRV
LRVG
LRVGR
LRVH
LRVR
LT
LTDBR
LTDR
LTDTR
LTEBR
LTER
LTG
LTGF
LTGFR
LTGR
LTR
LTXBR
LTXR
LTXTR
R1,R2,M3
R3,D1(B1),D2(B2)
R1,R2
R1,R2
R3,D1(B1),D2(B2)
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,D2(X2,B2)
R1,R2
D2(B2)
D2(B2)
R1,R3,R2,M4
R1,R2
R1,R2
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,RI2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
Name
Load Negative (SB)
Load Negative (SH)
Load Negative (6432)
Load Negative (64)
Load Negative (32)
Load Negative (EB)
Load Negative (EH)
Load on Condition (32)
Load High on Condition (32)
Load High on Condition (32)
Load on Condition (64)
Load Halfword Immediate on Condition
(6416)
Load on Condition (64)
Load Halfword High Immediate on Condition (3216)
Load Halfword Immediate on Condition
(3216)
Load on Condition (32)
Load Pair Disjoint (32)
Load Positive (LB)
Load Positive (L)
Load Pair Disjoint (64)
Load Positive (LH)
Load Positive (SB)
Load Positive (SH)
Load Positive (6432)
Load Positive (64)
Load Pair from Quadword (64&64128)
Load Positive (32)
Load PSW
Load PSW Extended
Load Page-Table-Entry Address
Load Positive (EB)
Load Positive (EH)
Load (32)
Load Real Address (32)
Load Real Address (64)
Load Real Address (32)
Load Rounded (LHEH)
Load Rounded (SHLH)
Load Relative Long (32)
Load Reversed (32)
Load Reversed (64)
Load Reversed (64)
Load Reversed (16)
Load Reversed (32)
Load and Test (32)
Load and Test (LB)
Load and Test (LH)
Load and Test (LD)
Load and Test (SB)
Load and Test (SH)
Load and Test (64)
Load And Test (6432)
Load and Test (6432)
Load and Test (64)
Load and Test (32)
Load and Test (EB)
Load and Test (EH)
Load and Test (ED)
Format
RRE
RR
RRE
RRE
RR
RRE
RRE
RSY-b
RSY-b
RRF-c
RSY-b
RIE-g
Opcode
B301
31
B911
B901
11
B341
B361
EBF2
EBE0
B9E0
EBE2
EC46
Class
&
Notes
¤c
¤c
cN
cN
c
¤c
¤c
L1
L2
L2
L1
L2
RRF-c B9E2 L1
RIE-g EC4E L2
RIE-g EC42 L2
RRF-c
SSF
RRE
RRE
SSF
RR
RRE
RR
RRE
RRE
RXY-a
RR
S
S
RRF-b
RRE
RRE
RR
RX-a
RXY-a
RXY-a
RR
RR
RIL-b
RXY-a
RXY-a
RRE
RXY-a
RRE
RXY-a
RRE
RR
RRE
RRE
RR
RXY-a
RXY-a
RRE
RRE
RR
RRE
RRE
RRE
B9F2
C84
B310
B370
C85
20
B300
30
B910
B900
E38F
10
82
B2B2
B9AA
B340
B360
18
B1
E303
E313
25
35
C4D
E31E
E30F
B90F
E31F
B91F
E312
B312
22
B3D6
B302
32
E302
E332
B912
B902
12
B342
B362
B3DE
L1
c IA
¤c
¤ FS
c IA
¤c
¤c
¤c
cN
cN
¤N
c
pn
pnN
p c D2
¤c
¤c
pc
pcN
p c LD
¤
¤
GE
N3
N
N
N3
N3
c EI
¤c
¤c
¤ c TF
¤c
¤c
c EI
c GE
cN
cN
c
¤c
¤c
¤ c TF
15
SA22-7871-08.book Page 16 Thursday, February 19, 2015 3:46 PM
Mnemonic
LURA
LURAG
LXD
LXDB
LXDBR
LXDR
LXDTR
LXE
LXEB
LXEBR
LXER
LXR
LY
LZDR
LZER
LZRF
LZRG
LZXR
M
MAD
MADB
MADBR
MADR
MAE
MAEB
MAEBR
MAER
MAY
MAYH
MAYHR
MAYL
MAYLR
MAYR
MC
MD
MDB
MDBR
MDE
MDEB
MDEBR
MDER
MDR
MDTR
MDTRA
ME
MEE
MEEB
MEEBR
MEER
MER
MFY
MGHI
MH
MHI
MHY
ML
MLG
MLGR
MLR
MP
16
Operands
R1,R2
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2,M4
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,D2(X2,B2)
R1
R1
R1,D2(X2,B2)
R1,D2(X2,B2)
R1
R1,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,R2
R1,R3,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,R2
R1,R3,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,R2
D1(B1),I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2,R3
R1,R2,R3,M4
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,D2(X2,B2)
R1,I2
R1,D2(X2,B2)
R1,I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
D1(L1,B1),D2(L2,B2)
Name
Load Using Real Address (32)
Load Using Real Address (64)
Load Lengthened (EHLH)
Load Lengthened (EBLB)
Load Lengthened (EBLB)
Load Lengthened (EHLH)
Load Lengthened (EDLD)
Load Lengthened (EHSH)
Load Lengthened (EBSB)
Load Lengthened (EBSB)
Load Lengthened (EHSH)
Load (E)
Load (32)
Load Zero (L)
Load Zero (S)
Load and Zero Rightmost Byte (32)
Load and Zero Rightmost Byte (64)
Load Zero (E)
Multiply (6432)
Multiply and Add (LH)
Multiply and Add (LB)
Multiply and Add (LB)
Multiply and Add (LH)
Multiply and Add (SH)
Multiply and Add (SB)
Multiply and Add (SB)
Multiply and Add (SH)
Multiply and Add Unnormalized (EHLH)
Multiply and Add Unnormalized (EHHLH)
Multiply and Add Unnormalized (EHHLH)
Multiply and Add Unnormalized (EHLLH)
Multiply and Add Unnormalized (EHLLH)
Multiply and Add Unnormalized (EHLH)
Monitor Call
Multiply (LH)
Multiply (LB)
Multiply (LB)
Multiply (LHSH)
Multiply (LBSB)
Multiply (LBSB)
Multiply (LHSH)
Multiply (LH)
Multiply (LD)
Multiply (LD)
Multiply (LHSH)
Multiply (SH)
Multiply (SB)
Multiply (SB)
Multiply (SH)
Multiply (LHSH)
Multiply (6432)
Multiply Halfword Immediate (6416)
Multiply Halfword (3216)
Multiply Halfword Immediate (3216)
Multiply Halfword (6416)
Multiply Logical (6432)
Multiply Logical (12864)
Multiply Logical (12864)
Multiply Logical (6432)
Multiply Decimal
z/Architecture Reference Summary
Format
RRE
RRE
RXE
RXE
RRE
RRE
RRF-d
RXE
RXE
RRE
RRE
RRE
RXY-a
RRE
RRE
RXY-a
RXY-a
RRE
RX-a
RXF
RXF
RRD
RRD
RXF
RXF
RRD
RRD
RXF
RXF
RRD
RXF
RRD
RRD
SI
RX-a
RXE
RRE
RX-a
RXE
RRE
RR
RR
RRF-a
RRF-a
RX-a
RXE
RXE
RRE
RRE
RR
RXY-a
RI-a
RX-a
RI-a
RXY-a
RXY-a
RXY-a
RRE
RRE
SS-b
Opcode
B24B
B905
ED25
ED05
B305
B325
B3DC
ED26
ED06
B306
B326
B365
E358
B375
B374
E33B
E32A
B376
5C
ED3E
ED1E
B31E
B33E
ED2E
ED0E
B30E
B32E
ED3A
ED3C
B33C
ED38
B338
B33A
AF
6C
ED1C
B31C
7C
ED0C
B30C
3C
2C
B3D0
B3D0
7C
ED37
ED17
B317
B337
3C
E35C
A7D
4C
A7C
E37C
E396
E386
B986
B996
FC
Class
&
Notes
p
pN
¤
¤
¤
¤
¤ TF
¤
¤
¤
¤
¤
LD
¤
¤
LZ
LZ
¤
¤ HM
¤
¤
¤ HM
¤ HM
¤
¤
¤ HM
¤ UE
¤ UE
¤ UE
¤ UE
¤ UE
¤ UE
¤
¤
¤
¤
¤
¤
¤
¤
¤
¤ TF
¤F
¤
¤
¤
¤
¤
¤
GE
N
GE
N3
N
N
N3
¤
SA22-7871-08.book Page 17 Thursday, February 19, 2015 3:46 PM
Mnemonic
MR
MS
MSCH
MSD
MSDB
MSDBR
MSDR
MSE
MSEB
MSEBR
MSER
MSFI
MSG
MSGF
MSGFI
MSGFR
MSGR
MSR
MSTA
MSY
MVC
MVCDK
MVCIN
MVCK
MVCL
MVCLE
MVCLU
MVCOS
MVCP
MVCS
MVCSK
MVGHI
MVHHI
MVHI
MVI
MVIY
MVN
MVO
MVPG
MVST
MVZ
MXBR
MXD
MXDB
MXDBR
MXDR
MXR
MXTR
MXTRA
MY
MYH
MYHR
MYL
MYLR
MYR
N
NC
NG
NGR
NGRK
Operands
R1,R2
R1,D2(X2,B2)
D2(B2)
R1,R3,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,R2
R1,R3,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,R2
R1,I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,I2
R1,R2
R1,R2
R1,R2
R1
R1,D2(X2,B2)
D1(L,B1),D2(B2)
D1(B1),D2(B2)
D1(L,B1),D2(B2)
D1(R1,B1),D2(B2),R3
R1,R2
R1,R3,D2(B2)
R1,R3,D2(B2)
D1(B1),D2(B2),R3
D1(R1,B1),D2(B2),R3
D1(R1,B1),D2(B2),R3
D1(B1),D2(B2)
D1(B1),I2
D1(B1),I2
D1(B1),I2
D1(B1),I2
D1(B1),I2
D1(L,B1),D2(B2)
D1(L1,B1),D2(L2,B2)
R1,R2
R1,R2
D1(L,B1),D2(B2)
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2,R3
R1,R2,R3,M4
R1,R3,D2(X2,B2)
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,D2(X2,B2)
R1,R3,R2
R1,R3,R2
R1,D2(X2,B2)
D1(L,B1),D2(B2)
R1,D2(X2,B2)
R1,R2
R1,R2,R3
Name
Multiply (6432)
Multiply Single (32)
Modify Subchannel
Multiply and Subtract (LH)
Multiply and Subtract (LB)
Multiply and Subtract (LB)
Multiply and Subtract (LH)
Multiply and Subtract (SH)
Multiply and Subtract (SB)
Multiply and Subtract (SB)
Multiply and Subtract (SH)
Multiply Single Immediate (32)
Multiply Single (64)
Multiply Single (6432)
Multiply Single Immediate (6432)
Multiply Single (6432)
Multiply Single (64)
Multiply Single (32)
Modify Stacked State
Multiply Single (32)
Move (character)
Move with Destination Key
Move Inverse
Move with Key
Move Long
Move Long Extended
Move Long Unicode
Move with Optional Specifications
Move to Primary
Move to Secondary
Move with Source Key
Move (6416)
Move (1616)
Move (3216)
Move Immediate
Move Immediate
Move Numerics
Move with Offset
Move Page
Move String
Move Zones
Multiply (EB)
Multiply (EHLH)
Multiply (EBLB)
Multiply (EBLB)
Multiply (EHLH)
Multiply (EH)
Multiply (ED)
Multiply (ED)
Multiply Unnormalized (EHLH)
Multiply Unnormalized (EHHLH)
Multiply Unnormalized (EHHLH)
Multiply Unnormalized (EHLLH)
Multiply Unnormalized (EHLLH)
Multiply Unnormalized (EHLH)
AND (32)
AND (character)
AND (64)
AND (64)
AND (64)
Format
RR
RX-a
S
RXF
RXF
RRD
RRD
RXF
RXF
RRD
RRD
RIL-a
RXY-a
RXY-a
RIL-a
RRE
RRE
RRE
RRE
RXY-a
SS-a
SSE
SS-a
SS-d
RR
RS-a
RSY-a
SSF
SS-d
SS-d
SSE
SIL
SIL
SIL
SI
SIY
SS-a
SS-b
RRE
RRE
SS-a
RRE
RX-a
RXE
RRE
RR
RR
RRF-a
RRF-a
RXF
RXF
RRD
RXF
RRD
RRD
RX-a
SS-a
RXY-a
RRE
RRF-a
Opcode
1C
71
B232
ED3F
ED1F
B31F
B33F
ED2F
ED0F
B30F
B32F
C21
E30C
E31C
C20
B91C
B90C
B252
B247
E351
D2
E50F
E8
D9
0E
A8
EB8E
C80
DA
DB
E50E
E548
E544
E54C
92
EB52
D1
F1
B254
B255
D3
B34C
67
ED07
B307
27
26
B3D8
B3D8
ED3B
ED3D
B33D
ED39
B339
B33B
54
D4
E380
B980
B9E4
Class
&
Notes
pc
¤ HM
¤
¤
¤ HM
¤ HM
¤
¤
¤ HM
GE
N
N
GE
N
N
¤
LD
¤
q
¤
qc
i¤c
¤c
¤ c E2
q c MO
qc
qc
q
GE
GE
GE
LD
¤
¤
qc
¤c
¤
¤
¤
¤
¤
¤
¤
¤ TF
¤F
¤ UE
¤ UE
¤ UE
¤ UE
¤ UE
¤ UE
c
¤c
cN
cN
c DO
17
SA22-7871-08.book Page 18 Thursday, February 19, 2015 3:46 PM
Mnemonic
NI
NIAI
NIHF
NIHH
NIHL
NILF
NILH
NILL
NIY
NR
NRK
NTSTG
NY
O
OC
OG
OGR
OGRK
OI
OIHF
OIHH
OIHL
OILF
OILH
OILL
OIY
OR
ORK
OY
PACK
PALB
PC
PCC
PCKMO
PFD
PFDRL
PFMF
PFPO
PGIN
PGOUT
PKA
PKU
PLO
POPCNT
PPA
PPNO
PR
PT
PTF
PTFF
PTI
PTLB
QADTR
QAXTR
RCHP
RISBG
RISBGN
RISBHG
RISBLG
RLL
RLLG
18
ForOperands
Name
mat
D1(B1),I2
AND Immediate
SI
I1,I2
Next Instruction Access Intent
IE
R1,I2
AND Immediate (high)
RIL-a
AND Immediate (high high)
RI-a
R1,I2
R1,I2
AND Immediate (high low)
RI-a
R1,I2
AND Immediate (low)
RIL-a
R1,I2
AND Immediate (low high)
RI-a
R1,I2
AND Immediate (low low)
RI-a
AND Immediate
SIY
D1(B1),I2
R1,R2
AND (32)
RR
R1,R2,R3
AND (32)
RRF-a
R1,D2(X2,B2)
Nontransactional Store (64)
RXY-a
AND (32)
RXY-a
R1,D2(X2,B2)
R1,D2(X2,B2)
OR (32)
RX-a
OR (character)
SS-a
D1(L,B1),D2(B2)
R1,D2(X2,B2)
OR (64)
RXY-a
R1,R2
OR (64)
RRE
R1,R2,R3
OR (64)
RRF-a
D1(B1),I2
OR Immediate
SI
R1,I2
OR Immediate (high)
RIL-a
R1,I2
OR Immediate (high high)
RI-a
R1,I2
OR Immediate (high low)
RI-a
R1,I2
OR Immediate (low)
RIL-a
R1,I2
OR Immediate (low high)
RI-a
R1,I2
OR Immediate (low low)
RI-a
D1(B1),I2
OR Immediate
SIY
R1,R2
OR (32)
RR
R1,R2,R3
OR (32)
RRF-a
R1,D2(X2,B2)
OR (32)
RXY-a
D1(L1,B1),D2(L2,B2) Pack
SS-b
Purge ALB
RRE
D2(B2)
Program Call
S
Perform Cryptographic Computation
RRE
Perform Crypto. Key Mgmt. Operations
RRE
M1,D2(X2,B2)
Prefetch Data
RXY-b
M1,RI2
Prefetch Data Relative Long
RIL-c
R1,R2
Perform Frame Management Function
RRE
Perform Floating-Point Operation
E
R1,R2
Page In
RRE
R1,R2
Page Out
RRE
SS-f
D1(B1),D2(L2,B2) Pack ASCII
D1(B1),D2(L2,B2) Pack Unicode
SS-f
R1,D2(B2),R3,D4(B4) Perform Locked Operation
SS-e
R1,R2
Population Count
RRE
Perform Processor Assist
RRF-c
R1,R2,M3
Perform Pseudorandom Number Operation RRE
R1,R2
Program Return
E
R1,R2
Program Transfer
RRE
R1
Perform Topology Function
RRE
Perform Timing-Facility Function
E
R1,R2
Program Transfer with Instance
RRE
Purge TLB
S
R1,R3,R2,M4
Quantize (LD)
RRF-b
R1,R3,R2,M4
Quantize (ED)
RRF-b
Reset Channel Path
S
R1,R2,I3,I4[,I5]
Rotate then Insert Selected Bits (64)
RIE-f
R1,R2,I3,I4[,I5]
Rotate then Insert Selected Bits (64)
RIE-f
R1,I2,I3,I4[,I5]
Rotate then Insert Selected Bits High (32) RIE-f
R1,I2,I3,I4[,I5]
Rotate then Insert Selected Bits Low (32) RIE-f
R1,R3,D2(B2)
Rotate Left Single Logical (32)
RSY-a
R1,R3,D2(B2)
Rotate Left Single Logical (64)
RSY-a
z/Architecture Reference Summary
Opcode
94
B2FA
C0A
A54
A55
C0B
A56
A57
EB54
14
B9F4
E325
E354
56
D6
E381
B981
B9E6
96
C0C
A58
A59
C0D
A5A
A5B
EB56
16
B9F6
E356
F2
B248
B218
B92C
B928
E336
C62
B9AF
010A
B22E
B22F
E9
E1
EE
B9E1
B2E8
B93C
0101
B228
B9A2
0104
B99E
B20D
B3F5
B3FD
B23B
EC55
EC59
EC5D
EC51
EB1D
EB1C
Class
&
Notes
c
EH
c EI
cN
cN
c EI
cN
cN
c LD
c
c DO
¤ TX
c LD
c
¤c
cN
cN
c DO
c
c EI
cN
cN
c EI
cN
cN
c LD
c
c DO
c LD
¤
p
q
¤ c M4
M3
¤ GE
¤ GE
p ED1
¤ PF
p c ES
p c ES
¤ E2
¤ E2
¤c
c PK
PA
M5
qn
q
c p CT
qc
q RA
p
¤ TF
¤ TF
pc
c GE
MI
HW
HW
N3
N
SA22-7871-08.book Page 19 Thursday, February 19, 2015 3:46 PM
Mnemonic
RNSBG
ROSBG
RP
RRBE
RRBM
RRDTR
RRXTR
RSCH
RXSBG
S
SAC
SACF
SAL
SAM24
SAM31
SAM64
SAR
SCHM
SCK
SCKC
SCKPF
SD
SDB
SDBR
SDR
SDTR
SDTRA
SE
SEB
SEBR
SER
SFASR
SFPC
SG
SGF
SGFR
SGR
SGRK
SH
SHHHR
SHHLR
SHY
SIE
SIGP
SL
SLA
SLAG
SLAK
SLB
SLBG
SLBGR
SLBR
SLDA
SLDL
SLDT
SLFI
SLG
SLGF
SLGFI
SLGFR
Operands
R1,R2,I3,I4[,I5]
R1,R2,I3,I4[,I5]
D2(B2)
R1,R2
R1,R2
R1,R3,R2,M4
R1,R3,R2,M4
R1,R2,I3,I4[,I5]
R1,D2(X2,B2)
D2(B2)
D2(B2)
R1,R2
D2(B2)
D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2,R3
R1,R2,R3,M4
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1
R1
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2,R3
R1,D2(X2,B2)
R1,R2,R3
R1,R2,R3
R1,D2(X2,B2)
D2(B2)
R1,R3,D2(B2)
R1,D2(X2,B2)
R1,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,D2(B2)
R1,D2(B2)
R1,R3,D2(X2,B2)
R1,I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,I2
R1,R2
Name
Rotate then AND Selected Bits (64)
Rotate then OR Selected Bits (64)
Resume Program
Reset Reference Bit Extended
Reset Reference Bits Multiple
Reround (LD)
Reround (ED)
Resume Subchannel
Rotate then Exclusive OR Selected Bits
(64)
Subtract (32)
Set Address Space Control
Set Address Space Control Fast
Set Address Limit
Set Addressing Mode (24)
Set Addressing Mode (31)
Set Addressing Mode (64)
Set Access
Set Channel Monitor
Set Clock
Set Clock Comparator
Set Clock Programmable Field
Subtract Normalized (LH)
Subtract (LB)
Subtract (LB)
Subtract Normalized (LH)
Subtract (LD)
Subtract (LD)
Subtract Normalized (SH)
Subtract (SB)
Subtract (SB)
Subtract Normalized (SH)
Set FPC and Signal
Set FPC
Subtract (64)
Subtract (6432)
Subtract (6432)
Subtract (64)
Subtract (64)
Subtract Halfword (3216)
Subtract High (32)
Subtract High (32)
Subtract Halfword (3216)
Start Interpretive Execution
Signal Processor
Subtract Logical (32)
Shift Left Single (32)
Shift Left Single (64)
Shift Left Single (32)
Subtract Logical with Borrow (32)
Subtract Logical with Borrow (64)
Subtract Logical with Borrow (64)
Subtract Logical with Borrow (32)
Shift Left Double (64)
Shift Left Double Logical (64)
Shift Significand Left (LD)
Subtract Logical Immediate (32)
Subtract Logical (64)
Subtract Logical (6432)
Subtract Logical Immediate (6432)
Subtract Logical (6432)
Format
RIE-f
RIE-f
S
RRE
RRE
RRF-b
RRF-b
S
RIE-f
Opcode
EC54
EC56
B277
B22A
B9AE
B3F7
B3FF
B238
EC57
RX-a
S
S
S
E
E
E
RRE
S
S
S
E
RX-a
RXE
RRE
RR
RRF-a
RRF-a
RX-a
RXE
RRE
RR
RRE
RRE
RXY-a
RXY-a
RRE
RRE
RRF-a
RX-a
RRF-a
RRF-a
RXY-a
S
RS-a
RX-a
RS-a
RSY-a
RSY-a
RXY-a
RXY-a
RRE
RRE
RS-a
RS-a
RXF
RIL-a
RXY-a
RXY-a
RIL-a
RRE
5B
B219
B279
B237
010C
010D
010E
B24E
B23C
B204
B206
0107
6B
ED1B
B31B
2B
B3D3
B3D3
7B
ED0B
B30B
3B
B385
B384
E309
E319
B919
B909
B9E9
4B
B9C9
B9D9
E37B
B214
AE
5F
8B
EB0B
EBDD
E399
E389
B989
B999
8F
8D
ED40
C25
E30B
E31B
C24
B91B
Class
&
Notes
c GE
c GE
qn
pc
p RB
¤ TF
¤ TF
pc
c GE
c
q
q
p
¤ N3
¤ N3
¤N
¤
p
pc
p
p
¤c
¤c
¤c
¤c
¤ c TF
¤cF
¤c
¤c
¤c
¤c
¤ XF
¤
cN
cN
cN
cN
c DO
c
c HW
c HW
c LD
ip
pc
c
c
cN
c DO
c N3
cN
cN
c N3
c
¤ TF
c EI
cN
cN
c EI
cN
19
SA22-7871-08.book Page 20 Thursday, February 19, 2015 3:46 PM
Mnemonic
SLGR
SLGRK
SLHHHR
SLHHLR
SLL
SLLG
SLLK
SLR
SLRK
SLXT
SLY
SP
SPKA
SPM
SPT
SPX
SQD
SQDB
SQDBR
SQDR
SQE
SQEB
SQEBR
SQER
SQXBR
SQXR
SR
SRA
SRAG
SRAK
SRDA
SRDL
SRDT
SRK
SRL
SRLG
SRLK
SRNM
SRNMB
SRNMT
SRP
SRST
SRSTU
SRXT
SSAIR
SSAR
SSCH
SSKE
SSM
ST
STAM
STAMY
STAP
STC
STCH
STCK
STCKC
STCKE
STCKF
STCM
20
Operands
R1,R2
R1,R2,R3
R1,R2,R3
R1,R2,R3
R1,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R2
R1,R2,R3
R1,R3,D2(X2,B2)
R1,D2(X2,B2)
D1(L1,B1),D2(L2,B2)
D2(B2)
R1
D2(B2)
D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
R1,R2
R1,R2
R1,R2
R1,R2
R1,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,D2(B2)
R1,D2(B2)
R1,R3,D2(X2,B2)
R1,R2,R3
R1,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
D2(B2)
D2(B2)
D2(B2)
D1(L1,B1),D2(B2),I3
R1,R2
R1,R2
R1,R3,D2(X2,B2)
R1
R1
D2(B2)
R1,R2[,M3]
D2(B2)
R1,D2(X2,B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
D2(B2)
D2(B2)
D2(B2)
D2(B2)
R1,M3,D2(B2)
Name
Subtract Logical (64)
Subtract Logical (64)
Subtract Logical High (32)
Subtract Logical High (32)
Shift Left Single Logical (32)
Shift Left Single Logical (64)
Shift Left Single Logical (32)
Subtract Logical (32)
Subtract Logical (32)
Shift Significand Left (ED)
Subtract Logical (32)
Subtract Decimal
Set PSW Key from Address
Set Program Mask
Set CPU Timer
Set Prefix
Square Root (LH)
Square Root (LB)
Square Root (LB)
Square Root (LH)
Square Root (SH)
Square Root (SB)
Square Root (SB)
Square Root (SH)
Square Root (EB)
Square Root (EH)
Subtract (32)
Shift Right Single (32)
Shift Right Single (64)
Shift Right Single (32)
Shift Right Double (64)
Shift Right Double Logical (64)
Shift Significand Right (LD)
Subtract (32)
Shift Right Single Logical (32)
Shift Right Single Logical (64)
Shift Right Single Logical (32)
Set BFP Rounding Mode (2 bit)
Set BFP Rounding Mode (3 bit)
Set DFP Rounding Mode
Shift and Round Decimal
Search String
Search String Unicode
Shift Significand Right (ED)
Set Secondary ASN with Instance
Set Secondary ASN
Start Subchannel
Set Storage Key Extended
Set System Mask
Store (32)
Store Access Multiple
Store Access Multiple
Store CPU Address
Store Character
Store Character High (8)
Store Clock
Store Clock Comparator
Store Clock Extended
Store Clock Fast
Store Characters under Mask (low)
z/Architecture Reference Summary
Format
RRE
RRF-a
RRF-a
RRF-a
RS-a
RSY-a
RSY-a
RR
RRF-a
RXF
RXY-a
SS-b
S
RR
S
S
RXE
RXE
RRE
RRE
RXE
RXE
RRE
RRE
RRE
RRE
RR
RS-a
RSY-a
RSY-a
RS-a
RS-a
RXF
RRF-a
RS-a
RSY-a
RSY-a
S
S
S
SS-c
RRE
RRE
RXF
RRE
RRE
S
RRF-d
S
RX-a
RS-a
RSY-a
S
RX-a
RXY-a
S
S
S
S
RS-b
Opcode
B90B
B9EB
B9CB
B9DB
89
EB0D
EBDF
1F
B9FB
ED48
E35F
FB
B20A
04
B208
B210
ED35
ED15
B315
B244
ED34
ED14
B314
B245
B316
B336
1B
8A
EB0A
EBDC
8E
8C
ED41
B9F9
88
EB0C
EBDE
B299
B2B8
B2B9
F0
B25E
B9BE
ED49
B99F
B225
B233
B22B
80
50
9B
EB9B
B212
42
E3C3
B205
B207
B278
B27C
BE
Class
&
Notes
cN
c DO
c HW
c HW
N
DO
c
c DO
¤ TF
c LD
¤c
q
n
p
p
¤
¤
¤
¤
¤
¤
¤
¤
¤
¤
c
c
cN
c DO
c
¤ TF
c DO
N
DO
¤
¤F
¤ TR
¤c
¤c
¤ c E3
¤ TF
¤ RA
¤
pc
pc
p
LD
p
HW
¤c
p
¤c
¤ c SC
SA22-7871-08.book Page 21 Thursday, February 19, 2015 3:46 PM
Mnemonic
STCMH
STCMY
STCPS
STCRW
STCTG
STCTL
STCY
STD
STDY
STE
STEY
STFH
STFL
STFLE
STFPC
STG
STGRL
STH
STHH
STHRL
STHY
STIDP
STM
STMG
STMH
STMY
STNSM
STOC
STOCFH
STOCG
STOSM
STPQ
STPT
STPX
STRAG
STRL
STRV
STRVG
STRVH
STSCH
STSI
STURA
STURG
STY
SU
SUR
SVC
SW
SWR
SXBR
SXR
SXTR
SXTRA
SY
TABORT
TAM
TAR
TB
TBDR
TBEDR
Operands
R1,M3,D2(B2)
R1,M3,D2(B2)
D2(B2)
D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
D2(B2)
D2(B2)
D2(B2)
R1,D2(X2,B2)
R1,RI2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,RI2
R1,D2(X2,B2)
D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
R1,R3,D2(B2)
D1(B1),I2
R1,D2(B2),M3
R1,D2(B2),M3
R1,D2(B2),M3
D1(B1),I2
R1,D2(X2,B2)
D2(B2)
D2(B2)
D1(B1),D2(B2)
R1,RI2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
D2(B2)
D2(B2)
R1,R2
R1,R2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,R2
I
R1,D2(X2,B2)
R1,R2
R1,D2
R1,D2
R1,R2,R3
R1,R2,R3,M4
R1,D2(X2,B2)
D2(B2)
R1,R2
R1,R2
R1,M3,R2
R1,M3,R2
Name
Store Characters under Mask (high)
Store Characters under Mask (low)
Store Channel Path Status
Store Channel Report Word
Store Control (64)
Store Control (32)
Store Character
Store (L)
Store (L)
Store (S)
Store (S)
Store High (32)
Store Facility List
Store Facility List Extended
Store FPC
Store (64)
Store Relative Long (64)
Store Halfword (16)
Store Halfword High (16)
Store Halfword Relative Long (16)
Store Halfword (16)
Store CPU ID
Store Multiple (32)
Store Multiple (64)
Store Multiple High (32)
Store Multiple (32)
Store Then And System Mask
Store on Condition (32)
Store High on Condition (32)
Store on Condition (64)
Store Then Or System Mask
Store Pair to Quadword (64,64128)
Store CPU Timer
Store Prefix
Store Real Address (64)
Store Relative Long (32)
Store Reversed (32)
Store Reversed (64)
Store Reversed (16)
Store Subchannel
Store System Information
Store Using Real Address (32)
Store Using Real Address (64)
Store (32)
Subtract Unnormalized (SH)
Subtract Unnormalized (SH)
Supervisor Call
Subtract Unnormalized (LH)
Subtract Unnormalized (LH)
Subtract (EB)
Subtract Normalized (EH)
Subtract (ED)
Subtract (ED)
Subtract (32)
Transaction Abort
Test Addressing Mode
Test Access
Test Block
Convert HFP to BFP (LBLH)
Convert HFP to BFP (SBLH)
Format
RSY-b
RSY-b
S
S
RSY-a
RS-a
RXY-a
RX-a
RXY-a
RX-a
RXY-a
RXY-a
S
S
S
RXY-a
RIL-b
RX-a
RXY-a
RIL-b
RXY-a
S
RS-a
RSY-a
RSY-a
RSY-a
SI
RSY-b
RSY-b
RSY-b
SI
RXY-a
S
S
SSE
RIL-b
RXY-a
RXY-a
RXY-a
S
S
RRE
RRE
RXY-a
RX-a
RR
I
RX-a
RR
RRE
RR
RRF-a
RRF-a
RXY-a
S
E
RRE
RRE
RRF-e
RRF-e
Opcode
EB2C
EB2D
B23A
B239
EB25
B6
E372
60
ED67
70
ED66
E3CB
B2B1
B2B0
B29C
E324
C4B
40
E3C7
C47
E370
B202
90
EB24
EB26
EB90
AC
EBF3
EBE1
EBE3
AD
E38E
B209
B211
E502
C4F
E33E
E32F
E33F
B234
B27D
B246
B925
E350
7F
3F
0A
6F
2F
B34B
37
B3DB
B3DB
E35B
B2FC
010B
B24C
B22C
B351
B350
Class
&
Notes
¤N
LD
p
pc
pN
p
LD
¤
¤ LD
¤
¤ LD
HW
p N3
¤ c FL
¤
N
GE
HW
GE
LD
p
N
N
LD
p
L1
L2
L1
p
¤N
p
p
pN
GE
N3
N
N3
pc
pc
p
pN
LD
¤c
¤c
¤
¤c
¤c
¤c
¤c
¤ c TF
¤cF
c LD
¤ TX
¤ c N3
¤c
ipc
¤c
¤c
21
SA22-7871-08.book Page 22 Thursday, February 19, 2015 3:46 PM
Mnemonic
TBEGIN
TBEGINC
TCDB
TCEB
TCXB
TDCDT
TDCET
TDCXT
TDGDT
TDGET
TDGXT
TEND
THDER
THDR
TM
TMH
TMHH
TMHL
TML
TMLH
TMLL
TMY
TP
TPI
TPROT
TR
TRACE
TRACG
TRAP2
TRAP4
TRE
TROO
TROT
TRT
TRTE
TRTO
TRTR
TRTRE
TRTT
TS
TSCH
UNPK
UNPKA
UNPKU
UPT
VA
VAC
VACC
VACCC
VAVG
VAVGL
VCDG
VCDLG
VCEQ
VCGD
VCH
VCHL
VCKSM
VCLGD
VCLZ
22
Operands
D1(B1),I2
D1(B1),I2
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
R1,D2(X2,B2)
Name
Transaction Begin (nonconstrained)
Transaction Begin (constrained)
Test Data Class (LB)
Test Data Class (SB)
Test Data Class (EB)
Test Data Class (LD)
Test Data Class (SD)
Test Data Class (ED)
Test Data Group (LD)
Test Data Group (SD)
Test Data Group (ED)
Transaction End
R1,R2
Convert BFP to HFP (LHSB)
Convert BFP to HFP (LHLB)
R1,R2
D1(B1),I2
Test under Mask
R1,I2
Test under Mask High
R1,I2
Test under Mask (high high)
R1,I2
Test under Mask (high low)
R1,I2
Test under Mask Low
R1,I2
Test under Mask (low high)
R1,I2
Test under Mask (low low)
D1(B1),I2
Test under Mask
D1(L1,B1)
Test Decimal
D2(B2)
Test Pending Interruption
D1(B1),D2(B2)
Test Protection
D1(L,B1),D2(B2)
Translate
R1,R3,D2(B2)
Trace (32)
R1,R3,D2(B2)
Trace (64)
Trap
D2(B2)
Trap
R1,R2
Translate Extended
R1,R2[,M3]
Translate One to One
R1,R2[,M3]
Translate One to Two
D1(L,B1),D2(B2)
Translate and Test
R1,R2[,M3]
Translate and Test Extended
R1,R2[,M3]
Translate Two to One
D1(L,B1),D2(B2)
Translate and Test Reverse
R1,R2[,M3]
Translate and Test Reverse Extended
R1,R2[,M3]
Translate Two to Two
D2(B2)
Test and Set
Test Subchannel
D2(B2)
D1(L1,B1),D2(L2,B2) Unpack
D1(L1,B1),D2(B2) Unpack ASCII
D1(L1,B1),D2(B2) Unpack Unicode
Update Tree
Vector Add
V1,V2,V3,M4
V1,V2,V3,V4,M5
Vector Add With Carry
V1,V2,V3,M4
Vector Add Compute Carry
V1,V2,V3,V4,M5
Vector Add With Carry Compute Carry
V1,V2,V3,M4
Vector Average
V1,V2,V3,M4
Vector Average Logical
V1,V2,M3,M4,M5
Vector FP Convert from Fixed 64-bit
V1,V2,M3,M4,M5
Vector FP Convert from Logical 64-bit
V1,V2,V3,M4,M5
Vector Compare Equal
V1,V2,M3,M4,M5
Vector FP Convert to Fixed 64-bit
V1,V2,V3,M4,M5
Vector Compare High
V1,V2,V3,M4,M5
Vector Compare High Logical
Vector Checksum
V1,V2,V3
V1,V2,M3,M4,M5
Vector FP Convert to Logical 64-bit
Vector Count Leading Zeros
V1,V2,M3
z/Architecture Reference Summary
Format
SIL
SIL
RXE
RXE
RXE
RXE
RXE
RXE
RXE
RXE
RXE
S
RRE
RRE
SI
RI-a
RI-a
RI-a
RI-a
RI-a
RI-a
SIY
RSL
S
SSE
SS-a
RS-a
RSY-a
E
S
RRE
RRF-c
RRF-c
SS-a
RRF-c
RRF-c
SS-a
RRF
RRF-c
S
S
SS-b
SS-a
SS-a
E
VRR-c
VRR-d
VRR-c
VRR-d
VRR-c
VRR-c
VRR-a
VRR-a
VRR-b
VRR-a
VRR-b
VRR-b
VRR-c
VRR-a
VRR-a
Opcode
E560
E561
ED11
ED10
ED12
ED54
ED50
ED58
ED55
ED51
ED59
B2F8
B358
B359
91
A70
A72
A73
A71
A70
A71
EB51
EBC0
B236
E501
DC
99
EB0F
01FF
B2FF
B2A5
B993
B992
DD
B9BF
B991
D0
B9BD
B990
93
B235
F3
EA
E2
0102
E7F3
E7BB
E7F1
E7B9
E7F2
E7F0
E7C3
E7C1
E7F8
E7C2
E7FB
E7F9
E766
E7C0
E753
Class
&
Notes
¤ c TX
¤ c CX
¤c
¤c
¤c
¤ TF
¤ TF
¤ TF
¤ TF
¤ TF
¤ TF
¤ c TX
¤c
¤c
c
c
cN
cN
c
cN
cN
c LD
¤ c E2
pc
pc
¤
p
pN
¤
¤
¤c
¤ c E2
¤ c E2
¤c
¤ PE
¤ c E2
¤ c E3
¤ PE
¤ c E2
¤c
pc
¤
¤ c E2
¤ c E2
i¤c
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ c* VF
¤ VF
¤ c* VF
¤ c* VF
¤ VF
¤ VF
¤ VF
SA22-7871-08.book Page 23 Thursday, February 19, 2015 3:46 PM
Mnemonic
VCTZ
VEC
VECL
VERIM
Operands
V1,V2,M3
V1,V2,M3
V1,V2,M3
V1,V2,V3,I4,M5
VERLL
VERLLV
VESL
VESLV
VESRA
VESRAV
VESRL
VESRLV
VFA
VFAE
VFCE
VFCH
VFCHE
VFD
VFEE
VFENE
VFI
VFM
VFMA
VFMS
VFPSO
VFS
VFSQ
VFTCI
VGBM
VGEF
VGEG
VGFM
VGFMA
V1,V3,D2(B2),M4
V1,V2,V3,M4
V1,V3,D2(B2),M4
V1,V2,V3,M4
V1,V3,D2(B2),M4
V1,V2,V3,M4
V1,V3,D2(B2),M4
V1,V2,V3,M4
V1,V2,V3,M4,M5
V1,V2,V3,M4[,M5]
V1,V2,V3,M4,M5,M6
V1,V2,V3,M4,M5,M6
V1,V2,V3,M4,M5,M6
V1,V2,V3,M4,M5
V1,V2,V3,M4[,M5]
V1,V2,V3,M4[,M5]
V1,V2,M3,M4,M5
V1,V2,V3,M4,M5
V1,V2,V3,V4,M5,M6
V1,V2,V3,V4,M5,M6
V1,V2,M3,M4,M5
V1,V2,V3,M4,M5
V1,V2,M3,M4
V1,V2,I3,M4,M5
V1,I2
V1,D2(V2,B2),M3
V1,D2(V2,B2),M3
V1,V2,V3,M4
V1,V2,V3,V4,M5
VGM
VISTR
VL
VLBB
VLC
VLDE
VLEB
VLED
VLEF
VLEG
VLEH
VLEIB
VLEIF
VLEIG
VLEIH
VLGV
VLL
VLLEZ
VLM
VLP
VLR
VLREP
VLVG
VLVGP
VMAE
V1,I2,I3,V4
V1,V2,M3[,M5]
V1,D2(X2,B2)
V1,D2(X2,B2),M3
V1,V2,M3
V1,V2,M3,M4
V1,D2(X2,B2),M3
V1,V2,M3,M4,M5
V1,D2(X2,B2),M3
V1,D2(X2,B2),M3
V1,D2(X2,B2),M3
V1,I2,M3
V1,I2,M3
V1,I2,M3
V1,I2,M3
R1,V3,D2(B2),M4
V1,R3,D2(B2)
V1,D2(X2,B2),M3
V1,V3,D2(B2)
V1,V2,M3
V1,V2
V1,D2(X2,B2),M3
V1,R3,D2(B2),M4
V1,R2,R3
V1,V2,V3,V4,M5
Name
Vector Count Trailing Zeros
Vector Element Compare
Vector Element Compare Logical
Vector Element Rotate and Insert Under
Mask
Vector Element Rotate Left Logical
Vector Element Rotate Left Logical
Vector Element Shift Left
Vector Element Shift Left
Vector Element Shift Right Arithmetic
Vector Element Shift Right Arithmetic
Vector Element Shift Right Logical
Vector Element Shift Right Logical
Vector FP Add
Vector Find Any Element Equal
Vector FP Compare Equal
Vector FP Compare High
Vector FP Compare High or Equal
Vector FP Divide
Vector Find Element Equal
Vector Find Element Not Equal
Vector Load FP Integer
Vector FP Multiply
Vector FP Multiply and Add
Vector FP Multiply and Subtract
Vector FP Perform Sign Operation
Vector FP Subtract
Vector FP Square Root
Vector FP Test Data Class Immediate
Vector Generate Byte Mask
Vector Gather Element (32)
Vector Gather Element (64)
Vector Galois Field Multiply Sum
Vector Galois Field Multiply Sum and Accumulate
Vector Generate Mask
Vector Isolate String
Vector Load
Vector Load to Block Boundary
Vector Load Complement
Vector FP Load Lengthened
Vector Load Element (8)
Vector FP Load Rounded
Vector Load Element (32)
Vector Load Element (64)
Vector Load Element (16)
Vector Load Element Immediate (8)
Vector Load Element Immediate (32)
Vector Load Element Immediate (64)
Vector Load Element Immediate (16)
Vector Load GR from VR Element
Vector Load With Length
Vector Load Logical Element and Zero
Vector Load Multiple
Vector Load Positive
Vector Load
Vector Load and Replicate
Vector Load VR Element from GR
Vector Load VR from GRs Disjoint
Vector Multiply and Add Even
Format
VRR-a
VRR-a
VRR-a
VRI-d
Opcode
E752
E7DB
E7D9
E772
Class
&
Notes
¤ VF
¤ c VF
¤ c VF
¤ VF
VRS-a
VRR-c
VRS-a
VRR-c
VRS-a
VRR-c
VRS-a
VRR-c
VRR-c
VRR-b
VRR-c
VRR-c
VRR-c
VRR-c
VRR-b
VRR-b
VRR-a
VRR-c
VRR-e
VRR-e
VRR-a
VRR-c
VRR-a
VRI-e
VRI-a
VRV
VRV
VRR-c
VRR-d
E733
E773
E730
E770
E73A
E77A
E738
E778
E7E3
E782
E7E8
E7EB
E7EA
E7E5
E780
E781
E7C7
E7E7
E78F
E78E
E7CC
E7E2
E7CE
E74A
E744
E713
E712
E7B4
E7BC
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ c* VF
¤ c* VF
¤ c* VF
¤ c* VF
¤ VF
¤ c* VF
¤ c* VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
VRI-b
VRR-a
VRX
VRX
VRR-a
VRR-a
VRX
VRR-a
VRX
VRX
VRX
VRI-a
VRI-a
VRI-a
VRI-a
VRS-c
VRS-b
VRX
VRS-a
VRR-a
VRR-a
VRX
VRS-b
VRR-f
VRR-d
E746
E75C
E706
E707
E7DE
E7C4
E700
E7C5
E703
E702
E701
E740
E743
E742
E741
E721
E737
E704
E736
E7DF
E756
E705
E722
E762
E7AE
¤ VF
¤ c* VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
23
SA22-7871-08.book Page 24 Thursday, February 19, 2015 3:46 PM
Mnemonic
VMAH
VMAL
VMALE
VMALH
VMALO
VMAO
VME
VMH
VML
VMLE
VMLH
VMLO
VMN
VMNL
VMO
VMRH
VMRL
VMX
VMXL
VN
VNC
VNO
VO
VPDI
VPERM
VPK
VPKLS
VPKS
VPOPCT
VREP
VREPI
VS
VSBCBI
Name
Vector Multiply and Add High
Vector Multiply and Add Low
Vector Multiply and Add Logical Even
Vector Multiply and Add Logical High
Vector Multiply and Add Logical Odd
Vector Multiply and Add Odd
Vector Multiply Even
Vector Multiply High
Vector Multiply Low
Vector Multiply Logical Even
Vector Multiply Logical High
Vector Multiply Logical Odd
Vector Minimum
Vector Minimum Logical
Vector Multiply Odd
Vector Merge High
Vector Merge Low
Vector Maximum
Vector Maximum Logical
Vector AND
Vector AND with Complement
Vector NOR
Vector OR
Vector Permute Doubleword Immediate
Vector Permute
Vector Pack
Vector Pack Logical Saturate
Vector Pack Saturate
Vector Population Count
Vector Replicate
Vector Replicate Immediate
Vector Subtract
Vector Subtract With Borrow Compute
Borrow Indication
VSBI
V1,V2,V3,V4,M5
Vector Subtract With Borrow Indication
VSCBI
V1,V2,V3,M4
Vector Subtract Compute Borrow Indication
VSCEF V1,D2(V2,B2),M3
Vector Scatter Element (32)
VSCEG V1,D2(V2,B2),M3
Vector Scatter Element (64)
VSEG
V1,V2,M3
Vector Sign Extend to Doubleword
VSEL
V1,V2,V3,V4
Vector Select
Vector Shift Left
VSL
V1,V2,V3
VSLB
V1,V2,V3
Vector Shift Left By Byte
VSLDB V1,V2,V3,I4
Vector Shift Left Double By Byte
Vector Shift Right Arithmetic
VSRA
V1,V2,V3
VSRAB V1,V2,V3
Vector Shift Right Arithmetic By Byte
VSRL
V1,V2,V3
Vector Shift Right Logical
VSRLB V1,V2,V3
Vector Shift Right Logical By Byte
VST
V1,D2(X2,B2)
Vector Store
VSTEB V1,D2(X2,B2),M3
Vector Store Element (8)
VSTEF V1,D2(X2,B2),M3
Vector Store Element (32)
VSTEG V1,D2(X2,B2),M3
Vector Store Element (64)
Vector Store Element (16)
VSTEH V1,D2(X2,B2),M3
VSTL
V1,R3,D2(B2)
Vector Store With Length
Vector Store Multiple
VSTM
V1,V3,D2(B2)
VSTRC V1,V2,V3,V4,M5[,M6] Vector String Range Compare
VSUM
V1,V2,V3,M4
Vector Sum Across Word
Vector Sum Across Doubleword
VSUMG V1,V2,V3,M4
VSUMQ V1,V2,V3,M4
Vector Sum Across Quadword
Vector Test Under Mask
VTM
V1,V2
VUPH
V1,V2,M3
Vector Unpack High
24
Operands
V1,V2,V3,V4,M5
V1,V2,V3,V4,M5
V1,V2,V3,V4,M5
V1,V2,V3,V4,M5
V1,V2,V3,V4,M5
V1,V2,V3,V4,M5
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3,M4
V1,V2,V3
V1,V2,V3
V1,V2,V3
V1,V2,V3
V1,V2,V3,M4
V1,V2,V3,V4
V1,V2,V3,M4
V1,V2,V3,M4,M5
V1,V2,V3,M4,M5
V1,V2,M3
V1,V3,I2,M4
V1,I2,M3
V1,V2,V3,M4
V1,V2,V3,V4,M5
z/Architecture Reference Summary
Format
VRR-d
VRR-d
VRR-d
VRR-d
VRR-d
VRR-d
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-c
VRR-e
VRR-c
VRR-b
VRR-b
VRR-a
VRI-c
VRI-a
VRR-c
VRR-d
Opcode
E7AB
E7AA
E7AC
E7A9
E7AD
E7AF
E7A6
E7A3
E7A2
E7A4
E7A1
E7A5
E7FE
E7FC
E7A7
E761
E760
E7FF
E7FD
E768
E769
E76B
E76A
E784
E78C
E794
E795
E797
E750
E74D
E745
E7F7
E7BD
Class
&
Notes
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ c* VF
¤ c* VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
VRR-d
VRR-c
VRV
VRV
VRR-a
VRR-e
VRR-c
VRR-c
VRI-d
VRR-c
VRR-c
VRR-c
VRR-c
VRX
VRX
VRX
VRX
VRX
VRS-b
VRS-a
VRR-d
VRR-c
VRR-c
VRR-c
VRR-a
VRR-a
E7BF
E7F5
E71B
E71A
E75F
E78D
E774
E775
E777
E77E
E77F
E77C
E77D
E70E
E708
E70B
E70A
E709
E73F
E73E
E78A
E764
E765
E767
E7D8
E7D7
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ c* VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
SA22-7871-08.book Page 25 Thursday, February 19, 2015 3:46 PM
Mnemonic
VUPL
VUPLH
VUPLL
VX
WFC
WFK
X
XC
XG
XGR
XGRK
XI
XIHF
XILF
XIY
XR
XRK
XSCH
XY
ZAP
Operands
V1,V2,M3
V1,V2,M3
V1,V2,M3
V1,V2,V3
V1,V2,M3,M4
V1,V2,M3,M4
R1,D2(X2,B2)
D1(L,B1),D2(B2)
R1,D2(X2,B2)
R1,R2
R1,R2,R3
D1(B1),I2
R1,I2
R1,I2
D1(B1),I2
R1,R2
R1,R2,R3
Name
Vector Unpack Low
Vector Unpack Logical High
Vector Unpack Logical Low
Vector Exclusive OR
Vector FP Compare Scalar
Vector FP Compare and Signal Scalar
Exclusive OR (32)
Exclusive OR (character)
Exclusive OR (64)
Exclusive OR (64)
Exclusive OR (64)
Exclusive OR Immediate
Exclusive OR Immediate (high)
Exclusive OR Immediate (low)
Exclusive OR Immediate
Exclusive OR (32)
Exclusive OR (32)
Cancel Subchannel
R1,D2(X2,B2)
Exclusive Or (32)
D1(L1,B1),D2(L2,B2) Zero and Add
Floating-Point Operand Lengths and Types:
E
Extended (binary, decimal or hex)
EB Extended binary
ED Extended decimal
EH Extended hex
EHL Extended hex (low-order part)
EHH Extended hex (high-order part)
L
Long (binary, decimal or hex)
Notes:
&
¤
Combination of fields
One or more restrictions apply in the
transactional-execution mode
c
Condition code set
c*
Condition code may be set based on
control in the instruction
i
Interruptible instruction
n
New condition code loaded
p
Privileged instruction; restricted in the
transactional-execution mode
q
Semiprivileged instruction; restricted in
the transactional-execution mode
u
Condition code is unpredictable
CS Compare-and-swap-and-store facility
CT Configuration topology facility
CX Constrained-transactional-execution
facility
D2 DAT-enhancement facility 2
DE DAT-enhancement facility
DO Distinct-operands facility
E2 Extended-translation facility 2
E3 Extended-translation facility 3
ED1 Enhanced-DAT facility 1
ED2 Enhanced-DAT facility 2
EH Execution-hint facility
EI
Extended-immediate facility
ES Expanded-storage facility
ET Extract-CPU-time facility
F
Floating-point-extension facility
FG FPR-GPR-transfer facility
FL Store-facility-list-extended facility
FS Floating-point-support-sign-handling
facility
GE General-instructions-extension facility
HM HFP multiply-and-add/subtract facility
Format
VRR-a
VRR-a
VRR-a
VRR-c
VRR-a
VRR-a
RX-a
SS-a
RXY-a
RRE
RRF-a
SI
RIL-a
RIL-a
SIY
RR
RRF-a
S
RXY-a
SS-b
Opcode
E7D6
E7D5
E7D4
E76D
E7CB
E7CA
57
D7
E382
B982
B9E7
97
C06
C07
EB57
17
B9F7
B276
E357
F8
Class
&
Notes
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
¤ VF
c
¤c
cN
cN
c DO
c
c EI
c EI
c LD
c
c DO
pc
c LD
¤c
LB
LD
LH
S
SB
SD
SH
Long binary
Long decimal
Long hex
Short (binary, decimal or hex)
Short binary
Short decimal
Short hex
HW
IA
L1
L2
LD
LT
LZ
M3
M4
M5
MI
MO
High-word facility
Interlocked-access facility
Load/store-on-condition facility 1
Load/store-on-condition facility 2
Long-displacement facility
Load-and-trap facility
Load-and-zero-rightmost-byte facility
Message-security assist extension 3
Message-security assist extension 4
Message-security assist extension 5
Miscellaneous-instructions facility
Move-with-optional-specifications
facility
Message-security assist
New in z/Architecture
New in z/Architecture and added to
ESA/390
Processor-assist facility
DFP-packed-conversion facility
Parsing-enhancement facility
PFPO facility
Population-count facility
ASN-and-LX-reuse facility
Reset-reference-bits multiple facility
Store-clock-fast facility
Decimal-floating-point facility
Decimal-floating-point-rounding facility
TOD-clock-steering facility
Transactional-execution facility
HFP unnormalized-extension facility
Vector facility for z/Architecture
IEEE-exception-support facility
Execute-extension facility
DFP zoned-conversion facility
MS
N
N3
PA
PC
PE
PF
PK
RA
RB
SC
TF
TR
TS
TX
UE
VF
XF
XX
ZF
25
SA22-7871-08.book Page 26 Thursday, February 19, 2015 3:46 PM
Machine Instructions by Operation Code
OpCode
0101
0102
0104
0107
010A
010B
010C
010D
010E
01FF
04
05
06
07
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
35
36
37
38
39
3A
3B
3C
3C
3D
3E
3F
40
26
Mnemonic
PR
UPT
PTFF
SCKPF
PFPO
TAM
SAM24
SAM31
SAM64
TRAP2
SPM
BALR
BCTR
BCR
SVC
BSM
BASSM
BASR
MVCL
CLCL
LPR
LNR
LTR
LCR
NR
CLR
OR
XR
LR
CR
AR
SR
MR
DR
ALR
SLR
LPDR
LNDR
LTDR
LCDR
HDR
LDXR
LRDR
MXR
MXDR
LDR
CDR
ADR
SDR
MDR
DDR
AWR
SWR
LPER
LNER
LTER
LCER
HER
LEDR
LRER
AXR
SXR
LER
CER
AER
SER
MDER
MER
DER
AUR
SUR
STH
OpCode
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
67
68
69
6A
6B
6C
6D
6E
6F
70
71
78
79
7A
7B
7C
7C
7D
7E
7F
80
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
Mnemonic
LA
STC
IC
EX
BAL
BCT
BC
LH
CH
AH
SH
MH
BAS
CVD
CVB
ST
LAE
N
CL
O
X
L
C
A
S
M
D
AL
SL
STD
MXD
LD
CD
AD
SD
MD
DD
AW
SW
STE
MS
LE
CE
AE
SE
MDE
ME
DE
AU
SU
SSM
LPSW
Diagnose
BRXH
BRXLE
BXH
BXLE
SRL
SLL
SRA
SLA
SRDL
SLDL
SRDA
SLDA
STM
TM
MVI
TS
NI
CLI
OI
OpCode
97
98
99
9A
9B
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A5A
A5B
A5C
A5D
A5E
A5F
A70
A70
A71
A71
A72
A73
A74
A75
A76
A77
A78
A79
A7A
A7B
A7C
A7D
A7E
A7F
A8
A9
AC
AD
AE
AF
B1
B202
B204
B205
B206
B207
B208
B209
B20A
B20B
B20D
B210
B211
B212
B214
B218
B219
B21A
B221
B222
B223
B224
B225
B226
B227
B228
B229
z/Architecture Reference Summary
Mnemonic
XI
LM
TRACE
LAM
STAM
IIHH
IIHL
IILH
IILL
NIHH
NIHL
NILH
NILL
OIHH
OIHL
OILH
OILL
LLIHH
LLIHL
LLILH
LLILL
TMH
TMLH
TML
TMLL
TMHH
TMHL
BRC
BRAS
BRCT
BRCTG
LHI
LGHI
AHI
AGHI
MHI
MGHI
CHI
CGHI
MVCLE
CLCLE
STNSM
STOSM
SIGP
MC
LRA
STIDP
SCK
STCK
SCKC
STCKC
SPT
STPT
SPKA
IPK
PTLB
SPX
STPX
STAP
SIE
PC
SAC
CFC
IPTE
IPM
IVSK
IAC
SSAR
EPAR
ESAR
PT
ISKE
SA22-7871-08.book Page 27 Thursday, February 19, 2015 3:46 PM
OpCode
B22A
B22B
B22C
B22D
B22E
B22F
B230
B231
B232
B233
B234
B235
B236
B237
B238
B239
B23A
B23B
B23C
B240
B241
B244
B245
B246
B247
B248
B249
B24A
B24B
B24C
B24D
B24E
B24F
B250
B252
B254
B255
B257
B258
B25A
B25D
B25E
B263
B276
B277
B278
B279
B27C
B27D
B299
B29C
B29D
B2A5
B2A6
B2A6
B2A7
B2A7
B2B0
B2B1
B2B2
B2B8
B2B9
B2BD
B2E8
B2EC
B2F8
B2FA
B2FC
B2FF
B300
B301
B302
B303
B304
B305
B306
Mnemonic
RRBE
SSKE
TB
DXR
PGIN
PGOUT
CSCH
HSCH
MSCH
SSCH
STSCH
TSCH
TPI
SAL
RSCH
STCRW
STCPS
RCHP
SCHM
BAKR
CKSM
SQDR
SQER
STURA
MSTA
PALB
EREG
ESTA
LURA
TAR
CPYA
SAR
EAR
CSP
MSR
MVPG
MVST
CUSE
BSG
BSA
CLST
SRST
CMPSC
XSCH
RP
STCKE
SACF
STCKF
STSI
SRNM
STFPC
LFPC
TRE
CU21
CUUTF
CU12
CUTFU
STFLE
STFL
LPSWE
SRNMB
SRNMT
LFAS
PPA
ETND
TEND
NIAI
TABORT
TRAP4
LPEBR
LNEBR
LTEBR
LCEBR
LDEBR
LXDBR
LXEBR
OpCode
B307
B308
B309
B30A
B30B
B30C
B30D
B30E
B30F
B310
B311
B312
B313
B314
B315
B316
B317
B318
B319
B31A
B31B
B31C
B31D
B31E
B31F
B324
B325
B326
B32E
B32F
B336
B337
B338
B339
B33A
B33B
B33C
B33D
B33E
B33F
B340
B341
B342
B343
B344
B344
B345
B345
B346
B346
B347
B347
B348
B349
B34A
B34B
B34C
B34D
B350
B351
B353
B357
B357
B358
B359
B35B
B35F
B35F
B360
B361
B362
B363
B365
B366
B367
B369
Mnemonic
MXDBR
KEBR
CEBR
AEBR
SEBR
MDEBR
DEBR
MAEBR
MSEBR
LPDBR
LNDBR
LTDBR
LCDBR
SQEBR
SQDBR
SQXBR
MEEBR
KDBR
CDBR
ADBR
SDBR
MDBR
DDBR
MADBR
MSDBR
LDER
LXDR
LXER
MAER
MSER
SQXR
MEER
MAYLR
MYLR
MAYR
MYR
MAYHR
MYHR
MADR
MSDR
LPXBR
LNXBR
LTXBR
LCXBR
LEDBR
LEDBRA
LDXBR
LDXBRA
LEXBR
LEXBRA
FIXBR
FIXBRA
KXBR
CXBR
AXBR
SXBR
MXBR
DXBR
TBEDR
TBDR
DIEBR
FIEBR
FIEBRA
THDER
THDR
DIDBR
FIDBR
FIDBRA
LPXR
LNXR
LTXR
LCXR
LXR
LEXR
FIXR
CXR
OpCode
B370
B371
B372
B373
B374
B375
B376
B377
B37F
B384
B385
B38C
B390
B391
B392
B394
B394
B395
B395
B396
B396
B398
B398
B399
B399
B39A
B39A
B39C
B39D
B39E
B3A0
B3A1
B3A2
B3A4
B3A4
B3A5
B3A5
B3A6
B3A6
B3A8
B3A8
B3A9
B3A9
B3AA
B3AA
B3AC
B3AD
B3AE
B3B4
B3B5
B3B6
B3B8
B3B9
B3BA
B3C1
B3C4
B3C5
B3C6
B3C8
B3C9
B3CA
B3CD
B3D0
B3D0
B3D1
B3D1
B3D2
B3D2
B3D3
B3D3
B3D4
B3D5
B3D6
B3D7
B3D8
B3D8
Mnemonic
LPDFR
LNDFR
CPSDR
LCDFR
LZER
LZDR
LZXR
FIER
FIDR
SFPC
SFASR
EFPC
CELFBR
CDLFBR
CXLFBR
CEFBR
CEFBRA
CDFBR
CDFBRA
CXFBR
CXFBRA
CFEBR
CFEBRA
CFDBR
CFDBRA
CFXBR
CFXBRA
CLFEBR
CLFDBR
CLFXBR
CELGBR
CDLGBR
CXLGBR
CEGBR
CEGBRA
CDGBR
CDGBRA
CXGBR
CXGBRA
CGEBR
CGEBRA
CGDBR
CGDBRA
CGXBR
CGXBRA
CLGEBR
CLGDBR
CLGXBR
CEFR
CDFR
CXFR
CFER
CFDR
CFXR
LDGR
CEGR
CDGR
CXGR
CGER
CGDR
CGXR
LGDR
MDTR
MDTRA
DDTR
DDTRA
ADTR
ADTRA
SDTR
SDTRA
LDETR
LEDTR
LTDTR
FIDTR
MXTR
MXTRA
27
SA22-7871-08.book Page 28 Thursday, February 19, 2015 3:46 PM
OpCode
B3D9
B3D9
B3DA
B3DA
B3DB
B3DB
B3DC
B3DD
B3DE
B3DF
B3E0
B3E1
B3E1
B3E2
B3E3
B3E4
B3E5
B3E7
B3E8
B3E9
B3E9
B3EA
B3EB
B3EC
B3ED
B3EF
B3F1
B3F1
B3F2
B3F3
B3F4
B3F5
B3F6
B3F7
B3F9
B3F9
B3FA
B3FB
B3FC
B3FD
B3FE
B3FF
B6
B7
B900
B901
B902
B903
B904
B905
B906
B907
B908
B909
B90A
B90B
B90C
B90D
B90E
B90F
B910
B911
B912
B913
B914
B916
B917
B918
B919
B91A
B91B
B91C
B91D
B91E
B91F
B920
28
Mnemonic
DXTR
DXTRA
AXTR
AXTRA
SXTR
SXTRA
LXDTR
LDXTR
LTXTR
FIXTR
KDTR
CGDTR
CGDTRA
CUDTR
CSDTR
CDTR
EEDTR
ESDTR
KXTR
CGXTR
CGXTRA
CUXTR
CSXTR
CXTR
EEXTR
ESXTR
CDGTR
CDGTRA
CDUTR
CDSTR
CEDTR
QADTR
IEDTR
RRDTR
CXGTR
CXGTRA
CXUTR
CXSTR
CEXTR
QAXTR
IEXTR
RRXTR
STCTL
LCTL
LPGR
LNGR
LTGR
LCGR
LGR
LURAG
LGBR
LGHR
AGR
SGR
ALGR
SLGR
MSGR
DSGR
EREGG
LRVGR
LPGFR
LNGFR
LTGFR
LCGFR
LGFR
LLGFR
LLGTR
AGFR
SGFR
ALGFR
SLGFR
MSGFR
DSGFR
KMAC
LRVR
CGR
OpCode
B921
B925
B926
B927
B928
B92A
B92B
B92C
B92D
B92E
B92F
B930
B931
B93C
B93E
B93F
B941
B942
B943
B946
B949
B94A
B94B
B951
B952
B953
B959
B95A
B95B
B960
B961
B972
B973
B980
B981
B982
B983
B984
B985
B986
B987
B988
B989
B98A
B98D
B98E
B98F
B990
B991
B992
B993
B994
B995
B996
B997
B998
B999
B99A
B99B
B99D
B99E
B99F
B9A2
B9AA
B9AE
B9AF
B9B0
B9B1
B9B2
B9B3
B9BD
B9BE
B9BF
B9C8
B9C9
B9CA
Mnemonic
CLGR
STURG
LBR
LHR
PCKMO
KMF
KMO
PCC
KMCTR
KM
KMC
CGFR
CLGFR
PPNO
KIMD
KLMD
CFDTR
CLGDTR
CLFDTR
BCTGR
CFXTR
CLGXTR
CLFXTR
CDFTR
CDLGTR
CDLFTR
CXFTR
CXLGTR
CXLFTR
CGRT
CLGRT
CRT
CLRT
NGR
OGR
XGR
FLOGR
LLGCR
LLGHR
MLGR
DLGR
ALCGR
SLBGR
CSPG
EPSW
IDTE
CRDTE
TRTT
TRTO
TROT
TROO
LLCR
LLHR
MLR
DLR
ALCR
SLBR
EPAIR
ESAIR
ESEA
PTI
SSAIR
PTF
LPTEA
RRBM
PFMF
CU14
CU24
CU41
CU42
TRTRE
SRSTU
TRTE
AHHHR
SHHHR
ALHHHR
OpCode
B9CB
B9CD
B9CF
B9D8
B9D9
B9DA
B9DB
B9DD
B9DF
B9E0
B9E1
B9E2
B9E4
B9E6
B9E7
B9E8
B9E9
B9EA
B9EB
B9F2
B9F4
B9F6
B9F7
B9F8
B9F9
B9FA
B9FB
BA
BB
BD
BE
BF
C00
C01
C04
C05
C06
C07
C08
C09
C0A
C0B
C0C
C0D
C0E
C0F
C20
C21
C24
C25
C28
C29
C2A
C2B
C2C
C2D
C2E
C2F
C42
C44
C45
C46
C47
C48
C4B
C4C
C4D
C4E
C4F
C5
C60
C62
C64
C65
C66
C67
z/Architecture Reference Summary
Mnemonic
SLHHHR
CHHR
CLHHR
AHHLR
SHHLR
ALHHLR
SLHHLR
CHLR
CLHLR
LOCFHR
POPCNT
LOCGR
NGRK
OGRK
XGRK
AGRK
SGRK
ALGRK
SLGRK
LOCR
NRK
ORK
XRK
ARK
SRK
ALRK
SLRK
CS
CDS
CLM
STCM
ICM
LARL
LGFI
BRCL
BRASL
XIHF
XILF
IIHF
IILF
NIHF
NILF
OIHF
OILF
LLIHF
LLILF
MSGFI
MSFI
SLGFI
SLFI
AGFI
AFI
ALGFI
ALFI
CGFI
CFI
CLGFI
CLFI
LLHRL
LGHRL
LHRL
LLGHRL
STHRL
LGRL
STGRL
LGFRL
LRL
LLGFRL
STRL
BPRP
EXRL
PFDRL
CGHRL
CHRL
CLGHRL
CLHRL
SA22-7871-08.book Page 29 Thursday, February 19, 2015 3:46 PM
OpCode
C68
C6A
C6C
C6D
C6E
C6F
C7
C80
C81
C82
C84
C85
CC6
CC8
CCA
CCB
CCD
CCF
D0
D1
D2
D3
D4
D5
D6
D7
D9
DA
DB
DC
DD
DE
DF
E1
E2
E302
E303
E304
E306
E308
E309
E30A
E30B
E30C
E30D
E30E
E30F
E312
E313
E314
E315
E316
E317
E318
E319
E31A
E31B
E31C
E31D
E31E
E31F
E320
E321
E324
E325
E326
E32A
E32E
E32F
E330
E331
E332
E334
E336
E33A
E33B
Mnemonic
CGRL
CLGRL
CGFRL
CRL
CLGFRL
CLRL
BPP
MVCOS
ECTG
CSST
LPD
LPDG
BRCTH
AIH
ALSIH
ALSIHN
CIH
CLIH
TRTR
MVN
MVC
MVZ
NC
CLC
OC
XC
MVCK
MVCP
MVCS
TR
TRT
ED
EDMK
PKU
UNPKU
LTG
LRAG
LG
CVBY
AG
SG
ALG
SLG
MSG
DSG
CVBG
LRVG
LT
LRAY
LGF
LGH
LLGF
LLGT
AGF
SGF
ALGF
SLGF
MSGF
DSGF
LRV
LRVH
CG
CLG
STG
NTSTG
CVDY
LZRG
CVDG
STRVG
CGF
CLGF
LTGF
CGH
PFD
LLZRGF
LZRF
OpCode
E33E
E33F
E346
E350
E351
E354
E355
E356
E357
E358
E359
E35A
E35B
E35C
E35E
E35F
E370
E371
E372
E373
E375
E376
E377
E378
E379
E37A
E37B
E37C
E380
E381
E382
E385
E386
E387
E388
E389
E38E
E38F
E390
E391
E394
E395
E396
E397
E398
E399
E39C
E39C
E39F
E3C0
E3C2
E3C3
E3C4
E3C6
E3C7
E3C8
E3CA
E3CB
E3CD
E3CF
E500
E501
E502
E50E
E50F
E544
E548
E54C
E554
E555
E558
E559
E55C
E55D
E560
E561
Mnemonic
STRV
STRVH
BCTG
STY
MSY
NY
CLY
OY
XY
LY
CY
AY
SY
MFY
ALY
SLY
STHY
LAY
STCY
ICY
LAEY
LB
LGB
LHY
CHY
AHY
SHY
MHY
NG
OG
XG
LGAT
MLG
DLG
ALCG
SLBG
STPQ
LPQ
LLGC
LLGH
LLC
LLH
ML
DL
ALC
SLB
LLGTAT
LLGFAT
LAT
LBH
LLCH
STCH
LHH
LLHH
STHH
LFHAT
LFH
STFH
CHF
CLHF
LASP
TPROT
STRAG
MVCSK
MVCDK
MVHHI
MVGHI
MVHI
CHHSI
CLHHSI
CGHSI
CLGHSI
CHSI
CLFHSI
TBEGIN
TBEGINC
OpCode
E700
E701
E702
E703
E704
E705
E706
E707
E708
E709
E70A
E70B
E70E
E712
E713
E71A
E71B
E721
E722
E727
E730
E733
E736
E737
E738
E73A
E73E
E73F
E740
E741
E742
E743
E744
E745
E746
E74A
E74D
E750
E752
E753
E756
E75C
E75F
E760
E761
E762
E764
E765
E766
E767
E768
E769
E76A
E76B
E76D
E770
E772
E773
E774
E775
E777
E778
E77A
E77C
E77D
E77E
E77F
E780
E781
E782
E784
E78A
E78C
E78D
E78E
E78F
Mnemonic
VLEB
VLEH
VLEG
VLEF
VLLEZ
VLREP
VL
VLBB
VSTEB
VSTEH
VSTEG
VSTEF
VST
VGEG
VGEF
VSCEG
VSCEF
VLGV
VLVG
LCBB
VESL
VERLL
VLM
VLL
VESRL
VESRA
VSTM
VSTL
VLEIB
VLEIH
VLEIG
VLEIF
VGBM
VREPI
VGM
VFTCI
VREP
VPOPCT
VCTZ
VCLZ
VLR
VISTR
VSEG
VMRL
VMRH
VLVGP
VSUM
VSUMG
VCKSM
VSUMQ
VN
VNC
VO
VNO
VX
VESLV
VERIM
VERLLV
VSL
VSLB
VSLDB
VESRLV
VESRAV
VSRL
VSRLB
VSRA
VSRAB
VFEE
VFENE
VFAE
VPDI
VSTRC
VPERM
VSEL
VFMS
VFMA
29
SA22-7871-08.book Page 30 Thursday, February 19, 2015 3:46 PM
OpCode
E794
E795
E797
E7A1
E7A2
E7A3
E7A4
E7A5
E7A6
E7A7
E7A9
E7AA
E7AB
E7AC
E7AD
E7AE
E7AF
E7B4
E7B9
E7BB
E7BC
E7BD
E7BF
E7C0
E7C1
E7C2
E7C3
E7C4
E7C5
E7C7
E7CA
E7CB
E7CC
E7CE
E7D4
E7D5
E7D6
E7D7
E7D8
E7D9
E7DB
E7DE
E7DF
E7E2
E7E3
E7E5
E7E7
E7E8
E7EA
E7EB
E7F0
E7F1
E7F2
E7F3
E7F5
E7F7
E7F8
E7F9
E7FB
E7FC
E7FD
E7FE
E7FF
E8
E9
EA
EB04
EB0A
EB0B
EB0C
EB0D
EB0F
EB14
EB1C
EB1D
EB20
30
Mnemonic
VPK
VPKLS
VPKS
VMLH
VML
VMH
VMLE
VMLO
VME
VMO
VMALH
VMAL
VMAH
VMALE
VMALO
VMAE
VMAO
VGFM
VACCC
VAC
VGFMA
VSBCBI
VSBI
VCLGD
VCDLG
VCGD
VCDG
VLDE
VLED
VFI
WFK
WFC
VFPSO
VFSQ
VUPLL
VUPLH
VUPL
VUPH
VTM
VECL
VEC
VLC
VLP
VFS
VFA
VFD
VFM
VFCE
VFCHE
VFCH
VAVGL
VACC
VAVG
VA
VSCBI
VS
VCEQ
VCHL
VCH
VMNL
VMXL
VMN
VMX
MVCIN
PKA
UNPKA
LMG
SRAG
SLAG
SRLG
SLLG
TRACG
CSY
RLLG
RLL
CLMH
OpCode
EB21
EB23
EB24
EB25
EB26
EB2B
EB2C
EB2D
EB2F
EB30
EB31
EB3E
EB44
EB45
EB4C
EB51
EB52
EB54
EB55
EB56
EB57
EB6A
EB6E
EB7A
EB7E
EB80
EB81
EB8E
EB8F
EB90
EB96
EB98
EB9A
EB9B
EBC0
EBDC
EBDD
EBDE
EBDF
EBE0
EBE1
EBE2
EBE3
EBE4
EBE6
EBE7
EBE8
EBEA
EBF2
EBF3
EBF4
EBF6
EBF7
EBF8
EBFA
EC42
EC44
EC45
EC46
EC4E
EC51
EC54
EC55
EC56
EC57
EC59
EC5D
EC64
EC65
EC70
EC71
EC72
EC73
EC76
EC77
EC7C
Mnemonic
CLMY
CLT
STMG
STCTG
STMH
CLGT
STCMH
STCMY
LCTLG
CSG
CDSY
CDSG
BXHG
BXLEG
ECAG
TMY
MVIY
NIY
CLIY
OIY
XIY
ASI
ALSI
AGSI
ALGSI
ICMH
ICMY
MVCLU
CLCLU
STMY
LMH
LMY
LAMY
STAMY
TP
SRAK
SLAK
SRLK
SLLK
LOCFH
STOCFH
LOCG
STOCG
LANG
LAOG
LAXG
LAAG
LAALG
LOC
STOC
LAN
LAO
LAX
LAA
LAAL
LOCHI
BRXHG
BRXLG
LOCGHI
LOCHHI
RISBLG
RNSBG
RISBG
ROSBG
RXSBG
RISBGN
RISBHG
CGRJ
CLGRJ
CGIT
CLGIT
CIT
CLFIT
CRJ
CLRJ
CGIJ
OpCode
EC7D
EC7E
EC7F
ECD8
ECD9
ECDA
ECDB
ECE4
ECE5
ECF6
ECF7
ECFC
ECFD
ECFE
ECFF
ED04
ED05
ED06
ED07
ED08
ED09
ED0A
ED0B
ED0C
ED0D
ED0E
ED0F
ED10
ED11
ED12
ED14
ED15
ED17
ED18
ED19
ED1A
ED1B
ED1C
ED1D
ED1E
ED1F
ED24
ED25
ED26
ED2E
ED2F
ED34
ED35
ED37
ED38
ED39
ED3A
ED3B
ED3C
ED3D
ED3E
ED3F
ED40
ED41
ED48
ED49
ED50
ED51
ED54
ED55
ED58
ED59
ED64
ED65
ED66
ED67
EDA8
EDA9
EDAA
EDAB
EDAC
z/Architecture Reference Summary
Mnemonic
CLGIJ
CIJ
CLIJ
AHIK
AGHIK
ALHSIK
ALGHSIK
CGRB
CLGRB
CRB
CLRB
CGIB
CLGIB
CIB
CLIB
LDEB
LXDB
LXEB
MXDB
KEB
CEB
AEB
SEB
MDEB
DEB
MAEB
MSEB
TCEB
TCDB
TCXB
SQEB
SQDB
MEEB
KDB
CDB
ADB
SDB
MDB
DDB
MADB
MSDB
LDE
LXD
LXE
MAE
MSE
SQE
SQD
MEE
MAYL
MYL
MAY
MY
MAYH
MYH
MAD
MSD
SLDT
SRDT
SLXT
SRXT
TDCET
TDGET
TDCDT
TDGDT
TDCXT
TDGXT
LEY
LDY
STEY
STDY
CZDT
CZXT
CDZT
CXZT
CPDT
SA22-7871-08.book Page 31 Thursday, February 19, 2015 3:46 PM
OpCode
EDAD
EDAE
EDAF
EE
EF
F0
F1
F2
F3
F8
F9
FA
FB
FC
FD
Mnemonic
CPXT
CDPT
CXPT
PLO
LMD
SRP
MVO
PACK
UNPK
ZAP
CP
AP
SP
MP
DP
31
SA22-7871-08.book Page 32 Thursday, February 19, 2015 3:46 PM
Condition Codes
Condition Code 
Mask Bit Value 
General Instructions
Add
Add Halfword
Add Halfword Immediate
Add High
Add Immediate
Add Immediate High
Add Logical
Zero
Zero
Zero
Zero
Zero
Zero
Zero, no carry
Add Logical High
Zero, no carry
0
8
Add Logical Immediate
Zero, no carry
Add Logical with Carry
Zero, no carry
Add Logical with Signed Immediate
Add Logical with Signed Immediate High
AND
AND Immediate
Zero, no carry
Checksum
Zero, no carry
Zero
ANDed bits
zero
Checksum
complete
Cipher Message
Normal completion
Cipher Message with Chaining Normal completion
Cipher Message with Cipher
Normal comFeedback
pletion
Cipher Message with Counter Normal completion
Cipher Message with Output
Normal comFeedback
pletion
Compare
Equal
Compare and Form Codeword Equal
Compare and Swap
Compare and Swap and Store
Compare Double and Swap
Compare Halfword
Compare Halfword Immediate
Compare Halfword Relative
Long
Compare High
Compare Immediate
Compare Immediate High
Compare Logical
Compare Logical Characters
under Mask
Compare Logical High
Compare Logical Immediate
Compare Logical Immediate
High
Compare Logical Long
Compare Logical Long
Extended
Equal
Equal
Equal
Equal
Equal
Equal
1
4
2
2
3
1
< Zero
< Zero
< Zero
< Zero
< Zero
< Zero
Not zero, no
carry
Not zero, no
carry
Not zero, no
carry
Not zero, no
carry
Not zero, no
carry
Not zero, no
carry
Not zero
ANDed bits
not zero
—
> Zero
> Zero
> Zero
> Zero
> Zero
> Zero
Zero, carry
Overflow
Overflow
Overflow
Overflow
Overflow
Overflow
Not zero, carry
Zero, carry
Not zero, carry
Zero, carry
Not zero, carry
Zero, carry
Not zero, carry
Zero, carry
Not zero, carry
Zero, carry
Not zero, carry
—
—
—
—
—
Verification
mismatch
Verification
mismatch
Verification
mismatch
Verification
mismatch
Verification
mismatch
First op low
First op low
and ctl = 0, or
first op high
and ctl = 1
Not equal
Not equal
Not equal
First op low
First op low
First op low
—
First op high
First op high
and ctl = 0, or
first op low
and ctl = 1
—
—
—
First op high
First op high
First op high
CPU-determined completion
Partial completion
Partial completion
Partial completion
Partial completion
Partial completion
—
—
—
—
—
—
—
—
—
—
—
—
Equal
Equal
Equal
Equal
Equal, or
Mask is zero
Equal
Equal
Equal
First op low
First op low
First op low
First op low
First op low
First op high
First op high
First op high
First op high
First op high
—
—
—
—
—
First op low
First op low
First op low
First op high
First op high
First op high
—
—
—
Equal
Equal
First op low
First op low
First op high
First op high
Compare Logical Long Unicode
Equal
First op low
First op high
Compare Logical Relative
Long
Compare Logical String
Equal
First op low
First op high
—
CPU-determined completion
CPU-determined completion
—
Equal
First op low
First op high
First op low
Last bytes
equal
First op high
Last bytes
unequal
Compare Relative Long
Equal
Compare until Substring Equal Equal substring
32
z/Architecture Reference Summary
CPU-determined completion
—
CPU-determined completion
SA22-7871-08.book Page 33 Thursday, February 19, 2015 3:46 PM
Condition Code 
Mask Bit Value 
Compression Call
0
8
Second op
end
Compute Intermediate MesNormal comsage Digest
pletion
Compute Last Message Digest Normal completion
Compute Message Authentica- Normal comtion Code
pletion
Convert UTF-16 to UTF-32
Data processed
1
4
First op end, —
not second op
end
—
—
—
Verification
mismatch
First op full
Convert UTF-16 to UTF-8
Data processed
First op full
Convert UTF-32 to UTF-16
Data processed
First op full
Convert UTF-32 to UTF-8
Data processed
First op full
Convert UTF-8 to UTF-16
Data processed
First op full
Convert UTF-8 to UTF-32
Data processed
First op full
Exclusive OR
Exclusive OR Immediate
Zero
XORed bits
zero
No one bit
found
All zero, or
mask is zero
Not zero
XORed bits
not zero
—
Zero
Zero
Zero
Zero
Operand
lengths equal
Operand
lengths equal
< Zero
< Zero
< Zero
—
First op
shorter
First op
shorter
Find Leftmost One
Insert Characters under Mask
Load and Test
Load Complement
Load Negative
Load Positive
Move Long
Move Long Extended
Move Long Unicode
Operand
lengths equal
Move String
—
OR
OR Immediate
Zero
ORed bits
zero
Perform Cryptographic Compu- Normal comtation
pletion
Perform Locked Operation (test Equal
bit zero)
Perform Locked Operation (test
bit one)
Perform Pseudorandom Number Operation
Population Count
Rotate Then AND Selected
Bits
Rotate Then Exclusive OR
Selected Bits
Rotate Then Insert Selected
Bits
Rotate Then OR Selected Bits
Search String, Search String
Unicode
Code valid
Normal completion
Zero
Selected bits
zero
Selected bits
zero
Zero
Selected bits
zero
—
Leftmost bit =
1
2
2
3
1
CPU-determined completion
Partial completion
—
Partial completion
—
Partial completion
Invalid low
CPU-detersurrogate
mined completion
Invalid low
CPU-detersurrogate
mined completion
Invalid UTF-32 CPU-detercharacter
mined completion
Invalid UTF-32 CPU-detercharacter
mined completion
Invalid UTF-8 CPU-detercharacter
mined completion
Invalid UTF-8 CPU-detercharacter
mined completion
—
—
—
—
One bit found
—
Not zero, but
with leftmost
bit = 0
> Zero
> Zero
—
> Zero
First op longer
—
—
Overflow
—
Overflow
Overlap
First op longer CPU-determined completion
First op
First op longer CPU-detershorter
mined completion
Second op
—
CPU-determoved
mined completion
Not zero
—
—
ORed bits not —
—
zero
Verification
—
Partial commismatch
pletion
First op not
First op equal, —
equal
third op not
equal
—
—
Code invalid
—
—
Not zero
Selected bits
not zero
Selected bits
not zero
< zero
—
—
Partial completion
—
—
—
—
> zero
—
—
—
Character not
found
CPU-determined completion
Selected bits
not zero
Character
found
33
SA22-7871-08.book Page 34 Thursday, February 19, 2015 3:46 PM
Condition Code 
Mask Bit Value 
0
8
See Note
Set Program Mask4
Shift Left (Double / Single)
Zero
Shift Right (Double / Single)
Zero
Store Clock (STCK, STCKE or Set state
STCKF)
1
4
See Note
< Zero
< Zero
Not-set state
2
2
See Note
> Zero
> Zero
Error state
Store Facility List Extended
—
—
< Zero
< Zero
< Zero
Not zero, borrow
Not zero, borrow
Not zero, borrow
Not zero, borrow
31-bit mode
Leftmost bit
one
Mixed 0's and
1's
Mixed 0's and
1's and leftmost bit zero
Mixed 0's and
1's and leftmost bit zero
—
—
> Zero
> Zero
> Zero
Zero, no borrow
Zero, no borrow
Zero, no borrow
Zero, no borrow
—
—
3
1
See Note
Overflow
—
Stopped state
or not operational
Incomplete list
stored
Overflow
Overflow
Overflow
Not zero, no
borrow
Not zero, no
borrow
Not zero, no
borrow
Not zero, no
borrow
64-bit mode
—
—
All ones
Subtract
Subtract Halfword
Subtract High
Subtract Logical
Complete list
stored
Zero
Zero
Zero
—
Subtract Logical High
—
Subtract Logical Immediate
—
Subtract Logical with Borrow
Zero, borrow
Test Addressing Mode
Test and Set
24-bit mode
Leftmost bit
zero
Test under Mask (TM)
All zeros, or
mask is zero
Test under Mask (TMH, TMHH, All zeros or
TMHL, TML, TMLH, TMLL) mask is zero
Mixed 0's and
1's and leftmost bit one
Test under Mask High, Low
All zeros or
Mixed 0's and
mask is zero
1's and leftmost bit one
Transaction Begin
Successful
—
Transaction End
In TX mode
Not in TX
mode
Translate and Test, Translate
All zeros
Not zero, scan Not zero, scan
and Test Reverse
incomplete
complete
Translate and Test Extended, All selected
Nonzero func- —
Translate and Test Reverse function codes tion code
Extended
zero
selected
Translate Extended
Data proFirst op byte
—
cessed
equal test byte
Translate One to One, One to
Two, Two to One, Two to
Two
Unpack ASCII
Unpack Unicode
Update Tree
All ones
All ones
—
—
—
CPU-determined completion
CPU-determined completion
CPU determinded completion
Sign invalid
Sign invalid
Path not complete and
compared register negative
Character not
found
Character
found
—
Sign plus
Sign plus
Compare
equal at current node on
path
Sign minus
Sign minus
Path complete, no
nodes compared equal
—
—
—
< Zero
First op low
< Zero
< Zero
< Zero
< Zero
Sign invalid
> Zero
First op high
> Zero
> Zero
> Zero
> Zero
Digit invalid
Zero and Add
Zero
Equal
Zero
Zero
Zero
Zero
Digits and sign
valid
Zero
< Zero
> Zero
Overflow
—
—
—
Overflow
Overflow
Sign and digit
invalid
Overflow
Floating-Point
Instructions
Add
Add Normalized
Add Unnormalized
Compare (BFP)
Compare (HFP)
Compare and Signal
Compare Biased Exponent
Convert BFP to HFP
Convert HFP to BFP
Convert to Fixed
Zero
Zero
Zero
Equal
Equal
Equal
Equal
Zero
Zero
Zero
< Zero
< Zero
< Zero
First op low
First op low
First op low
First op low
< Zero
< Zero
< Zero
> Zero
> Zero
> Zero
First op high
First op high
First op high
First op high
> Zero
> Zero
> Zero
NaN
—
—
Unordered
—
Unordered
Unordered
Special case
Special case
Special case
Decimal Instructions
Add Decimal
Compare Decimal
Edit
Edit and Mark
Shift and Round Decimal
Subtract Decimal
Test Decimal
34
z/Architecture Reference Summary
SA22-7871-08.book Page 35 Thursday, February 19, 2015 3:46 PM
Condition Code 
Mask Bit Value 
Convert to Logical
Convert to Packed
Convert to Zoned
Divide to Integer
Load and Test (BFP)
Load and Test (HFP)
Load Complement (BFP)
Load Complement (HFP)
Load Negative (BFP)
Load Negative (HFP)
Load Positive (BFP)
Load Positive (HFP)
Perform Floating-Point Operation (T=0)
Perform Floating-Point Operation (T=1)
Subtract
Subtract Normalized
Subtract Unnormalized
Test Data Class
Test Data Group
0
8
1
4
Zero
Zero
Zero
Remainder
complete,
quotient normal
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Normal result
< Zero
< Zero
< Zero
Remainder
complete,
quotient overflow or NaN
< Zero
< Zero
< Zero
< Zero
< Zero
< Zero
—
—
Nontrap
exception
Function valid —
Zero
Zero
Zero
Zero (no
match)
Zero (no
match)
Vector-Facility Instructions
Load Count to Block Boundary = 16
All elements
Vector Compare Equal5
equal
5 All elements
Vector Compare High Logical
high
All elements
Vector Compare High5
high
Vector Element Compare
Equal
Vector Element Compare Logi- Equal
cal
Vector Find Any Element
None equal,
zero found
Equal5
2
2
3
1
> Zero
Special case
> Zero
Special case
> Zero
Special case
Remainder
Remainder
incomplete,
incomplete,
quotient nor- quotient overmal
flow or NaN
> Zero
NaN
> Zero
—
> Zero
NaN
> Zero
—
—
NaN
—
—
> Zero
NaN
> Zero
—
Trap exception —
—
< Zero
< Zero
< Zero
One (match)
> Zero
> Zero
> Zero
—
Function
invalid
NaN
—
—
—
One (match)
—
—
—
Some elements equal
Some elements high
Some elements high
Low
Low
—
—
< 16
No element
equal
No element
high
No element
high
—
—
—
—
High
High
Equal element found,
no zeros if
ZS=1
Zero found
Equal eleVector Find Element Equal5
ment found,
no zeros
Vector Find Element Not
Zero found
Not equal element found,
Equal5
less than
Vector FP Compare And Signal Elements
First element
Scalar
equal
low
All elements
Mix of equal
Vector FP Compare Equal5
equal
and unequal
(or unordered) elements
Vector FP Compare High Or
All elements  Mix of  and <
5
Equal
All elements > Mix of > and 
Vector FP Compare High5
Equal element found
and zero
found
Equal element found,
and zero
Not equal
found, greater
than
First element
high
—
Vector FP Compare Scalar
First element
high
—
Vector FP Test Data Class
Immediate
Elements
equal
Match
Vector Pack Logical Saturate5
Zero element
found
No saturation
Vector Pack Saturate5
No saturation
Vector Isolate String5
Vector String Range Compare5 Zero found
First element
low
Selected bit 1
for some (but
not all) elements
—
—
—
—
Some saturated
Some saturated
At least one in At least one in
ranges, no
ranges, zero
zero
found
No equal elements, no
zeros
Not equal, no
zeros
Equal, no zero
Elements
unordered
All elements
not equal (or
unordered)
All elements <
(or unordered)
All elements 
(or unordered)
Elements
unordered
No match
All elements
nonzero
All saturated
All saturated
No ranges
match, no
zeros
35
SA22-7871-08.book Page 36 Thursday, February 19, 2015 3:46 PM
Condition Code 
Mask Bit Value 
Vector Test Under Mask
0
8
All zeros or
mask zero
Control Instructions
Compare and Replace DAT
Table Entry
Compare and Swap and Purge
Diagnose1
Extract Stacked State
Insert Address Space Control
Load Address Space Parameters
Load Page-Table-Entry
Address
Load PSW3
Load PSW Extended3
Load Real Address2
Move Page
Move to Primary
Move to Secondary
Move with Key
Move with Optional Specifications
Page In
Mixed
—
3
1
All ones
Equal
Not equal
—
—
Equal
See note
Branch state
entry
Primaryspace
mode
Not equal
See note
Program call
state entry
Secondaryspace
mode
Primary not
available
—
See note
—
—
See note
—
Access register mode
Homespace
mode
Secondary not
authorized or
not available
Address
Address
Invalid bit on
returned;
returned;
in RTE or
STE.P=0
STE.P=1
STE.
See note
See note
See note
See note
See note
See note
Translation
Segment table Page table
available
entry invalid
entry invalid
Data moved
First op
Second op
invalid, both
invalid
valid in ES,
locked, or ES
error
Length  256 —
—
Length  256 —
—
Length  256 —
—
Length  4096 —
—
Spaceswitch
event
Parameters
loaded
Operation
completed
Page Out
Operation
completed
Perform Timing Facility Func- Function pertion
formed
Perform Topology Function
Initiated
Program Return
See note
Reset Reference Bit Extended Ref = 0, Chg =
0
See note
Resume Program3
Set Clock
Set
Signal Processor
Accepted
Store System Information
Info provided
Test Access
ALET = 0
Test Block
Test Protection
Usable
Fetch and
store allowed
Input/Output
Instructions
Cancel Subchannel
Clear Subchannel
Halt Subchannel
Modify Subchannel
Reset Channel Path
Resume Subchannel
36
Function
started
Function
started
Function
started
Function executed
Function
started
Function
started
1
4
2
2
ES data error
—
—
—
—
—
Exception
condition
exists.
See note
See note
See note
—
Length > 256
Length > 256
Length > 256
Length > 4096
ES block not
available
ES data error —
ES block not
available
—
—
Function not
available
—
Rejected
—
See note
See note
See note
Ref = 0, Chg = Ref = 1, Chg = Ref = 1, Chg =
1
0
1
See note
See note
See note
Secure
—
Not operational
Status stored Busy
Not operational
—
—
Info not available
ALET uses
ALET uses
ALET = 1 or
DUALD
PSALD
causes ART
exception
Unusable
—
—
Fetch allowed; No fetch or
Translation not
no store
store allowed available
allowed
Nonintermedi- Busy
ate status
pending
Status pend- Busy
ing
—
Busy
Status pending
Not operational
Not operational
Not operational
Not operational
Not operational
Not applicable Not operational
z/Architecture Reference Summary
SA22-7871-08.book Page 37 Thursday, February 19, 2015 3:46 PM
Condition Code 
Mask Bit Value 
Start Subchannel
Store Channel Report Word
Store Subchannel
Test Pending Interruption
Test Subchannel
0
8
Function
started
CRW stored
SCHIB stored
1
4
Status pending
Zeros stored
—
2
2
Interruption
not pending
IRB stored;
not status
pending
Interruption
—
code stored
IRB stored;
—
status pending
Busy
—
—
3
1
Not operational
—
Not operational
—
Not operational
Notes:
1 For Diagnose, the resulting condition code is model-dependent.
2
For Load Real Address, condition code 3 is set if address-space-control element not available,
region-table entry outside table or invalid, segment-table entry outside table, or, for LRA in 24or 31-bit mode when bits 0-32 of entry address not all zeros, segment- or page-table entry
invalid.
3 For Load PSW, Load PSW Extended, and Resume Program, the condition code is loaded
from the condition-code field of the second operand.
4 For Set Program Mask, the condition code is loaded from bit positions 2 and 3 of the first operand.
5
For various vector-facility instructions, the condition code is optionally set based on the CS
control in the M5 field of the instruction.
Assembler Instructions
Function
Option control
Mnemonic
*PROCESS
ACONTROL
Meaning
Specify assembler options
Dynamically modify options
Data definition
CCW
CCW0
CCW1
DC
DS
Define channel command word
Define format-0 channel command word
Define format-1 channel command word
Define constant
Define storage
Program
sectioning
and linking
ALIAS
AMODE
CATTR
COM
CSECT
CXD
DSECT
DXD
ENTRY
EXTRN
LOCTR
RMODE
RSECT
START
WXTRN
XATTR
Rename external symbol
Specify addressing mode
Define class/part name and attributes
Identify common control section
Identify control section
Cumulative length of external dummy section
Identify dummy section
Define external dummy section
Identify entry-point symbol
Identify external symbol
Specify multiple location counters
Specify residence mode
Identify read-only control section
Start assembly
Identify weak external symbol
Declare external symbol attributes
Base register
assignment
DROP
USING
Drop base address register
Use base address and register
Control of
listing
AEJECT
ASPACE
CEJECT
EJECT
PRINT
SPACE
TITLE
Start new page in macro definition
Space lines in macro definition
Conditional start new page
Start new page
Control listing contents
Space listing
Identify assembly output
Program control
ADATA
CNOP
COPY
END
EQU
EXITCTL
ICTL
ISEQ
LTORG
Provide data for SYSADATA file
Conditional no operation
Copy predefined source coding
End assembly
Equate symbol
Program control data for I/O exits
Input format control
Input sequence checking
Begin literal pool
37
SA22-7871-08.book Page 38 Thursday, February 19, 2015 3:46 PM
Function
Mnemonic
OPSYN
ORG
POP
PUNCH
PUSH
REPRO
Meaning
Equate operation code
Set location counter
Restore ACONTROL, PRINT, or USING status
Punch a record
Save current ACONTROL, PRINT, or USING status
Reproduce following record
Conditional
assembly
ACTR
AGO
AIF
AINSERT
ANOP
AREAD
GBLA
GBLB
GBLC
LCLA
LCLB
LCLC
MHELP
MNOTE
SETA
SETAF
SETB
SETC
SETCF
Conditional assembly branch counter
Unconditional branch
Conditional branch
Create input record
Assembly no operation
Assign input record to SETC symbol
Define global SETA symbol
Define global SETB symbol
Define global SETC symbol
Define local SETA symbol
Define local SETB symbol
Define local SETC symbol
Trace macro flow
Generate message
Set arithmetic variable symbol
Set arithmetic variable symbol from external function
Set binary variable symbol
Set character variable symbol
Set character variable symbol from external function
Macro definition
MACRO
MEND
MEXIT
Source: SC26-4940.
Macro definition header
Macro definition trailer
Macro expansion exit
Extended-Mnemonic Instructions for Branch on Condition
Extended Mnemonic*
(RX or RR)
B or BR
NOP or NOPR
Meaning
Unconditional branch
No operation
Machine Instr.*
(RX or RR)
BC or BCR 15,
BC or BCR 0,
After
Compare
Instructions
(A:B)
BH or BHR
BL or BLR
BE or BER
BNH or BNHR
BNL or BNLR
BNE or BNER
Branch on A High
Branch on A Low
Branch on A Equal B
Branch on A Not High
Branch on A Not Low
Branch on A Not Equal B
BC or BCR 2,
BC or BCR 4,
BC or BCR 8,
BC or BCR 13,
BC or BCR 11,
BC or BCR 7,
After
Arithmetic
Instructions
BP or BPR
BM or BMR
BZ or BZR
BO or BOR
BNP or BNPR
BNM or BNMR
BNZ or BNZR
BNO or BNOR
Branch on Plus
Branch on Minus
Branch on Zero
Branch on Overflow
Branch on Not Plus
Branch on Not Minus
Branch on Not Zero
Branch on No Overflow
BC or BCR 2,
BC or BCR 4,
BC or BCR 8,
BC or BCR 1,
BC or BCR 13,
BC or BCR 11,
BC or BCR 7,
BC or BCR 14,
Use
Control
After Test
under Mask
Instruction
BO or BOR
Branch if Ones
BC or BCR 1,
BM or BMR
Branch if Mixed
BC or BCR 4,
BZ or BZR
Branch if Zeros
BC or BCR 8,
BNO or BNOR
Branch if Not Ones
BC or BCR 14,
BNM or BNMR
Branch if Not Mixed
BC or BCR 11,
BNZ or BNZR
Branch if Not Zeros
BC or BCR 7,
Source: SC26-4940.
* Second operand, not shown, is D2 (X2, B2) for RX format and R2 for RR format.
Extended-Mnemonic Instructions for Relative-Branch Instructions
Use
General
Branch Rel.
on Condition
Extended
Mnemonic
BRU or J
BRUL or JLU
JNOP*
Meaning
Unconditional Branch Relative
Unconditional Branch Relative
No Operation
Machine
Instr.
BRC 15,I2
BRCL 15,I2
BRC 0,I2
After
Compare
Instructions
BRH or JH*
BRL or JL*
BRE or JE*
Branch Relative on A High
Branch Relative on A Low
Branch Relative on A Equal B
BRC 2,I2
BRC 4,I2
BRC 8,I2
38
z/Architecture Reference Summary
SA22-7871-08.book Page 39 Thursday, February 19, 2015 3:46 PM
Extended
Mnemonic
BRNH or JNH*
BRNL or JNL*
BRNE or JNE*
Meaning
Branch Relative on A Not High
Branch Relative on A Not Low
Branch Relative on A Not Equal B
Machine
Instr.
BRC 13,I2
BRC 11,I2
BRC 7,I2
After
Arithmetic
Instructions
BRP or JP*
BRM or JM*
BRZ or JZ*
BRO or JO*
BRNP or JNP*
BRNM or JNM*
BRNZ or JNZ*
BRNO or JNO*
Branch Relative on Plus
Branch Relative on Minus
Branch Relative on Zero
Branch Relative on Overflow
Branch Relative on Not Plus
Branch Relative on Not Minus
Branch Relative on Not Zero
Branch Relative on No Overflow
BRC 2,I2
BRC 4,I2
BRC 8,I2
BRC 1,I2
BRC 13,I2
BRC 11,I2
BRC 7,I2
BRC 14,I2
After Test
under Mask
Instruction
BRO or JO*
BRM or JM*
BRZ or JZ*
BRNO or JNO*
BRNM or JNM*
BRNZ or JNZ*
Branch Relative if Ones
Branch Relative if Mixed
Branch Relative if Zeros
Branch Relative if Not Ones
Branch Relative if Not Mixed
Branch Relative if Not Zeros
BRC 1,I2
BRC 4,I2
BRC 8,I2
BRC 14,I2
BRC 11,I2
BRC 7,I2
Use
Other Branch
Relative
Instructions
JAS
Branch Relative and Save
BRAS R1,I2
JASL
Branch Relative and Save Long
BRASL R1,I2
JCT
Branch Relative on Count (32)
BRCT R1,I2
JCTG
Branch Relative on Count (64)
BRCTG R1,I2
JXH
Branch Relative on Index High (32)
BRXH R1,R3,I2
JXHG
Branch Relative on Index High (64)
BRXHG R1,R3,I2
JXLE
Br. Rel. on Index Low or Equal (32)
BRXLE R1,R3,I2
JXLEG
Br. Rel. on Index Low or Equal (64)
BRXLG R1,R3,I2
Source: SC26-4940.
* To obtain BRCL instead of BRC, add L at the end of the B mnemonic or insert L after the J of the J
mnemonic. For example, change BRNZ or JNZ to BRNZL or JLNZ.
Extended-Mnemonic Suffixes for Compare-and-Branch, and
Compare-and-Trap Instructions
Suffix Meaning
H
High
L
Low
E
Equal
Explanation:
M3 Value
2
4
8
Suffix
NH
NL
NE
Meaning
Not High
Not Low
Not Equal
M3 Value
13
11
7
These suffixes may be appended to the following mnemonics: CGIB, CGIJ, CGIT, CGRB,
CGRJ, CGRT, CIB, CIJ, CIT, CLFIT, CLGIB, CLGIJ, CLGIT, CLGRB, CLGRJ, CLGRT, CLGT,
CLIB, CLIJ, CLRB, CLRJ, CLRT, CLT, CRB, CRJ, CRT. When the suffix is coded, the M3 operand must be omitted.
Extended-Mnemonic Suffixes for Load/Store-on-Condition
Instructions
Suffix Meaning
O*
One / Overflow
H
High
P*
Plus
L
Low
M*
Minus / Mixed
E
Equal
Z*
Zero
Explanation:
M3 Value
1
2
2
4
4
8
8
Suffix
NO *
NH
NP *
NL
NM *
NE
NZ *
Meaning
Not one / Not overflow
Not High
Not Plus
Not Low
Not Minus / Mixed
Not Equal
Not Zero
M3 Value
14
13
13
11
11
7
7
These suffixes may be appended to the following mnemonics: LOC, LOCG, LOCGHI, LOCGR,
LOCHHI, LOCHI, LOCR, STOC, STOCFH, STOCG. Suffixes marked with an asterisk (*) may not
be available on earlier versions of the High Level Assembler.
Extended-Mnemonic Suffixes for Rotate-Then-Insert / AND / OR /
Exclusive OR-Selected-Bits Instructions
Extended
Mnemonic
RISBGZ
RISBHGZ
Meaning
Set the zero-remaining-bits control (bit 0 of the I4 field) to one.
Set the zero-remaining-bits control (bit 0 of the I4 field) to one.
39
SA22-7871-08.book Page 40 Thursday, February 19, 2015 3:46 PM
Extended
Mnemonic
RISBLGZ
RNSBGT
ROSBGT
RXSBGT
Meaning
Set the zero-remaining-bits control (bit 0 of the I4 field) to one.
Set the test-results control (bit 0 of the I3 field) to one.
Set the test-results control (bit 0 of the I3 field) to one.
Set the test-results control (bit 0 of the I3 field) to one.
Extended-Mnemonics for Vector-Facility Instructions
See z/Architecture Principles of Operation (SA22-7832) Chapters 21-24
CNOP Alignment
Quadword
Doubleword
Fullword
Halfword
Doubleword
Fullword
Halfword
Halfword
Halfword
Fullword
Halfword
Halfword
Fullword
Halfword
Halfword
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
0,4
0,8
0,16
2,4
2,8
2,16
0,4
4,8
4,16
2,4
6,8
6,16
0,4
0,8
8,16
2,4
2,8
10,16
0,4
4,8
12,16
2,4
6,8
14,16
For byte offset and boundary values greater than 16, see IBM High Level Assembler
for z/OS, z/VM & z/VSE Language Reference (SC26-4940).
Summary of Constants
Type
A
AD
B
C
CA
CE
CU
D
DB
DD
DH
E
EB
ED
EH
F
FD
G
H
J
JD
L
LB
LD
LH
LQ
P
Q
QD
QY
R
RD
S
SY
V
VD
X
40
Implied
Length,
Bytes
4
8
Even
8
8
8
8
4
4
4
4
4
8
Even
2
4
8
16
16
16
16
16
4
8
3
4
8
2
3
4
8
-
Default Alignment
Word
Doubleword
Byte
Byte
Byte
Byte
Byte
Doubleword
Doubleword
Doubleword
Doubleword
Word
Word
Word
Word
Word
Doubleword
Byte
Halfword
Word
Doubleword
Doubleword
Doubleword
Doubleword
Doubleword
Quadword
Byte
Word
Doubleword
Halfword
Word
Doubleword
Halfword
Halfword
Word
Doubleword
Byte
Format
Value of address or expression
Value of address or expression
Binary digits
Characters
Characters (ASCII)
Characters (EBCDIC)
Characters, translated to Unicode
Long hex floating point
Long binary floating point
Long decimal floating point
Long hex floating point
Short hex floating point
Short binary floating point
Short decimal floating point
Short hex floating point
Fixed-point binary
Fixed-point binary
Graphic (double-byte) characters
Fixed-point binary
Symbol naming a DXD, DSECT, or class
Symbol naming a DXD, DSECT, or class
Extended hex floating point
Extended binary floating point
Extended decimal floating point
Extended hex floating point
Extended hex floating point
Packed decimal
Symbol naming a DXD, DSECT, or part
Symbol naming a DXD, DSECT, or part
Symbol naming a DXD, DSECT, or part in longdisplacement form
PSECT address value
PSECT address value
Address in base-displacement form
Address in base-and-long-displacement form
Externally defined address value
Externally defined address value
Hexadecimal digits
z/Architecture Reference Summary
Truncation/
Padding
Left
Left
Left
RIght
RIght
RIght
Right
Right
Right
Right
Right
Right
Right
Right
Right
Left
Left
Right
Left
Left
Left
Right
Right
Right
Right
Right
Left
Left
Left
–
Left
Left
–
–
–
–
Left
SA22-7871-08.book Page 41 Thursday, February 19, 2015 3:46 PM
Implied
Length, Default AlignType
Bytes ment
Format
Y
2
Halfword
Value of address or expression
Z
Byte
Zoned decimal
Source: SC26-4940.
Truncation/
Padding
Left
Left
Assigned Storage Locations
Hex
Addr
80-83
84-85
86-87
88-8B
Dec
Addr
128-131
132-133
134-135
136-139
Addr
Type
R
R
R
R
8C-8F
140-143
R
90-93
144-147
R
94-95
96-97
98-9F
A0
148-149
150-151
152-159
160
R
R
R
R
A1
161
R
A2
162
R
A3
163
A/R
A8-AF
B0-B7
B8-BB
168-175
176-183
184-187
R
R
R
BC-BF
C0-C3
188-191
192-195
R
R
C8-CB
E8-EF
F4-F7
F8-FF
100-107
108-10B
10C-10F
110-117
120-12F
130-13F
140-14F
150-15F
160-16F
170-17F
1A0-1AF
1B0-1BF
1C0-1CF
1D0-1DF
1E0-1EF
1F0-1FF
11B0-11B7
11C0-11FF
1200-127F
1280-12FF
1300-130F
200-203
232-239
244-247
248-255
256-263
264-267
268-271
272-279
288-303
304-319
320-335
336-351
352-367
368-383
416-431
432-447
448-463
464-479
480-495
496-511
4528-4535
4544-4607
4608-4735
4736-4863
4864-4879
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A/R
A/R
A/R
1318-131B 4888-4891 A
131C-131F 4892-4895 A/R
Function
External-interruption parameter
CPU address associated with external interruption, or zeros
External-interruption code (see table on page 42)
SVC-interruption identification: 0-12 zeros, 13-14 ILC, 15 zero,
16-31 code
Program-interruption identification: 0-12 zeros, 13-14 ILC, 15
zero, 16-31 code (see table on page 42)
Data-exception code or vector-exception code: 0-23 zeros, 2431 code (for DXC, see table on page 43; for VXC, see table on
page 44)
Monitor-class number: 0-7 zeros, 8-15 number
PER code, ATMID, AI (see table on page 45)
PER address
Exception access identification: 0-3 zeros, 4-7 access-register
number
PER access identification: 0-3 zeros, 4-7 access-register number
Operand access identification (if page-translation exception recognized by MOVE PAGE): 0-3 R1, 4-7 R2
Store-status/machine-check architectural-mode identification: 06 zeros, 7 one
Translation-exception identification (see table on page 43)
Monitor code
Subsystem-identification word: 0-12 zeros, 13-14 SSID,15 one,
16-31 subchannel number
I/O-interruption parameter
I/O-interruption-identification word: 0-1 zeros, 2-4 I/O-interruption subclass, 5-31 zeros
STFL facility list (see “Facility Indications” on page 46)
Machine-check-interruption code (see diagram on page 45)
External-damage code (see diagram on page 46)
Failing-storage address
Enhanced-Monitor Counter-Array Origin
Enhanced-Monitor Counter-Array Size
Enhanced-Monitor Exception Count
Breaking-event address
Restart old PSW
External old PSW
Supervisor-call old PSW
Program old PSW
Machine-check old PSW
Input/output old PSW
Restart new PSW
External new PSW
Supervisor-call new PSW
Program new PSW
Machine-check new PSW
Input/output new PSW
Machine-check-extended-save-area address
Available for programming
Store-status/machine-check floating-point-register save area
Store-status/machine-check general-register save area
Store-status PSW save area or machine-check fixed-logout
area*
Store-status prefix save area
Store-status/machine-check floating-point-control-register save
area
41
SA22-7871-08.book Page 42 Thursday, February 19, 2015 3:46 PM
Hex
Dec
Addr
Addr
Addr
Type Function
1324-1327 4900-4903 A/R Store-status/machine-check TOD-programmable-register save
area
1328-132F 4904-4911 A/R Store-status/machine-check CPU-timer save area
1331-1337 4913-4919 A/R Store-status/machine-check clock-comparator bits 0-55 save
area (zeros at 4912)
1340-137F 4928-4991 A/R Store-status/machine-check access-register save area
1380-13FF 4992-5119 A/R Store-status/machine-check control-register save area
1800-18FF 6144-6399 R
Program-interruption TDB (see diagram on page 68)
A
Absolute address.
R
Real address.
A/R
A if store status; R if machine check.
*
Contents may vary among models; see System Library manuals.
External-Interruption Codes
At real-storage locations 134-135 (86-87 hex)
Code
(Hex)
0040
1004
1005
1007
1200
1201
1202
1406
2401
Condition
Interrupt key
Clock comparator
CPU timer
Warning-track interruption
Malfunction alert
Emergency signal
External call
ETR
Service signal
Program-Interruption Codes
At real-storage locations 142-143 (8E-8F hex)
Code
(Hex)
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
0013
0015
0016
0018
001B
001C
001D
001F
0020
0021
0022
0023
42
Condition
Operation exception
Privileged-operation exception
Execute exception
Protection exception
Addressing exception
Specification exception
Data exception
Fixed-point-overflow exception
Fixed-point-divide exception
Decimal-overflow exception
Decimal-divide exception
HFP-exponent-overflow exception
HFP-exponent-underflow exception
HFP-significance exception
HFP-floating-point-divide exception
Segment-translation exception
Page-translation exception
Translation-specification exception
Special-operation exception
Operand exception
Trace-table exception
Transaction constraint
Vector-processing
Space-switch event
HFP-square-root exception
PC-translation-specification exception
AFX-translation exception
ASX-translation exception
LX-translation exception
EX-translation exception
z/Architecture Reference Summary
ILC Set
1 2
2
2
1 2
1 2
0 1 2
1 2
1 2
1 2
2
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1 2
1 2
0 1 2
2
2
1 2
1 2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Instr.
Ending
S
S
S
S T
S T
C
S
C
S T
C
C
S
C
S
C
C
C
S
N
N
S
S
S
N
S
S
C
S
S
N
N
N
N
SA22-7871-08.book Page 43 Thursday, February 19, 2015 3:46 PM
Code
(Hex)
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F
0030
0031
0032
0033
0034
0038
0039
003A
003B
0040
0080
0080
0119
0200
C
ILC
N
S
T
Condition
Primary-authority exception
Secondary-authority exception
LFX-translation exception
LSX-translation exception
ALET-specification exception
ALEN-translation exception
ALE-sequence exception
ASTE-validity exception
ASTE-sequence exception
Extended-authority exception
LSTE sequence
ASTE instance
Stack-full exception
Stack-empty exception
Stack-specification exception
Stack-type exception
Stack-operation exception
ASCE-type exception
Region-first-translation exception
Region-second-translation exception
Region-third-translation exception
Monitor event
PER basic event (code may be combined with another code)
PER nullification event
Crypto-operation exception
Transactional-execution-aborted event
Completed
Instruction-length code
Nullified
Suppressed
Terminated
ILC Set
2
1 2
2
2
1 2
1 2
1 2
1 2
1 2
1 2
2
1 2
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
0 1 2
0
2
1 2
3
3
3
3
3
3
3
3
3
3
3
3
3
Instr.
Ending
N
N
N
N
S
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
C
C
N
N
C
Data-Exception Code (DXC)
At real-storage location 147 (93 hex) and in byte 2 of floating-point-control register
Code
(Hex)
00
01
02
03
04
07
08
0B
0C
10
13
18
1B
1C
20
23
28
2B
2C
40
43
80
83
FE
FF
Data Exception
General operand
AFP register
BFP instruction
DFP instruction
Quantum exception
Simulated quantum exception
IEEE inexact and truncated
IXS inexact
IEEE inexact and incremented
IEEE underflow, exact
IXS underflow, exact
IEEE underflow, inexact and truncated
IXS underflow, inexact
IEEE underflow, inexact and incremented
IEEE overflow, exact
IXS overflow, exact
IEEE overflow, inexact and truncated
IXS overflow, inexact
IEEE overflow, inexact and incremented
IEEE division by zero
IXS division by zero
IEEE invalid operation
IXS invalid operation
Vector instruction
Compare-and-trap or load-and-trap instruction
43
SA22-7871-08.book Page 44 Thursday, February 19, 2015 3:46 PM
Vector-Exception Code (VXC)
At real-storage location 147 (93 hex) and in byte 2 of floating-point-control register
Vector Interrupt Code (VIC)
Value
Meaning
0
4
7
0001
IEEE invalid operation
0010
IEEE division by zero
Vector Index (VIX)
0011
IEEE overflow
Index to the leftmost element that recognized the 0100
IEEE underflow
exception
0101
IEEE inexact
VIX
VXC
PER Code, ATMID, and AI
At real-storage locations 150-151
PER Code
0
ATMID
8
AI
14 15
Program-Event-Recording (PER Code)
Bit
Meaning
0
Successful-branching event
1
Instruction-fetching event
2
Storage-alteration event
3
Reserved
4
Store-using-real-address event
5
Zero-address-detection event
6
Transaction-end event
7
Instruction-fetch-nullification event
Addressing and-Translation-Mode ID (ATMID)
Bit
Meaning
8
PSW bit 31
9
ATMID-validity bit
10
PSW bit 32
11
PSW bit 5
12-13
PSW bits 16-17
PER ASCE Identification (AI)
14-15
0 - primary; 1 - AR-specified;
2 - secondary; 3 - home
Translation-Exception Identification
At real-storage locations 168-175 (A8-AF hex)
Interruption
Code
(Hex)
Exception or Event
Format of Information Stored*
0004
Protection
If 61 zero: rest unpredictable
If 61 one: suppression, 0-51 address; 52-53 accessexception fetch/store indication; if DAT was on, 60
one if access-list-conrolled protection, 62-63 ASCE
identification, rest unpredictable, location 160 valid;
if DAT was off, rest unpredictable
0010
Segment translation
0-51 address; 52-53 access-exception fetch/store
indication; 54-61 unpredictable, 62-63 ASCE identification
0011
Page translation
0-51 address; 52-53 access-exception fetch/store
indication; 54-60 unpredictable, if 61, zero, not
MOVE PAGE; if 61 one, MOVE PAGE (see location
162); 62-63 ASCE identification
001C
Space switch
From primary-space mode: 32 old primary-spaceswitch-event control, 33-47 zeros, 48-63 old PASN
From home-space mode: 32 home-space-switchevent control, 33-63 zeros
0020
AFX translation
32-47 zeros, 48-63 address-space number
0021
ASX translation
32-47 zeros, 48-63 address-space number
0022
LX translation
32-43 zeros, 44-63 program-call number
0023
EX translation
32-43 zeros, 44-63 program-call number
0024
Primary authority
32-47 zeros, 48-63 address-space number
0025
Secondary authority
32-47 zeros, 48-63 address-space number
0026
0027
LFX translation
LSX translation
When bit 44 is 0: 32-43 zeros, 44-63 program-call
number. When bit 44 is 1, 32-63 program-call number
44
z/Architecture Reference Summary
SA22-7871-08.book Page 45 Thursday, February 19, 2015 3:46 PM
Interruption
Code
(Hex)
Exception or Event
Format of Information Stored*
0038
ASCE type
0-51 address; 52-53 access-exception fetch/store
indication; 54-61 unpredictable, 62-63 ASCE identification
0039
Region-first translation
0-51 address; 52-53 access-exception fetch/store
indication; 54-61 unpredictable, 62-63 ASCE identification
003A
Region-second translation
0-51 address; 52-53 access-exception fetch/store
indication; 54-61 unpredictable, 62-63 ASCE identification
003B
Region-third translation
0-51 address; 52-53 access exception fetch/store
indication; 54-61 unpredictable, 62-63 ASCE identification
* Bits 0-31 (bytes 168-171) unchanged if not described.
Machine-Check Interruption Code
At real-storage locations 232-239 (E8-EF hex)
S P S
C E
D
C
C
S
D WM P I
E
G C
D D R 0 D D 0 G W P SP K 0 0 B 0 SE C KE S P S M A FA 0 C FP R R 0 ST
0
4
8
14
16
24
26
31
I A
P
C
E R DA 0 0 0 0 0 0 0 R FCAP 0 CT C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32
Bit
0
1
2
4
5
7
8
9
10
11
14
16
17
18
19
20
21
22
23
24
26
27
28
29
31
32
33
34
42
43
44
46
47
35
40
42
46
48
56
63
Meaning
(SD) System damage
(PD) Instruction-processing damage
(SR) System recovery
(CD) Timing-facility damage
(ED) External damage
(DG) Degradation
(W) Warning
(CP) Channel report pending
(SP) Service-processor damage
(CK) Channel-subsystem damage
(B) Backed up
(SE) Storage error uncorrected
(SC) Storage error corrected
(KE) Storage-key error uncorrected
(DS) Storage degradation
(WP) PSW-MWP validity
(MS) PSW mask and key validity
(PM) PSW program-mask and condition-code validity
(IA) PSW-instruction-address validity
(FA) Failing-storage-address validity
(EC) External-damage-code validity
(FP) Floating-point-register validity
(GR) General-register validity
(CR) Control-register validity
(ST) Storage logical validity
(IE) Indirect storage error
(AR) Access-register validity
(DA) Delayed-access exception
(PR) TOD-programmable-register validity
(FC) Floating-point-control-register validity
(AP) Ancillary report
(CT) CPU-timer validity
(CC) Clock-comparator validity
45
SA22-7871-08.book Page 46 Thursday, February 19, 2015 3:46 PM
External-Damage Code
At real-storage address 244-247 (F4-F7 hex)
X X
0 0 0 0 0 0 0 0 N F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
8 9 10
Bit
8
9
16
24
31
Meaning
(XN) Expanded storage not operational
(XF) Expanded-storage control failure
Facility Indications
The first 32 facility indications are stored at real-storage locations 200-203 (C8-CB
hex) by STFL; the specified number of doublewords of facility indications are stored at
second-operand location by STFLE.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
13
14
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
39
46
Meaning when Bit is One
The instructions marked “N3” in the instruction-summary figures in Chapters 7 and 10 are
installed.
The z/Architecture architectural mode is installed.
The z/Architecture architectural mode is active. When this bit is zero, the ESA/390 architectural mode is active.
The DAT-enhancement facility is installed in the z/Architecture architectural mode. The
DAT-enhancement facility includes the INVALIDATE DAT TABLE ENTRY (IDTE) and
COMPARE AND SWAP AND PURGE (CSPG) instructions.
INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation
by selectively clearing TLB segment-table entries when a segment-table entry or entries
are invalidated. IDTE also performs the clearing-by-ASCE operation. Unless bit 4 is one,
IDTE simply purges all TLBs. Bit 3 is one if bit 4 is one.
INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation
by selectively clearing TLB region-table entries when a region-table entry or entries are
invalidated. Bits 3 and 4 are ones if bit 5 is one.
The ASN-and-LX reuse facility is installed in the z/Architecture architectural mode.
The store-facility-list-extended facility is installed.
The enhanced-DAT facility 1 is installed in the z/Architecture architectural mode.
The sense-running-status facility is installed in the z/Architecture architectural mode.
The conditional-SSKE facility is installed in the z/Architecture architectural mode.
The configuration-topology facility is installed in the z/Architecture architectural mode.
The IPTE-range facility is installed in the z/Architecture architectural mode.
The nonquiescing key-setting facility is installed in the z/Architecture architectural mode.
The extended-translation facility 2 is installed.
The message-security assist is installed.
The long-displacement facility is installed in the z/Architecture architectural mode.
The long-displacement facility has high performance. Bit 18 is one if bit 19 is one.
The HFP-multiply-add/subtract facility is installed.
The extended-immediate facility is installed in the z/Architecture architectural mode.
The extended-translation facility 3 is installed in the z/Architecture architectural mode.
The HFP-unnormalized-extension facility is installed in the z/Architecture architectural
mode.
The ETF2-enhancement facility is installed.
The store-clock-fast facility is installed in the z/Architecture architectural mode.
The parsing-enhancement facility is installed in the z/Architecture architectural mode.
The move-with-optional-specifications facility is installed in the z/Architecture architectural
mode.
The TOD-clock-steering facility is installed in the z/Architecture architectural mode.
The ETF3-enhancement facility is installed in the z/Architecture architectural mode.
The extract-CPU-time facility is installed in the z/Architecture architectural mode.
The compare-and-swap-and-store facility is installed in the z/Architecture architectural
mode.
The compare-and-swap-and-store facility 2 is installed in the z/Architecture architectural
mode.
The general-instructions-extension facility is installed in the z/Architecture architectural
mode.
The execute-extensions facility is installed in the z/Architecture architectural mode.
The enhanced-monitor facility is installed in the z/Architecture architectural mode.
The floating-point extension facility is installed in the z/Architecture architectural mode.
Assigned to IBM internal use.
z/Architecture Reference Summary
SA22-7871-08.book Page 47 Thursday, February 19, 2015 3:46 PM
Bit
40
41
42
43
44
45
47
48
49
50
51
52
53
57
66
67
68
73
74
75
76
77
78
80
129
142
Meaning when Bit is One
The set-program-parameters facility is installed in the z/Architecture architectural mode.
The floating-point-support-enhancement facilities (FPR-GR-loading, FPS-sign-handling,
and DFP-rounding) are installed in the z/Architecture architectural mode.
The DFP (decimal-floating-point) facility is installed in the z/Architecture architectural
mode.
The DFP (decimal-floating-point) facility has high performance. Bit 42 is one if bit 43 is
one.
The PFPO instruction is installed in the z/Architecture architectural mode.
The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities,
the interlocked-access facility 1, and the load/store-on-condition facility 1 are installed in
the z/Architecture architectural mode.
The CMPSC-enhancement facility is installed in the z/Architecture architectural mode.
The decimal-floating-point zoned-conversion facility is installed in the z/Architecture architectural mode.
The execution-hint, load-and-trap, miscellaneous-instruction-extensions and processorassist facilities, are installed in the z/Architecture architectural mode.
The constrained transactional-execution facility is installed in the z/Architecture architectural mode. This bit is meaningful only when bit 73 is one.
The local-TLB-clearing facility is installed in the z/Architecture architectural mode.
The interlocked-access facility 2 is installed.
The load/store-on-condition facility 2 and load-and-zero-rightmost-byte facility are
installed in the z/Architecture architectural mode.
The message-security-assist-extension-5 facility is installed in the z/Architecture architectural mode.
The reset-reference-bits-multiple facility is installed in the z/Architecture architectural
mode.
The CPU-measurement counter facility is installed in the z/Architecture architectural
mode.
The CPU-measurement sampling facility is installed in the z/Architecture architectural
mode.
The transactional-execution facility is installed in the z/Architecture architectural mode. Bit
49 is one when bit 73 is one.
The store-hypervisor-information facility is installed in the z/Architecture architectural
mode (see z/VM CP Programming Services [SC24-6179]).
The access-exception-fetch/store-indication facility is installed in the z/Architecture architectural mode.
The message-security-assist-extension-3 facility is installed in the z/Architecture architectural mode.
The message-security-assist-extension-4 facility is installed in the z/Architecture architectural mode.
The enhanced-DAT facility 2 is installed in the z/Architecture architectural mode.
The decimal-floating-point packed-conversion facility is installed in the z/Architecture
architectural mode.
The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
The store-CPU-counter-multiple facility is installed.
47
SA22-7871-08.book Page 48 Thursday, February 19, 2015 3:46 PM
Control Registers
CR
0
0
Bits
8
9
0
30
0
32
33
34
35
36
37
38
39
40
44
45
46
48
49
50
52
53
54
56
57
58
59
61
0-63
1
0-51
54
55
56
2
2
2
3
4
5
6
7
57
58
60-61
62-63
33-57
61
62-63
0-31
32-47
48-63
0-31
32-47
48-63
33-57
32-39
0-63
0-51
54
55
56
58
60-61
62-63
48
Name of Field
Transactional-execution control
Program-interruption filtering override
Warning-track-interruption enablement
Trace TOD-clock control
SSM-suppression control
TOD-clock-sync control
Low-address-protection control
Extraction-authority control
Secondary-space control
Fetch-protection-override control
Storage-protection-override control
Enhanced-DAT-enablement control
ASN-and-LX-reuse control
AFP-register control
Vector enablement control
Malfunction-alert subclass mask
Emergency-signal subclass mask
External-call subclass mask
Clock-comparator subclass mask
CPU-timer subclass mask
Service-signal subclass mask
Unused (See note)
Interrupt-key subclass mask
Unused (See note)
ETR subclass mask
Crypto control
Primary address-space-control element
Primary region-table or segmenttable origin or real-space token origin
Primary subspace-group control
Primary private-space control
Primary storage-alteration-event
control
Primary space-switch-event control
Primary real-space control
Primary designation-type control
Primary table length
Dispatchable-unit-control-table origin
Transaction diagnostic scope
Transaction diagnostic control
Secondary ASTE Instance Number
PSW-key mask
Secondary ASN
Primary ASTE Instance Number
Authorization index
Primary ASN
Primary-ASTE origin
I/O-interruption subclass mask
Secondary address-space-control
element
Secondary region-table or segment-table origin or real-space
token origin
Secondary subspace-group control
Secondary private-space control
Secondary storage-alteration-event
control
Secondary real-space control
Secondary designation-type control
Secondary table length
Associated with
Transactional-execution
Transactional-execution
Init*
0
0
Virtual machines
0
TOD clock
SSM instruction
TOD clock
Low-address protection
Instruction authorization
Instruction authorization
Key-controlled protection
Key-controlled protection
Dynamic address translation
Instruction authorization
Floating point
Vector facility for z/Architecture
External interruptions
External interruptions
External interruptions
External interruptions
External interruptions
External interruptions
External interruptions
Cryptography
Dynamic address translation
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
Dynamic address translation
0
Subspace groups
Dynamic address translation
Program-event recording
0
0
0
Program interruptions
Dynamic address translation
Dynamic address translation
Dynamic address translation
Access-register translation
0
0
0
0
0
Transactional execution
Transactional execution
Instruction authorization
Instruction authorization
Address spaces
Instruction authorization
Instruction authorization
Address spaces
Access-register translation
I/O interruptions
Dynamic address translation
0
0
0
0
0
0
0
0
0
0
0
Dynamic address translation
0
Subspace groups
Dynamic address translation
Program-event recording
0
0
0
Dynamic address translation
Dynamic address translation
Dynamic address translation
0
0
0
External interruptions
z/Architecture Reference Summary
SA22-7871-08.book Page 49 Thursday, February 19, 2015 3:46 PM
CR
8
9
Bits
16-31
32-47
48-63
32
33
34
36
37
38
39
10
11
12
13
40
41
42
0-63
0-63
0
1
2-61
62
63
0-63
0-51
54
55
56
14
15
57
58
60-61
62-63
32
33
35
36
37
38
39
42
44
45-63
0-60
Name of Field
Enhanced-monitor masks
Extended authorization index
Monitor masks
Successful-branching-event mask
Instruction-fetching-event mask
Storage-alteration-event mask
Store-using-real-address-event
mask
Zero-address-detection-event
mask
Transaction-end-event mask
Instruction-fetching-nullificationevent mask
Branch-address control
Event-suppression control
Storage-alteration-space control
PER starting address
PER ending address
Branch-trace control
Mode-trace control
Trace-entry address
ASN-trace control
Explicit-trace control
Home address-space-control element
Home region-table or segmenttable origin or real-space token origin
Home subspace-group control
Home private-space control
Home storage-alteration-event control
Home space-switch-event control
Home real-space control
Home designation-type control
Home table length
Unused (See note)
Unused (See note)
Channel-report-pending
subclass mask
Recovery subclass mask
Degradation subclass mask
External-damage subclass mask
Warning subclass mask
TOD-clock-control-override control
ASN-translation control
ASN-first-table origin
Linkage-stack-entry address
Associated with
MONITOR CALL instruction
Access-register translation
MONITOR CALL instruction
Program-event recording
Program-event recording
Program-event recording
Program-event recording
Init*
0
0
0
0
0
0
0
Program-event recording
0
Program-event recording
Program-event recording
0
0
Program-event recording
Program-event recording
Program-event recording
Program-event recording
Program-event recording
Tracing
Tracing
Tracing
Tracing
Tracing
Dynamic address translation
0
0
0
0
0
0
0
0
0
0
0
Dynamic address translation
0
Subspace groups
Dynamic address translation
Program-event recording
0
0
0
Program interruptions
Dynamic address translation
Dynamic address translation
Dynamic address translation
I/O machine-check handling
0
0
0
0
1
1
0
Machine-check handling
Machine-check handling
Machine-check handling
Machine-check handling
TOD clock
Instruction authorization
ASN translation
Linkage-stack operations
0
0
1
0
0
0
0
0
* Value after initial CPU reset.
Note: This bit is not used but is initialized to one for consistency with the
System/370 definition.
Floating-Point-Control (FPC) Register
Masks
Flags
DXC (see page 43)
or
VCX (see page 44)
I I I I I I
S S S S S S
M M M M M M 0 0 F F F F F F 0 0
i z o u x q
i z o u x q
0
Bit
0
1
2
3
4
8
16
0
24
DRM
0
BRM
31
Meaning
(IMi) IEEE-invalid-operation mask
(IMz) IEEE-division-by-zero mask
(IMo) IEEE-overflow mask
(IMu) IEEE-underflow mask
(IMx) IEEE-inexact mask
49
SA22-7871-08.book Page 50 Thursday, February 19, 2015 3:46 PM
5
8
9
10
11
12
13
16-23
25-27
29-31
50
(IMq) Quantum-exception mask
(SFi) IEEE-invalid-operation flag
(SFz) IEEE-division-by-zero flag
(SFo) IEEE-overflow flag
(SFu) IEEE-underflow flag
(SFx) IEEE-inexact flag
(SFq) Quantum-exception flag
(DXC) Data-exception code (see table on page 43)
(DRM) DFP Rounding mode
000 Round to nearest with ties to even
001 Round toward 0
010 Round toward +
011 Round toward -
100 Round to nearest with ties away from 0
101 Round to nearest with ties toward 0
110 Round away from 0
111 Round to prepare for shorter precision
(BRM) BFP Rounding mode
000 Round to nearest
001 Round toward 0
010 Round toward +
011 Round toward -
111 Round to prepare for shorter precision
z/Architecture Reference Summary
SA22-7871-08.book Page 51 Thursday, February 19, 2015 3:46 PM
Program-Status Word (PSW)
z/Architecture PSW
Program R
E
0 0 0 0 0 0
Mask I
A
0 R 0 0 0 T I E PSW Key 0 M W P AS CC
0
5
8
12
16
18
20
24 25
31
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A
32
63
Bits 0-31 of Instruction Address
64
95
Bits 32-63 of Instruction Address
96
Bit
1
5
6
7
12
13
14
15
16-17
18-19
20
21
22
24
23
31/32
127
Meaning
(R) Program-event-recording mask
(T = 1) DAT mode
(I) Input/output mask
(E) External mask
Zero indicates z/Architecture
(M) Machine-check mask
(W = 1) Wait state
(P = 1) Problem state
xx Real mode (T = 0)
00 – Primary-space mode (T = 1)
01 – Access-register mode (T = 1)
10 – Secondary-space mode (T = 1)
11 – Home-space mode (T = 1)
(CC) Condition code
Fixed-point-overflow mask
Decimal-overflow mask
HFP-exponent-underflow mask
Reserved for IBM use
HFP-significance mask
Extended/basic addressing mode
00 – 24-bit mode
01 – 31-bit mode
10 – Invalid
11 – 64-bit mode
ESA/390 PSW
Program
0 0 0 0 0 0 0 0
Mask
0 R 0 0 0 T I E PSW Key 1 M W P AS CC
0
A
5
8
12
16
20
24
31
Instruction Address
32
Bit
12
32
18
63
Meaning
One indicates ESA/390
(A = 1) 31-bit addressing mode
51
SA22-7871-08.book Page 52 Thursday, February 19, 2015 3:46 PM
Dynamic Address Translation
Virtual-Address Format
 11 
 11 
RFX
 11 
RSX
0
11
 11 
RTX
22
 8 
SX
 12 
PX
33
BX
44
52
63
RX
Field
RX
RFX
RSX
RTX
SX
PX
BX
Meaning
Region index (region = 2G bytes)
Region first index
Region second index
Region third index
Segment index (segment = 1M bytes)
Page index (page = 4K bytes)
Byte index
Address-Space-Control Element (ASCE)
Region-Table or Segment-Table Designation (RTD or STD)
Region-Table or Segment-Table Origin
GP S XR
0
52 54
Bit
54
55
56
57
58
60-61
DT DL
58 60
63
Meaning
(G) Subspace-group control
(P) Private-space control
(S) Storage-alteration-event control
(X) Space-switch-event control
(R) Real-space control (R = 0)
(DT) Designation-type control
11 Region-first-table
10 Region-second-table
01 Region-third-table
00 Segment-table
(DL) Designation length (× 4K bytes)
62-63
Real-Space Designation (RSD)
Real-Space Token Origin
GPSXR
0
52 54
58
63
Bit
Meaning
58
(R) Real-space control (R = 1)
Note: Other bits are as in RTD or STD.
Table Values
Increment
Incr.
Size
Incr.
Entries
Max.
Size
Max.
Entries
Regions
Bytes
Region First
1-4
4KB
512
16KB
2K
8G
16E =16×260
Region Second
1-4
4KB
512
16KB
2K
4M
8P = 8×250
Region Third
1-4
4KB
512
16KB
2K
2K
4T = 4×240
Segment
1-4
4KB
512
16KB
2K
1
2G = 2×230
1
2KB
256
2KB
256
—
1M =
Table
Page
52
Max Table Maps
z/Architecture Reference Summary
220
SA22-7871-08.book Page 53 Thursday, February 19, 2015 3:46 PM
Region-Table Entry (RTE)
Region-First-Table Entry (RFTE)
Region-Second-Table Origin
P TF I
0
TT TL
52 54 56 58 60
63
Region-Second-Table Entry (RSTE)
Region-Third-Table Origin
P TF I
0
TT TL
52 54 56 58 60
63
Region-Third-Table Entry (RTTE, FC=0)
C
F
P TF I TT TL
R
C
Segment-Table Origin
0
52 54 56 58 60
63
Region-Third-Table Entry (RTTE, FC-1)
A
F
ACC F P
V
C
Region-Frame Absolute Address (RFAA)
0
Bit
47
48-51
52
53
54
56-57
58
59
60-61
62-63
33
48
52 54
I
C
TT
R
58 60
63
Meaning
(AV) Access-control (ACC) and fetch-protection (F) validity bit
(ACC) Access-control bits
(F) Fetch-protection bit
(FC) Format control
(P) DAT protection bit
(TF) Table offset (for next-lower-level table)
(I) Invalid bit (for set of regions in RFTE or RSTE, or for region in RTTE
(CR) Common-region bit
(TT) Table-type bits (for this table)
11=Region first table
10=Region second table
01=Region third table
(TL) Table length (for next-lower-level table) (× 4K bytes)
Segment-Table Entry (STE, FC=0)
F
P
C
Page-Table Origin
0
54
I C TT
58 60
63
Segment-Table Entry (STE, FC=1)
A
F
ACC F P
V
C
Segment-Frame Absolute Address
0
Bit
47
48-51
52
53
54
58
59
60-61
44
48
52 54
I
C
TT
S
58 60
63
Meaning
(AV) Access-control (ACC) and fetch-protection (F) validity bit
(ACC) Access-control bits
(F) Fetch-protection bit
(FC) Format control
(P) DAT-protection bit
(I) Segment-invalid bit
(CS) Common-segment bit
(TT) Table-type bits (for this table): 00=Segment table
53
SA22-7871-08.book Page 54 Thursday, February 19, 2015 3:46 PM
Page-Table Entry (PTE)
Page-Frame Real Address
0 I P0 / / / / / / / /
0
52
Bit
53
54
56
63
Meaning
(I) Page-invalid bit
(P) Page-protection bit
ASN Translation
Address-Space Number (ASN)
ASN-FirstTable Index
ASN-SecondTable Index
0
10
15
ASN-First-Table Entry
I
ASN-Second-Table Origin
0 1
Bit
0
0 0 0 0 0 0
26
31
Meaning
(I) AFX-invalid bit
ASN-Second-Table Entry (ASTE)
Byte
(Hex)
0 I
Authority-Table Origin
B
0 1
4
31
Authorization Index
0
CR
AA
Authority-Table Length
16
28
31
Address-Space-Control Element (ASCE=RTD/STD/RSD) Part 1
8
Region or Segment-Table Origin or Real-Space Token Origin
0
31
RTD or STD Part 2 (R=0)
C
Region or Seg.-Table Origin (Continued)
0
GPSXR
20
22
20
22
26
DT DL
28
31
RSD Part 2 (R=1)
C
Real-Space Token Origin (Continued)
0
10
GPSXR
26
Primary-Space Access-List Origin
0 1
14
31
ALL
25
31
ASN-Second-Table-Entry Sequence Number
0
31
Linkage-Table Designation (LTD)
18 V
Linkage-Table Origin
0 1
54
LTL
25
z/Architecture Reference Summary
31
SA22-7871-08.book Page 55 Thursday, February 19, 2015 3:46 PM
Linkage-First-Table Designation (LFTD)
18 V
Linkage-First-Table Origin
LFTL
0 1
24
1C

24
31
Available for Programming
0
31
28 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
0
31
2C
ASTEIN
0
31
30

3C
0
31
Byte.Bit
Meaning
0.0
(I) ASX-invalid bit
0.31
(B) Base-space bit
4.30
(CA) Controlled-ASN bit
4.31
(RA) Reusable-ASN bit
10.25-31 (ALL) Access-list length (× 128 bytes)
18.0
(V) Subsystem-linkage control
18.25-31 (LTL) Linkage-table length (× 128 bytes)
18.24-31 (LFTL) Linkage-first-table length (× 256 bytes)
PC-Number Translation
Program-Call Number (20-Bit)
Linkage Index
32
Entry Index
44
56
63
Program-Call Number (32-Bit, Bit 44=0)
0
32
LFX
44
LSX
51
Entry Index
56
63
Program-Call Number (32-Bit, Bit 44=1)
LFX1
1
32
LFX2
44
LSX
51
Entry Index
56
63
Linkage-Table Entry (LTE)
I
0 1
Bit
0
26-31
Entry-Table Origin
ETL
26
31
Meaning
(I) LX-invalid bit
(ETL) Entry-table length (× 128 bytes)
55
SA22-7871-08.book Page 56 Thursday, February 19, 2015 3:46 PM
Linkage-First-Table Entry (LFTE)
I
Linkage-Second-Table Origin
0 1
Bit
0
24
31
Meaning
(I) LFX-invalid bit
Linkage-Second-Table Entry (LSTE)
I
Entry-Table Origin
ETL
0 1
26
31
LSTESN
32
Bit
0
26-31
63
Meaning
(I) LSX-invalid bit
(ETL) Entry-table length (× 128 bytes)
Entry-Table Entry (ETE)
Byte
(Hex)
If Bit 10.1 (G) Is Zero
0
0
31
4 A
Bits 33-62 of Entry Instruction Address
P
0 1
31
If Bit 10.1 (G) Is One
0
Bits 0-31 of Entry Instruction Address
0
31
4
Bits 32-62 of Entry Instruction Address
P
0
8
31
Authorization Key Mask
0
C
Address-Space Number
16
31
16
31
Entry Key Mask
0
10 T G RI K M E C S
0
3
14
EK
8
Entry Ext. Auth. Index
12
16
ASN-Second-Table-Entry Address
0 1
26
18
31
Bits 0-31 of Entry Parameter
0
31
1C
Bits 32-63 of Entry Parameter
0
Byte.Bit
31
Meaning
4.0
(A) Entry addressing mode
4.31
(P) Entry problem state
10.0
(T) PC-type bit (zero: basic; one: stacking)
10.1
(G) Entry extended addressing mode
56
31
z/Architecture Reference Summary
SA22-7871-08.book Page 57 Thursday, February 19, 2015 3:46 PM
10.2
(RI) Reserved for IBM use
10.3
(K) PSW-key control (zero: unchanged; one: replace if stacking
10.4
(M) PSW-key-mask control (zero: Or; one: replace if stacking)
10.5
(E) EAX control (zero: unchanged; one: replace if stacking)
10.6
(C) Address-space-control control
10.7
(S) Secondary-ASN control
10.8-11
(EK) Entry key
Access-Register Translation
Access-List-Entry Token (ALET)
0 0 0 0 0 0 0 P
0
Bit
7
8-15
ALESN
Access-List-Entry Number
7 8
16
31
Meaning
(P) Primary-list bit (zero: use DUCT; one: use primary ASTE)
(ALESN) Access-list-entry sequence number
Dispatchable-Unit-Control Table (DUCT)
Byte
(Hex)
0
Base-ASTE Origin
0 1
4
31
S
A
Subspace-ASTE Origin
0
31
8
0
C
31
Subspace-ASTE Sequence Number
0
10
31
Dispatchable-Unit Access-List Origin
ALL
0 1
14
25
PSW-Key Mask
0
16
31
PSW Key
R
A
P
24
28
31
18
0
31
1C / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
0
31
In 24-Bit or 31-Bit Addressing Mode
20
0
24
31
Bits 33-63 of Return Address
0 1
31
57
SA22-7871-08.book Page 58 Thursday, February 19, 2015 3:46 PM
In 64-Bit Addressing Mode
20
Bits 0-31 of Return Address
0
31
24
Bits 32-63 of Return Address
0
31
0
31
28
2C
Trap-Control-Block Address
E
0
29 31
30

3C
0
31
Byte.Bit
Meaning
4.0
(SA) Subspace-active bit
10.25-31 (ALL) Access-list length (× 128 bytes)
14.28
(RA) Reduced-authority bit
14.31
(P) Problem-state bit
2C.31
(E) TRAP-enabled bit
///
Available for programming
Access-List Entry (ALE)
I
F
P
O
0 1
6
Access-List-Entry Authorization Index
(ALEAX)
ALESN
8
16
31
32
63
ASN-Second-Table-Entry Origin (ASTEO)
64
90
95
ASN-Second-Table-Entry Sequence Number (ASTESN)
96
Bit
0
6
7
8-15
127
Meaning
(I) ALEN-invalid bit
(FO) Fetch-only bit
(P) Private bit
(ALESN) Access-list-entry sequence number
Linkage-Stack Entries
Entry Descriptor
U
0 1
Entry Type
Section ID
8
Remaining Free Space
16
31
48
63
Next-Entry Size
32
58
z/Architecture Reference Summary
SA22-7871-08.book Page 59 Thursday, February 19, 2015 3:46 PM
Bit
0
1-7
Meaning
(U) Unstack-suppression bit
Entry type:
Header entry = 0001001 binary
Trailer entry = 0001010 binary
Branch state entry = 0001100 binary
Program-call state entry = 0001101 binary
Available for program use = 1xxxxxx binary
Header Entry (Entry Type 0001001)
Bits 0-31 of Backward Stack-Entry Address
0
31
Bits 32-60 of Backward Stack-Entry Address
B
32
61
63
Entry Descriptor (First Half)
64
95
Entry Descriptor (Second Half)
96
127
Bit
63
Meaning
(B) Backward stack-entry validity bit
Trailer Entry (Entry Type 0001010)
Bits 0-31 of Forward-Section-Header Address
0
31
Bits 32-60 of Forward-Section-Header Address
F
32
61
63
Entry Descriptor (First Half)
64
95
Entry Descriptor (Second Half)
96
127
Bit
63
Meaning
(F) Forward-section validity bit
Branch State Entry (Entry Type 0001100) and
Program-Call State Entry (Entry Type 0001101)
Byte
(Hex)
0

78
Contents of General Registers 0-15
63
0
80
PSW-Key Mask
0
88
Secondary ASN
16
Ext Auth Index
32
Primary ASN
48
63
Bits 0-63 of Program-Status Word
0
63
59
SA22-7871-08.book Page 60 Thursday, February 19, 2015 3:46 PM
In a Branch State Entry Made in 24-Bit or 31-Bit Mode
90
A
0
Bits 33-63 of Branch Address
32 33
63
In a Branch State Entry Made in 64-Bit Mode
90
Bits 0-62 of Branch Address
1
0
63
In a Program-Call State Entry Made on a Call to 24-Bit or 31-Bit Mode
90
Called-Space ID
0
0
Numeric part of PC Number
32
44
63
In a Program-Call State Entry Made on a Call to 64-Bit Mode
90
Called-Space ID
1
0
Numeric part of PC Number
32
98
44
63
Modifiable Area
0
63
A0
All Zeros
0
63
A8
Bits 64-127 of Program-Status Word
0
63
B0
SASTEIN
PASTEIN
0
63
0
63
B8

D8
E0

118
Contents of Access Registers 0-15
0
63
120
Entry Descriptor
0
Byte.Bit
90.32
63
Meaning
(A) Addressing mode (in branch state entry)
Trapping
Trap Control Block
Byte
(Hex)
0
PR
0
13
31
4
8
0
60
31
z/Architecture Reference Summary
SA22-7871-08.book Page 61 Thursday, February 19, 2015 3:46 PM
C
Trap-Save-Area Address
0 1
29
31
10
0
31
14
Trap-Program Address
0 1
31
18 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
1C / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
0
31
20

3C
0
31
Byte.Bit
0.13
Meaning
(P) PSW control (zero: PSW.31 must be zero, ESA/390 PSW stored; one: z/Architecture
PSW stored)
(R) General-register control (zero: bits 32-63 stored; one: bits 0-63 stored)
Available for programming
0.14
///
Trap Save Area
Byte
(Hex)
Trap Flags
0 EW
Zeros
IL
0 1 2
Zeros
13
4
31
15
Zeros
Bits 33-63 of Second-Operand Address of TRAP4
8
C
Access Register 15
0 1
31
PSW Values
If z/Architecture PSW Stored
Prog
Mask
10 0 U 0 0 0 U U U U U U U 0 U W P AS CC
14
B
A
E
A
24
31
Zeros
18
Bits 0-31 of Instruction Address
1C
Bits 32-63 of Instruction Address
0 1 2
0 0 0 0 0 0 0
5
12
14
16
18
20
61
SA22-7871-08.book Page 62 Thursday, February 19, 2015 3:46 PM
If ESA/390 PSW Stored
Prog
Mask
10 0 U 0 0 0 U U U U U U U 1 U W P AS CC
14 A
0 0 0 0 0 0 0 0
Bits 33-63 of Instruction Address
18
Zeros
1C
Zeros
0 1 2
5
12
20

9C
14
16
18
20
24
31
General Registers 0-15
A0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
A4 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
A8

FC
Unchanged
0
31
Byte.Bit
0.0
0.1
0.13-14
10-1F
U
///
Meaning
(E) TRAP was target of EXECUTE
(W) TRAP is TRAP4 (not TRAP2)
(IL) Instruction-length code
PSW values (see PSW on page 51)
Unpredictable
Available for programming
Trace-Entry Formats
Identification of Trace Entries
Trace-Entry Bits
0-7
8-11
Trace Entry
12-15
00000000
Type
Format
Branch
1
Set Secondary ASN
1
00100001
Program Call
11
00100010
Program Call
21
00010000
000N
00100001
0
Program Call
31
00100010
0
Program Call
41
00100010
100E
Program Call
51
00100010
101E
Program Call
61
00100011
111E
Program Call
71
00110001
000N
Program Transfer
1
00110001
100N
Program Transfer
2
00110010
0000
Program Return
1
00110010
0010
Program Return
2
00110010
1000
Program Return
4
00110010
1010
Program Return
5
00110010
110N
Program Transfer
3
00110011
0011
Program Return
3
00110011
1011
Program Return
6
00110011
1100
Program Return
7
00110011
1110
Program Return
8
62
z/Architecture Reference Summary
SA22-7871-08.book Page 63 Thursday, February 19, 2015 3:46 PM
Trace-Entry Bits
0-7
8-11
Trace Entry
12-15
00110100
1111
Type
Format
Program Return
9
01000001
Branch in Subspace Group
1
01000010
Branch in Subspace Group
2
Mode Switch
2
01010001
0010
01010001
0011
Mode Switch
1
01010001
1010
Mode-Switching Branch
1
01010001
1011
Mode-Switching Branch
2
01010010
0110
Mode Switch
3
01010010
1100
Branch
3
01010010
1111
Mode-Switching Branch
3
0111
0
Trace
1
0111
1
Trace
2
1
1
E
N
Branch
Format-1 and -2 entries are made when the ASN-and-LX-reuse facility (ALRF)
is not enabled. Entries of formats 3-7 are made when the facility is enabled.
Indicates, when one, that the extended-addressing-mode bit, PSW bit 31, was
set to one.
Indicates, when one, that an entry was made because of PTI or SSAIR.
Branch
F1 (Branch, RP, or TRAP2/4 to 24-Bit Mode)
00000000
0
Bits 40-63 of Branch Address
8
31
F2 (Branch, RP, or TRAP2/4 to 31/64-Bit Mode)
1
Bits 33-63 of Branch Address
0
31
F3 (Branch, RP, or TRAP2/4 to 64-Bit Mode)
010100101100
0
8
All Zeros
Bits 0-31 of Branch Address
12
32
63
Bits 32-63 of Branch Address
64
95
Note: “Branch” is BAKR, BALR, BASR, BASSM, BSA, or BSG.
Branch in Subspace Group (if ASN Tracing on)
F1 (in 24/31-Bit Mode)
0 1 0 0 0 0 0 1P
0
Bits 9-31 of ALET
A
8
Bits 33-63 of Branch Address
32
63
F2 (in 64-Bit Mode)
0 1 0 0 0 0 1 0P
0
Bits 9-31 of ALET
Bits 33-63 of Branch Address
8
32
63
Bits 32-63 of Branch Address
64
95
63
SA22-7871-08.book Page 64 Thursday, February 19, 2015 3:46 PM
Mode Switch
F1 (BASSM, BSM, PC, PR, RP, or SAM64 from 24/31-Bit to 64-Bit Mode)
010100010011
0
8
All Zeros
A
12
Updated Instruction Address
32
63
F2 (BASSM, BSM, PC, PR, RP, SAM24/31 from 64-Bit to 24/31-Bit Mode)
010100010010
0
8
All Zeros
Bits 32-63 of Updated Inst. Address
12
32
63
F3 (BASSM, BSM, PC, PR, RP, SAM24/31 from 64-Bit to 24/31-Bit Mode)
010100100110
0
8
All Zeros
Bits 0-31 of Updated Inst. Address
12
32
63
Bits 32-63 of Updated Inst. Address
64
95
Mode-Switching Branch
F1 (BASSM or RP from 64-Bit to 24/31-Bit Mode)
010100011010
0
8
All Zeros
A
12
Branch Address
32
63
F2 (BASSM or RP from 24/31-Bit to 64-Bit Mode)
010100011011
0
8
All Zeros
Bits 32-63 of Branch Address
12
32
63
F3 (BASSM or RP from 24/31-Bit to 64-Bit Mode)
010100101111
0
8
All Zeros
Bits 0-31 of Branch Address
12
32
63
Bits 32-63 of Branch Address
64
95
Program Call
F1 (in 24/31-Bit Mode, ALRF Not Enabled)
00100001
PSW
Key
0
8
All Zeros
A
12
Bits 33-62 of Return Address
32
P
63
F2 (in 64-Bit Mode, ALRF Not Enabled)
00100010
PSW
Key
0
8
All Zeros
Bits 0-31 of Return Address
12
32
Bits 32-62 of Return Address
64
63
P
95
F3 (in 24/31-Bit Mode, ALRF Enabled, 20-Bit PC Number)
00100001
PSW Bits 1-19 of 20-Bit PC Num0
A
Key
ber
0
8
64
12
Bits 33-62 of Return Address
32
z/Architecture Reference Summary
P
63
SA22-7871-08.book Page 65 Thursday, February 19, 2015 3:46 PM
F4 (in 64-Bit Mode, ALRF Enabled, 20-Bit PC Number)
00100010
PSW
0
Key
0
8
Bits 1-19 of 20-Bit PC
Number
Bits 0-31 of Return Address
12
32
Bits 32-62 of Return Address
64
63
P
95
F5 (in 24/31-Bit Mode, ALRF Enabled, 32-Bit PC Number)
00100010
PSW
1 0 0E
Key
0
8
12
All Zeros
A
16
Bits 33-62 of Return Address
32
P
63
32-Bit PC Number
64
95
F6 (in 64-Bit Mode, ALRF Enabled, 32-Bit PC Number, Bits 0-31 of Return Address
All Zeros)
00100010
PSW
1 0 1E
Key
0
8
12
All Zeros
Bits 32-62 of Return Address
16
32
P
63
32-Bit PC Number
64
95
F7 (in 64-Bit Mode, ALRF Enabled, 32-Bit PC Number, Bits 0-31 of Return Address
Not All Zeros)
00100011
PSW
1 1 1E
Key
0
8
12
All Zeros
Bits 0-31 of Return Address
16
32
Bits 32-62 of Return Address
P
64
63
32-Bit PC Number
96
127
Program Return
F1 (in 24/31-Bit to 24/31-Bit Mode)
00110010
PSW
0000
Key
0
8
A
12
New PASN
A
16
Bits 33-62 of Return Address
32
P
63
Bits 33-63 of Updated Inst. Address
64
95
F2 (in 64-Bit to 24/31-Bit Mode)
00110010
PSW
0010
Key
0
8
12
New PASN
A
16
32
Bits 33-62 of Return Address
P
63
Bits 32-63 of Updated Inst. Address
64
95
65
SA22-7871-08.book Page 66 Thursday, February 19, 2015 3:46 PM
F3 (in 64-Bit to 24/31-Bit Mode)
00110011
PSW
0011
Key
0
8
12
New PASN
A
16
Bits 33-62 of Return Address
32
P
63
Updated Instruction Address
64
127
F4 (in 24/31-Bit to 64-Bit Mode)
00110010
PSW
1000
Key
0
8
A
12
New PASN
Bits 32-62 of Return Address
16
32
P
63
Bits 33-63 of Updated Inst. Address
64
95
F5 (in 64-Bit to 64-Bit Mode)
00110010
PSW
1010
Key
0
8
12
New PASN
Bits 32-62 of Return Address
16
32
P
63
Bits 32-63 of Updated Inst. Address
64
95
F6 (in 64-Bit to 64-Bit Mode)
00110011
PSW
1011
Key
0
8
12
New PASN
Bits 32-62 of Return Address
16
32
P
63
Updated Instruction Address
64
127
F7 (in 24/31-Bit to 64-Bit Mode)
00110011
PSW
1100
Key
0
8
12
New PASN
Bits 0-31 of Return Address
16
32
Bits 32-62 of Return Address
PA
64
63
Updated Instruction Address
96
127
F8 (in 64-Bit to 64-Bit Mode)
00110011
PSW
1110
Key
0
8
12
New PASN
16
Bits 32-62 of Return Address
64
66
Bits 0-31 of Return Address
32
P
63
Bits 32-63 of Updated Inst. Address
96
z/Architecture Reference Summary
127
SA22-7871-08.book Page 67 Thursday, February 19, 2015 3:46 PM
F9 (in 64-Bit to 64-Bit Mode)
00110100
PSW
1111
Key
0
8
12
New PASN
Bits 0-31 of Return Address
16
32
Bits 32-62 of Return Address
P
64
63
Bits 0-31 of Updated Inst. Address
96
127
Bits 32-63 of Updated Inst. Address
128
159
Program Transfer
F1 (in 24/31-Bit Mode)
00110001
PSW
0 0 0N
Key
0
8
12
New PASN
Bits 32-63 of R2 Before
16
32
63
F2 (in 64-Bit Mode, Bits 0-31 of R2 All Zeros)
00110001
PSW
1 0 0N
Key
0
8
12
New PASN
Bits 32-63 of R2 Before
16
32
63
F3 (in 64-Bit Mode, Bits 0-31 of R2 Not All Zeros)
00110001
PSW
1 0 0N
Key
0
8
12
New PASN
Bits 0-31 of R2 Before
16
32
63
Bits 32-63 of R2 Before
64
95
Set Secondary ASN
F1
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0N
0
8
New SASN
16
31
Trace
F1 (TRACE)
0111 N 00000000
0
8
12
TOD-Clock Bits 16-63
16
63
TRACE Operand
64
(R1) - (R3)
96
4N+16
67
SA22-7871-08.book Page 68 Thursday, February 19, 2015 3:46 PM
F2 (TRACG)
0111 N 10000000
0
8
12
TOD-Clock Bits 0-47
16
63
TOD-Clock Bits 48-79
TRACE Operand
64
96
127
(R1) - (R3)
128
8N+24
Bit
Meaning
4-7
(N) One less than the number of registers in the trace entry.
Operand of Store Clock
Bits 0-63 of
Time-of-Day (TOD) Clock
0
63
Note: Bit 51 of the TOD clock corresponds to one microsecond.
Operand of Store Clock Extended
Zeros
0
Programmable
Field
Time-of-Day (TOD) Clock
8
112
127
Note: Bit 51 of the TOD clock (bit 59 of the operand) corresponds to one microsecond.
68
z/Architecture Reference Summary
SA22-7871-08.book Page 69 Thursday, February 19, 2015 3:46 PM
Transaction Diagnostic Block (TDB)
TBEGIN-specified TDB is the operand of the TBEGIN instruction when B1  0;
Program-interruption TDB is at real locations 6,144 - 6,399.
Byte
0 Format
Flags
TND
Transaction Abort Code1
8
16
Conflict Token
24
Aborted Transaction Instruction Address
EAID2
32
DXC2
Program Interruption Identification2
40
Translation-Exception Identification2
48
Breaking-Event Address2
56
Reserved
128
General Registers at Abort
248
0
8
16
32
48
63
Explanation:
1
Transaction abort codes:
2 – External interruption
4 – Nonfiltered program interruption
5 – Machine-check interruption
6 – I/O interruption
7 – Fetch overflow
8 – Store overflow
9 – Fetch conflict
10 – Store conflict
2
11 – Restricted instruction
12 – Filtered program interruption
13 – Nesting depth exceeded
14 – Cache fetch-related condition
15 – Cache store-related condition
16 – Cache other condition
255 – Miscellaneous condition
>255 – TABORT instruction
Field is stored only in the TBEGIN-specified TDB; otherwise, the field is reserved. The
program interruption identification is only stored for program-interruption conditions. The
EAID and translation-exception identification are stored only for access-list-controlled or DAT
protection, ASCE-type, page translation, region-first translation, region-second translation,
region-third translation, and segment translation program-interruption conditions. The DXC is
stored only for data program-exception conditions.
TND Transaction nesting depth
69
SA22-7871-08.book Page 70 Thursday, February 19, 2015 3:46 PM
70
z/Architecture Reference Summary
SA22-7871-08.book Page 71 Thursday, February 19, 2015 3:46 PM
Operation-Request Block (ORB)
Command-Mode ORB
Word
0
Interruption Parameter
1
Key
SCMY F P I AUBH T
2 0
3
LPM
LD0 0 0 0 0 X
Channel-Program Address
Reserved
CSS Priority
CU Priority
4
Reserved
5
Reserved
6
Reserved
Reserved
Reserved
7
0
8
16
24
31
Transport-Mode ORB
Word
0
Interruption Parameter
1
Key
0 0 0 0 0 0 0 0 0 B 0 0
2 0
3
LPM
0 0 0 0 0 0 0 X
Channel-Program Address
Reserved
CSS Priority
Reserved for Pgm.
4
Reserved
5
Reserved
6
Reserved
Reserved
Reserved
7
0
Word.Bit
1.0-3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16-23
1.24
1.25
1.31
3.0-7
3.16-23
8
16
24
31
Meaning
(Key) Subchannel key
(S) Suspend control
(C) Streaming-mode control
(M) Modification control
(Y) Synchronization control
(F) CCW-format control
(P) Prefetch control
(I) Initial-status-interruption control
(A) Address-limit-checking control
(U) Suppress-suspended-interruption control
(B) Channel-Program Type
(H) Format-2-IDAW control
(T) 2K-IDAW control
(LPM) Logical-path mask
(L) Incorrect-length-suppression mode
(D) Modified-CCW-indirect-data-addressing control
(X) ORB-extension control
Channel-subsystem priority
Control-unit priority
71
SA22-7871-08.book Page 72 Thursday, February 19, 2015 3:46 PM
Channel-Command Word (CCW)
Format-0 CCW
Command Code
0
Data Address
8
31
Flags
32
Byte Count
40
Bit
32
33
34
35
36
37
38
39
48
63
Meaning
(CD) Causes use of data-address portion of next CCW
(CC) Causes use of command code and data address of next CCW
(SLI) Causes suppression of possible incorrect-length indication
(Skip) Suppresses transfer of information to main storage
(PCI) Causes an intermediate-interruption condition to occur
(IDA) Causes bits 8-31 of CCW to specify location of first IDAW
(Suspend) Causes suspension before execution of this CCW
(MIDA) Causes bits 8-31 of CCW to specify location of first MIDAW
Format-1 CCW
Command Code
0
Flags
8
0
Byte Count
16
32
Bit
8
9
10
11
12
13
14
15
31
Data Address
63
Meaning
(CD) Causes use of data-address portion of next CCW
(CC) Causes use of command code and data address of next CCW
(SLI) Causes suppression of possible incorrect-length indication
(Skip) Suppresses transfer of information to main storage
(PCI) Causes an intermediate-interruption condition to occur
(IDA) Causes bits 33-63 of CCW to specify location of first IDAW
(Suspend) Causes suspension before execution of this CCW
(MIDA) Causes bits 33-63 of CCW to specify location of first MIDAW
Indirect-Data-Address Word (IDAW)
Format-1 IDAW
0
Data Address
0 1
31
Format-2 IDAW
Bits 0-31 of Data Address
0
31
Bits 32-63 of Data Address
32
72
63
z/Architecture Reference Summary
SA22-7871-08.book Page 73 Thursday, February 19, 2015 3:46 PM
Modified-CCW-Indirect-Data-Address Word (MIDAW)
Reserved
0
31
Reserved
32
Flags
Count
40
48
63
Bits 0-31 of Data Address
64
95
Bits 32-63 of Data Address
96
127
Bit
40
41
42
43-47
Meaning
Last MIDAW
Skip
Data-transfer-interruption control
Reserved
Transport Control Word (TCW)
Word
0
F 0 0 0 0 0 0
1
Reserved
Flags
TCCBL
RW
Reserved
2
Output-Data Address
3
4
Input-Data Address
5
6
Transport-Status-Block Address
7
8
Transport-Command-Control-Block Address
9
10
Output Count
11
Input Count
12
Reserved
14
15
Interrogate-TCW Address
0
Word.Bit
0.0-1
0.13
0.14
0.15
0.16-17
1.8-13
1.14
1.15
2
8
14 1516
24
31
Meaning
Format
Input transport-indirect-data addressing (TIDA)
Transport-command-control-block TIDA
Output TIDA
TIDAW Format
(TCCBL) Transport-Command-Control-Block Length
(R) Read Operations
(W) Write Operations
73
SA22-7871-08.book Page 74 Thursday, February 19, 2015 3:46 PM
Transport-Indirect-Data-Address Word (TIDAW)
Flags
Reserved
0
8
31
Count
32
48
63
Bits 0-31 of Data Address
64
95
Bits 32-63 of Data Address
96
127
Bit
0
1
2
3
4
5-7
Meaning
Last TIDA
Skip
Data-transfer-interruption control
(TTIC) TIDAW Transfer In Channel
Insert CBC Control
Reserved
Transport Command Control Block (TCCB)
Word
0
Transport-Command-Area Header
(TCAH)
3
4
Transport-Command Area
(TCA)
N
N+1
Transport-Command-Area Trailer
(TCAT)
N+
(2 or 3)
0
31
Transport Command Area Header (TCAH)
Word
0
Format
Reserved
Reserved
1
2
Reserved
Service-Action Code
Priority
Reserved
3
0
Word.Bit
1.24-31
74
TCAL
8
16
Meaning
(TCAL) Transport-Command-Area Length
z/Architecture Reference Summary
24
31
SA22-7871-08.book Page 75 Thursday, February 19, 2015 3:46 PM
Transport-Command Area (TCA) and
Transport-Command-Area Extension (TCAX)
Word
0
DCW
1
2
DCW
or
Control Data for Previous DCW

DCW
or
Control Data for Previous DCW
N
Reserved (TCAX only; not present in TCA)
Y
0
31
Device-Command Word (DCW)
Command Code
0
Flags
8
Reserved
16
Control-Data Count
24
31
Count
32
63
Bit
9
10
Meaning
(CC) Causes use of next DCW
(SLI) Suppresses incorrect-length indication
Interrogate TCA
Word
0
Interrogate DCW
1
2
Interrogate Data
N
0
31
75
SA22-7871-08.book Page 76 Thursday, February 19, 2015 3:46 PM
Interrogate Data
Word
0
Format
RC
1
PAM
PIM
2
Flags
RCQ
LPM
Timeout
Reserved
Reserved
3
4
Time
5
6
Program Identifier
7
8
Program-Dependent Data
N
0
Word.Bit
0.8-15
0.16-23
0.24-31
1.0-7
1.8-15
2.0-7
8
16
24
31
Meaning
(RC) Reason code
0 Interrogate reason not specified
1 Timeout
(RCQ) Reason-code qualifier
0 Interrogate reason qualifier not specified
1 Primary
2 Secondary
(LPM) Logical-path mask
(PAM) Path-available mask
(PIM) Path-installed mask
Flags
0 Multipath mode
1 Program path recovery
2 Critical
Transport Command Area Trailer (TCAT)
Word
0
Reserved
1
Write Count or Transport Count
2
Read Count (or not present)
0
31
CBC-Offset Block (COB)
Word
0
CBC Offset 0
1
CBC Offset 1
2
.
.
.
N
CBC Offset N
Reserved
Y
0
76
31
z/Architecture Reference Summary
SA22-7871-08.book Page 77 Thursday, February 19, 2015 3:46 PM
Transport Status Block (TSB)
Word
0
Transport-Status Header
2
3
Transport-Status Area
15
0
31
Transport Status Header (TSH)
Word
0
Length
Flags
1
DCW Offset
Count
Reserved
2
0
Word.Bit
0.8
0.9
0.10
0.11
0.13-15
8
16
31
Meaning
DCW-offset field valid
Count field valid
Cache miss
Time fields valid
Transport-Status Area (TSA) Format
0 TSA contents have no meaning
1 I/O-status TSA
2 Device-detected-program-check TSA
3 Interrogate TSA
I/O-Status TSA
Word
0
Device Time
1
Defer Time
2
Queue Time
3
Device-Busy Time
4
Device-Active-Only Time
5
Additional Data
(if present)
12
0
31
77
SA22-7871-08.book Page 78 Thursday, February 19, 2015 3:46 PM
Device-Detected-Program-Check TSA
Word
0
Reserved
Reason Code
1
Reason-Code Qualifier
4
5
Sense Data
(if present)
12
0
Word.Bit
0.24-31
78
24
31
Meaning
(RC) Reason Code
0 No information
1 TCCB transport failure
(RCQ) Reason-code-qualifier byte 0 (1.0-7)
0
No additional information
1
TCCB transport size error
2
TCCB CBC error
2 Invalid CBC detected on output data
RCQ word 0: Offset of first output-data byte for which error was detected
RCQ word 1: Offset of last output-data byte for which error was detected
3 Incorrect TCCB length specification
RCQ byte 0
0
No additional information
1
TCAL value not 8 greater than TCW TCCBL value
2
TCAL value is less than 20 or greater than 252
4 TCAH specification error
RCQ byte 0
0
No additional information
1
Format field specification error
2
Reserved field specification error
3
Service-action-code field specification error
5 DCW specification error
RCQ byte 0
0
No additional information
1
Reserved field specification error
2
Flags field command-chaining specification error
3
Control-data-count field specification error
4
TCOB location error
5
TCOB duplication error
6
TCOB multiple-count error
7
TCOB direction error
8
TCOB chaining error
9
TCOB count-specification error
10 TTE location error
11 TTE duplication error
12 TTE CD-count specification error
13 TTE count specification error
14 TTE direction error:
15 TTE chaining error
16 TCAX specification error
6 Transfer-direction specification error
RCQ byte 0
0
No additional information
1
Read-direction specification error
2
Write-direction field specification error
3
Read-write-conflict specification error
z/Architecture Reference Summary
SA22-7871-08.book Page 79 Thursday, February 19, 2015 3:46 PM
7 Transport-count specification error
RCQ byte 0
0
No additional information
1
Read-count specification error
2
Write-count specification error
8 Two I/O operations active
RCQ: No additional information
9 CBC-offset specification error
RCQ word 0: Byte offset of COB CBC-offset entry
Interrogate TSA
Word
0
Format
1
Operation State
Flags
Control-Unit Status
Device Status
Reserved
2
State-Dependent Information
4
5
Device-Level Identifier
6
Device-Dependent Information
12
0
Word.Bit
0.8
0.9
0.10
0.16-23
0.24-31
1.0-7
8
16
24
31
Meaning
Control-unit state valid
Device-state valid
Operation-state valid
(CS) Control-unit state
0 Busy
1 Recovery
2 Interrogate maximum
(DS) Device-unit state
0 Path-Group identification (in state-dependent-information field)
1 Long busy
2 Recovery
(OS) Operation state
0 No I/O operation present.
1 An I/O operation is present and executing.
2 An I/O operation is present and awaiting completion of another operation initiated by another configuration.
3 An I/O operation is present and awaiting completion of another operation initiated for the same device extent.
4 An I/O operation is present and waiting to perform a device-dependent operation.
79
SA22-7871-08.book Page 80 Thursday, February 19, 2015 3:46 PM
Subchannel-Information Block (SCHIB)
Word
0
1
2
3
Path-Management-Control Word
4
5
6
7
Subchannel-Status Word
(See “Command-Mode Subchannel-Status Word (SCSW)” on page 81.)
8
9
10
Model-Dependent Area /
Measurement-Block Address
11
12
Model-Dependent Area
0
31
Path-Management-Control Word (PMCW)
Word
0
Interruption Parameter
1 0 0 ISC 0 0 0 E LM MM D T V
2
LPM
3
Device Number
PNOM
LPUM
MBI
PIM
POM
PAM
4
CHPID-0
CHPID-1
CHPID-2
CHPID-3
5
CHPID-4
CHPID-5
CHPID-6
CHPID-7
6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FXS
0
Word.Bit
1.2-4
1.8
1.9-10
1.11-12
80
8
16
Meaning
(ISC) Interruption-subclass code
(E) Subchannel enabled
(LM) limit mode
00 No Checking
01 Data address must be  limit
10 Data address must be < limit
11 Reserved
(MM) Measurement-mode enable
00 Neither mode enabled
01 Device-connect-time-measurement enabled
10 Measurement-block-update enabled
11 Both modes enabled
z/Architecture Reference Summary
24
31
SA22-7871-08.book Page 81 Thursday, February 19, 2015 3:46 PM
1.13
1.14
1.15
2.0-7
2.8-15
2.16-23
2.24-31
3.0-15
3.16-23
3.24-31
4.0-7
6.29
6.30
6.31
(D) Multipath mode
(T) Timing facility available
(V) Device number valid
(LPM) Logical-path mask
(PNOM) Path-not-operational mask
(LPUM) Last-path-used mask
(PIM) Path-installed mask
(MBI) Measurement-block index
(POM) Path-operational mask
(PAM) Path-available mask
(CHPID-0) Channel-path ID for logical path 0 (typical)
(F) Measurement-block-format control
(X) Extended-measurement-word-mode enable
(S) Concurrent sense
Interruption-Response Block (IRB)
Word
0
1
Subchannel-Status Word
2
3
4
5
Extended-Status Word
6
7
8

15
Extended-Control Word
16

23
Extended-Measurement Word
0
31
Command-Mode Subchannel-Status Word (SCSW)
Word
Subchannel Control
0
Key
0
S L CC F P I X U Z E N 0
4 5 6
8
1
FC
17
AC
20
SC
27
31
CCW Address
2
Device Status
0
Word.Bit
0.0-3
0.4
0.5
0.6-7
0.8
0.9
13
Subchannel Status
8
Byte Count
16
31
Meaning
(Key) Subchannel key
(S) Suspend control
(L) Extended-status-word format (logout stored)
(CC) Deferred condition code
00 Normal I/O interruption
01 Status in SCSW
10 Reserved
11 Path not operational
(F) CCW-format control
(P) Prefetch control
81
SA22-7871-08.book Page 82 Thursday, February 19, 2015 3:46 PM
0.10
0.11
0.12
0.13
0.14
0.15
0.17-19
(I) Initial-status-interruption control
(X) IRB-format control
(U) Suppress-suspended-interruption control
(Z) Zero condition code
(E) Extended control (information stored in ECW of IRB)
(N) Path not operational (PNOM nonzero)
(FC) Function control
17 (40) Start, 18 (20) Halt, 19 (10) Clear
(AC) Activity control
20 (08) Resume pending
24 (80) Subchannel active
21 (04) Start pending
25 (40) Device active
22 (02) Halt pending
26 (20) Suspended
23 (01) Clear pending
(SC) Status control
27 (10) Alert
30 (02) Secondary
28 (08) Intermediate
31 (01) Status pending
29 (04) Primary
Device status (0-7)
Subchannel status (8-15)
0 (80) Attention
8 (80) Program-controlled interruption
1 (40) Status modifier
9 (40) Incorrect length
2 (20) Control-unit end
10 (20) Program check
3 (10) Busy
11 (10) Protection check
4 (08) Channel end
12 (08) Channel-data check
5 (04) Device end
13 (04) Channel-control check
6 (02) Unit check
14 (02) Interface-control check
7 (01) Unit exception
15 (01) Chaining check
0.20-26
0.27-31
2.0-15
Transport-Mode Subchannel-Status Word (SCSW)
Word
Subchannel Control
0
Key
0
0 L CC FMT X Q 0 E N 0
4 5 6
8
1
13
FC
17
AC
20
SC
27
31
TCW Address
2
Device Status
0
Word.Bit
0.0-3
0.5
0.6-7
0.8-10
0.11
0.12
0.14
0.15
0.17-19
0.20-26
0.27-31
82
11
Subchannel Status
8
FCX Status
16
SCHXS
24
Meaning
(Key) Subchannel key
(L) Extended-status-word format (logout stored)
(CC) Deferred condition code
00 Normal I/O interruption
01 Status in SCSW
10 Reserved
11 Path not operational
(FMT) Format
(X) IRB-format control
(Q) Interrogate complete
(E) Extended control (information stored in ECW of IRB)
(N) Path not operational (PNOM nonzero)
(FC) Function control
17 (40) Start, 18 (20) Halt, 19 (10) Clear
(AC) Activity control
21 (04) Start pending
23 (01) Clear pending
22 (02) Halt pending
25 (40) Device active
(SC) Status control
27 (10) Alert
30 (02) Secondary
28 (08) Intermediate
31 (01) Status pending
29 (04) Primary
z/Architecture Reference Summary
31
SA22-7871-08.book Page 83 Thursday, February 19, 2015 3:46 PM
2.0-15
2.16-23
2.24-31
Device status (0-7)
Subchannel status (8-15)
0 (80) Attention
8 (80) —
1 (40) —
9 (40) Incorrect length
2 (20) Control-unit end
10 (20) Program check
3 (10) Busy
11 (10) Protection check
4 (08) Channel end
12 (08) Channel-data check
5 (04) Device end
13 (04) Channel-control check
6 (02) Unit check
14 (02) Interface-control check
7 (01) Unit exception
15 (01) Channel-subsystem retry failed
FCX status (16-23)
23 (01) TSB valid
(SCHXS) Subchannel-extended status
24 (80) (F) Interrogate failed
25-31 (SESQ) SCHSX qualifier
0
No status available.
1
Storage-request limit exceeded.
2
Program check when not an interrogate operation, TCW read/write
data count not zero, and CE only or CE+DE only status received.
3
Transport mode not supported by the I/O device.
4
Transport mode not supported by the selected channel path.
6
Program check on TCW.
7
Device-detected program check condition due to indeterminate
cause.
8
Device-detected program check.
9
Program check on TIDAW - failing-storage-address (FSA) valid in
ESW (see below) and contains TIDAW address.
32 TCW access exception - FSA field valid and contains TCW
address.
33 TSB access exception - FSA field valid and contains TSB address.
34 TCCB access exception - FSA field valid and contains TCCB
address.
35 TIDAW access exception - FSA field valid and contains TIDAW
address.
36 Data access exception - FSA field valid and contains address of
data.
64 Invalid CBC error on read data.
66 Link protocol error condition.
67 Device-level recovery operation failed.
68 IFCC due to failed device-level recovery operation - program, protection, or data check may also be set in subchannel status.
70 Invalid CBC on status portion of transport response from device.
71 Invalid CBC on TSB transported from device.
Note: If FSA field valid for cases other than noted above, FSA field contains address of current TCW.
Extended-Status Word (ESW)
See chart on page 85 to determine the appropriate ESW format.
Format-0 ESW
Word
0
Subchannel Logout
1
Extended-Report Word
2
Failing-Storage Address
3
4
Secondary-CCW Address
0
31
83
SA22-7871-08.book Page 84 Thursday, February 19, 2015 3:46 PM
Format-0 ESW Word 0 (Subchannel Logout)
0
ESF
0 1
LPUM
8
Bit
1-7
R
FVF
16
SA
22
TC D E A
24
26
28
SC
31
Meaning
(ESF) Extended-status flags (1 key check, 2 measurement-block program check, 3
measurement-block data check, 4 measurement-block protection check, 5 CCW check,
6 IDAW check, 7:0)
(LPUM) Last-path-used mask
(R) Ancillary Report
(FVF) Field-validity flags (17 LPUM, 18 TC, 19 SC, 20 device status, 21 CCW address)
(SA) Storage-access code (00 access type unknown, 01 read, 10 write, 11 read backward)
(TC) Termination code (00 halt signal issued, 01 stop, stack, or normal termination, 10
clear signal issued)
(D) Device status check
(E) Secondary error
(A) I/O-error alert
(SC) Sequence code
8-15
16
17-21
22-23
24-25
26
27
28
29-31
Format-0 ESW Word 1 (Extended-Report Word)
0 L E A P T F S C R
0
Bit
1
2
3
4
5
6
7
8
9
10-15
3
8
SCNT
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
31
Meaning
(L) Request logging only
(E) Extended-subchannel-logout pending
(A) Authorization check
(P) Path-verification-required
(T) Channel-path timeout
(F) Failing-storage-address validity
(S) Concurrent sense
(C) Secondary-CCW-address validity
(R) Failing-storage-address format (zero: 1-31 of word 2; one: words 2 and 3)
(SCNT) Concurrent-sense count
Format-1 ESW Word 01
0 0 0 0 0 0 0 0
LPUM
0
8
Bit
8-15
Meaning
(LPUM) Last-path-used mask
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
31
Format-2 ESW Word 01
0 0 0 0 0 0 0 0
0
Bit
8-15
16-31
LPUM
8
DCTI
16
31
Meaning
(LPUM) Last-path-used mask
(DCTI) Device-connect-time interval
Format-3 ESW Word 01
0 0 0 0 0 0 0 0
LPUM
0
8
Bit
8-15
Meaning
(LPUM) Last-path-used mask
Unpredictable
16
1.
Word 1 is the same as word 1 of a format-0 ESW. Words 2, 3, and 4 are
zeros.
84
z/Architecture Reference Summary
31
SA22-7871-08.book Page 85 Thursday, February 19, 2015 3:46 PM
Information Stored in ESW
Subchannel Conditions under which ESW Is Stored by Test Subchannel Instruction
Path-Management-ConExtended-Status Word
Subchannel-Status Word
trol Word
(ESW)
DeviceConnectTime MeaStatus-Control
SussurementField
pended TimingMode
A I P S X L Bit
Bit Facility Bit Enable Bit
- - - - 0
*
*
*
DeviceConnectContents
Time MeaWord 0 Byte
surementMode Active Format 0 1 2 3
No / Yes
U
* * * *
* * 0 0 1
* * 1 * 1
1 0 0 1 1
1
1
1
*
*
*
*
*
*
*
*
*
No / Yes
No / Yes
No / Yes
0
0
0
R R R R
R R R R
R R R R
0 0 0 0 1
0 0 0 1 1
1 0 0 * 1
0
0
0
*
*
*
*
*
*
*
*
*
No / Yes
No / Yes
No / Yes
U
3
3
* * * *
Z M * *
Z M * *
*
*
*
*
*
*
*
*
1
1
1
1
*
*
*
*
1
1
1
1
0
0
0
0
*
*
*
*
0
1
1
1
*
0
1
1
No / Yes
No / Yes
No
Yes
1
1
1
2
Z
Z
Z
Z
M
M
M
M
Z
Z
Z
D
Z
Z
Z
D
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
*
0
1
1
1
*
*
0
1
1
No / Yes
No / Yes
No / Yes
No
Yes
U
1
1
1
2
*
Z
Z
Z
Z
*
M
M
M
M
*
Z
Z
Z
D
*
Z
Z
Z
D
0 0 0 1 1
1
1 1 0 0 1
0
These combinations do not occur.
* 1 0 1 1
*
Bit
Meaning
Not meaningful.
*
Bits may be zeros or ones.
A
Alert status.
D
Accumulated device-connect-time-interval (DCTI) value stored in bytes 2 and 3.
I
Intermediate status.
L
Extended-status-word format.
M
Last-path-used mask (LPUM) stored in byte 1.
P
Primary status.
R
Subchannel-logout information stored in bytes 0-3.
S
Secondary status.
U
No format defined.
X
Status pending.
Z
Bits are stored as zeros.
Extended-Control Word (ECW)
SCSW Bits
5
14
0
0
0
1
1
1
1
a.
0
1
1
ERW
Bit 7
ERW Bits 10-15
0
Zeros
1
Number of concurrentsense bytesa
0
Zeros
0
Zeros
1
Number of concurrentsense bytes
ECW Words 0-7
Unpredictable
Concurrent-sense informationa
Unpredictable
Model-dependent information
Concurrent-sense information
The contents of the ECW are specified by bits 5 and 14 of word 0 of the SCSW. The combination
of SCSW bit 5 zero, SCSW bit 14 one, and ERW bit 7 zero does not occur.
85
SA22-7871-08.book Page 86 Thursday, February 19, 2015 3:46 PM
Extended-Measurement Word
Word
0
Device-Connect Time
1
Function-Pending Time
2
Device-Disconnect Time
3
Control-Unit-Queuing Time
4
Device-Active-Only Time
5
Device-Busy Time
6
Initial-Command-Response Time
Reserved
7
0
31
Format 0 Measurement Block
Word
0
SSCH + RSCH Count
1
Sample Count
Device-Connect Time
2
Function-Pending Time
3
Device-Disconnect Time
4
Control-Unit-Queuing Time
5
Device-Active-Only Time
6
Device-Busy Time
7
Initial-Command-Response Time
0
86
16
z/Architecture Reference Summary
31
SA22-7871-08.book Page 87 Thursday, February 19, 2015 3:46 PM
Format 1 Measurement Block
Word
0
SSCH + RSCH Count
1
Sample Count
2
Device-Connect Time
3
Function-Pending Time
4
Device-Disconnect Time
5
Control-Unit-Queuing Time
6
Device-Active-Only Time
7
Device-Busy Time
8
Initial-Command-Response Time
9
Interrupt Delay Time
10
I/O Priority Delay Time
11

Reserved
15
0
31
Channel-Report Word (CRW)
0 S R C
0
Bit
1
2
3
4-7
8
10-15
16-31
RSC
4
A 0
8
ERC
10
Reporting-Source ID
16
31
Meaning
(S) Solicited CRW
(R) Overflow (one or more CRWs lost)
(C) Chaining (meaningless if bit 2 is one)
(RSC) Reporting-source code (see Reporting-Source table)
(A) Ancillary report
(ERC) Error-recovery code (see Error-Recovery-Code table)
Reporting-source ID (see Reporting-Source table)
Error-Recovery Codes
ERC
Condition
0 0 0 0 0 1
Available
0 0 0 0 1 0
Initialized
0 0 0 0 1 1
Temporary error
0 0 0 1 0 0
Installed parameters initialized
0 0 0 1 0 1
Terminal
0 0 0 1 1 0
Permanent error with facility not initialized
0 0 0 1 1 1
Permanent error with facility initialized
0 0 1 0 0 0
Installed parameters modified
87
SA22-7871-08.book Page 88 Thursday, February 19, 2015 3:46 PM
Reporting Source
The reporting-source-ID format depends on the RSC field of the channel-report word,
as follows:
RSC
0 0 1
0 0 1
0 0 1
0 1 0
1 0 0
1 0 1
0
1
1
0
1
1
Reporting Source
Monitoring facility
Subchannel (first or only CRW)
Subchannel (chained CRW)
Channel path
Configuration-alert facility
Channel subsystem
Reporting-Source ID
0 0 0 0 0 0 0 0 0
XXXXXXXX X
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 Y
0 0 0 0 0 0 0 0 Y
0 0 0 0 0 0 0 0 0
0
X
0
Y
Y
0
0
X
S
Y
Y
0
0
X
S
Y
Y
0
0
X
0
Y
Y
0
0
X
0
Y
Y
0
0
X
0
Y
Y
0
0
X
0
Y
Y
0
S = Subchannel-set identifier (SSID) when the MSS facility is installed and the CRW is
chained immediately following a CRW for a subchannel.
X = Subchannel number
Y = Channel-path ID (CHPID)
I/O Command Codes
Standard Command-Code Assignments (CCW and DCW Bits 0-7)
xxxx
mmmm
mmmm
0000
mmmm
0000
0 1 mm
0000
mm0 1
mm1 0
0010
mm1 1
0011
0000
Invalid Command
Write (a)
Read (a)
— Read IPL
Control
— Control no operation
Transport (b)
x – Bit Ignored
m – Modifier bit for specific type of I/O
device
mmmm
0000
1110
xxxx
0000
mmmm
mmmm
a
b
c
d
e
f
0100
0100
0100
1000
1000
1000
1100
Sense
— Basic Sense
— Sense ID
Transfer in channel (c)
Transfer in channel (d)
Invalid command (e)
Read backwards (f)
May designate control data in a DCW
DCW only
Format-0 CCW
Format-1 CCW
Format-1 CCW and nonzero m bit
CCW only
Standard Meanings of Bits of First Sense Byte
Bit
88
Bit
Designation
0
Designation
Command reject
4
Data check
1
Intervention required
5
Overrun
2
Bus-out check
6
(Device dependent)
3
Equipment check
7
(Device dependent)
z/Architecture Reference Summary
SA22-7871-08.book Page 89 Thursday, February 19, 2015 3:46 PM
Character Assignments
Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Hex
EBCDIC1
ISO-82
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
24
35
36
37
38
39
3A
3B
3C
3D
3E
3F
NUL
SOH
STX
ETX
SEL
HT
RNL
DEL
GE
SPS
RPT
VT
FF
CR
SO
SI
DLE
DC1
DC2
DC3
RES/ENP
NL
BS
POC
CAN
EM
UBS
CU1
IFS
IGS
IRS
ITB/IUS
DS
SOS
FS
WUS
BYP/INP
LF
ETB
ESC
SA
SFE
SM/SW
CSP
MFA
ENQ
ACK
BEL
NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
IFS
IGS
IRS
IUS
SP
!
"
#
$
%
&
'
(
)
*
+
,
.
/
0
1
2
3
4
5
6
7
8
9
:
;
<
=
>
?
SYN
IR
PP
TRN
NBS
EOT
SBS
IT
RFF
CU3
DC4
NAK
SUB
Dec
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Hex
EBCDIC1
ISO-82
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
SP
RSP
â
ä
à
á
ã
å
ç
ñ
¢
.
<
(
+
|
&
é
ê
ë
è
í
î
ï
ì
ß
!
$
*
)
;
¬
/
Â
Ä
À
Á
Ã
Å
Ç
Ñ
¦
,
%
_
>
?
ø
É
Ê
Ë
È
Í
Î
Ï
Ì
`
:
#
@
'
=
"
@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
[
\
]
^
_
`
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
{
|
}
~
•
89
SA22-7871-08.book Page 90 Thursday, February 19, 2015 3:46 PM
Dec
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
90
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EBCDIC1
Ø
a
b
c
d
e
f
g
h
i
«
»
ð
ý
þ
±
°
j
k
l
m
n
o
p
q
r
ª
º
æ
¸
Æ
¤
µ
~
s
t
u
v
w
x
y
z
¡
¿
Ð
Ý
þ
®
^
£
¥
·
©
§
¶
¼
½
¾
[
]
ä
¨
´
×
ISO-82
BPH
NBH
IND
NEL
SSA
ESA
HTS
HTJ
VTS
PLD
PLU
RI
SS2
SS3
DCS
PU1
PU2
STS
CCH
MW
SPA
EPA
SOS
SCI
CSI
ST
OSC
PM
APC
RSP
¡
¢
£
¤
¥
¦
§
¨
©
ª
«
¬
SHY
®
¯
°
±
²
³
´
µ
¶
·
¸
¹
º
»
¼
½
¾
¿
Dec
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
EBCDIC1
{
A
B
C
D
E
F
G
H
I
SHY
ô
ö
ò
ó
õ
}
J
K
L
M
N
O
P
Q
R
¹
û
ü
ù
ú
ÿ
\
÷
S
T
U
V
W
X
Y
Z
²
Ô
Ö
Ò
Ó
Õ
0
1
2
3
4
5
6
7
8
9
³
Û
Ü
Ù
Ú
EO
z/Architecture Reference Summary
ISO-82
À
Á
Â
Ã
Ä
Å
Æ
Ç
È
É
Ê
Ë
Ì
Í
Î
Ï
Ð
Ñ
Ò
Ó
Ô
Õ
Ö
×
Ø
Ù
Ú
Û
Ü
Ý
Þ
ß
à
á
â
ã
ä
å
æ
ç
è
é
ê
ë
ì
í
î
ï
ð
ñ
ò
ó
ô
õ
ö
÷
ø
ù
ú
û
ü
ý
þ
ÿ
SA22-7871-08.book Page 91 Thursday, February 19, 2015 3:46 PM
Notes:
1
2
The EBCDIC characters are based on code page 037.
The ISO-8 controls are from ISO 6429, and the graphics are from ISO 8859-1. The ISO-8
graphics are code page 00819, named ISO/ANSI Multilingual.
Control Character Representations
ACK
BEL
BS
BYP
CAN
CR
CSP
CU1
CU3
DC1
DC2
DC3
DC4
DEL
DLE
DS
EM
ENP
ENQ
EO
EOT
ESC
ETB
ETX
FF
FS
GE
HT
IFS
IGS
INP
IR
IRS
Acknowledge
Bell
Backspace
Bypass
Cancel
Carriage Return
Control Sequence Prefix
Customer Use 1
Customer Use 3
Device Control 1
Device Control 2
Device Control 3
Device Control 4
Delete
Data Link Escape
Digit Select
End of Medium
Enable Presentation
Enquiry
Eight Ones
End of Transmission
Escape
End of Transmission Block
End of Text
Form Feed
Field Separator
Graphic Escape
Horizontal Tab
Interchange File Separator
Interchange Group Separator
Inhibit Presentation
Index Return
Interchange Record Separator
IT
ITB
IUS
LF
MFA
NAK
NBS
NL
NUL
POC
PP
RES
RFF
RNL
RPT
SA
SBS
SEL
SFE
SI
SM
SO
SOH
SOS
SPS
STX
SUB
SW
SYN
TRN
UBS
VT
WUS
Indent Tab
Intermediate Transmission Block
International Unit Separator
Line Feed
Modify Field Attribute
Negative Acknowledge
Numeric Backspace
New Line
Null
Program-Operator Communication
Presentation Position
Restore
Required Form Feed
Required New Line
Repeat
Set Attribute
Subscript
Select
Start Field Extended
Shift In
Set Mode
Shift Out
Start of Heading
Start of Significance
Superscript
Start of Text
Substitute
Switch
Synchronous Idle
Transparent
Unit Backspace
Vertical Tab
Word Underscore
Additional ISO-8 Control Character Representations
APC
BPH
CCH
CSI
DCS
ESA
HTJ
HTS
IFS
IGS
IND
IRS
MW
NBH
NEL
OSC
Application Program Command
Break Permitted Here
Cancel Character
Control Sequence Introducer
Device Control String
End of Selected Area
Character Tabulation w/ Justification
Character Tabulation Set
Information Separator Four
Information Separator Three
Index
Information Separator Two
Message Waiting
No Break Here
Next Line
Operating System Command
PLD
PLU
PM
PU1
PU2
SCI
SOS
SPA
SSA
SS2
SS3
ST
STS
US
VTS
Partial Line Down
Partial Line Up
Privacy Message
Private Use One
Private Use Two
Single Character Introducer
Start of String
Start of Guarded Area
Start of Selected Area
Single Shift Two
Single Shift Three
String Terminator
Set Transmit State
Information Separator One
Line Tabulation Set
Formatting Character Representations
NSP
RSP
Numeric Space
Required Space
SP
SHY
Space
Syllable Hyphen
Two-Character BSC Data Link Controls
Function
ACK-0
ACK-1
WACK
RVI
EBCDIC
DLE,X'70'
DLE,X'61'
DLE,X'68'
DLE,X'7C'
ASCII
DLE,0
DLE,1
DLE,;
DLE,<
Commonly Used Editing Pattern Characters
Code
(Hex)
20
21
22
40
4B
Meaning
Digit selector
Start of significance
Field separator
Blank
Period
Code
(Hex)
5B
5C
6B
C3D9
C4C2
Meaning
Dollar sign
Asterisk
Comma
CR (credit)
DB (debit)
91
SA22-7871-08.book Page 92 Thursday, February 19, 2015 3:46 PM
ANSI-Defined Printer Control Characters
(A in RECFM field of DCB)
Code
blank
0
+
1
Action before Printing Record
Space 1 line
Space 2 lines
Space 3 lines
Suppress space
Skip to line 1 on new page
Hexadecimal and Decimal Conversion
From hex: locate each hex digit in its corresponding column position and note the decimal equivalents. Add these to obtain the decimal value.
From decimal: (1) locate the largest decimal value in the table that will fit into the decimal number to be converted, and (2) note its hex equivalent and hex column position.
(3) Find the decimal remainder. Repeat the process on this and subsequent remainders.
Note: Hexadecimal equivalents of all numbers from 0 to 255 are listed in the code
tables.
92
z/Architecture Reference Summary
F
E
D
C
B
A
9
8
7
6
5
4
3
2
8
268,435,456
536,870,912
805,306,368
1,073,741,824
1,342,177,280
1,610,612,736
1,879,048,192
2,147,483,648
2,415,919,104
2,684,354,560
2,952,790,016
3,221,225,472
3,489,660,928
3,758,096,384
4,026,531,840
0
0
1
Dec
0123
Hex
Bits:
Byte
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
7
Dec
0
16,777,216
33,554,432
50,331,648
67,108,864
83,886,080
100,663,296
117,440,512
134,217,728
150,994,944
167,772,160
184,549,376
201,326,592
218,103,808
234,881,024
251,658,240
4567
Halfword
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
6
Dec
0
1,048,576
2,097,152
3,145,728
4,194,304
5,242,880
6,291,456
7,340,032
8,388,608
9,437,184
10,485,760
11,534,336
12,582,912
13,631,488
14,680,064
15,728,640
0123
Byte
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
5
4567
Word
0
65,536
131,072
196,608
262,144
327,680
393,216
458,752
524,288
589,824
655,360
720,896
786,432
851,968
917,504
983,040
Dec
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
4
0123
0
4,096
8,192
12,288
16,384
20,480
24,576
28,672
32,768
36,864
40,960
45,056
49,152
53,248
57,344
61,440
Dec
Byte
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
3
4567
0
256
512
768
1,024
1,280
1,536
1,792
2,048
2,304
2,560
2,816
3,072
3,328
3,584
3,840
Dec
Halfword
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
2
0123
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
Dec
Byte
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Hex
1
4567
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Dec
SA22-7871-08.book Page 93 Thursday, February 19, 2015 3:46 PM
93
SA22-7871-08.book Page 94 Thursday, February 19, 2015 3:46 PM
Powers of 2 and 16
m
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
94
n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
4
9
1
2
4
9
18
36
72
144
288
576
152
305
611
223
1
2
4
8
17
35
70
140
281
562
125
251
503
007
014
028
057
115
230
460
921
843
686
372
2m and 16n
1
2
4
8
16
32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
262 144
524 288
1 048 576
2 097 152
4 194 304
8 388 608
16 777 216
33 554 432
67 108 864
134 217 728
268 435 456
536 870 912
1 073 741 824
2 147 483 648
4 294 967 296
8 589 934 592
17 179 869 184
34 359 738 368
68 719 476 736
137 438 953 472
274 877 906 944
549 755 813 888
099 511 627 776
199 023 255 552
398 046 511 104
796 093 022 208
592 186 044 416
184 372 088 832
368 744 177 664
737 488 355 328
474 976 710 656
949 953 421 312
899 906 842 624
799 813 685 248
599 627 370 496
199 254 740 992
398 509 481 984
797 018 963 968
594 037 927 936
188 075 855 872
376 151 711 744
752 303 423 488
504 606 846 976
009 213 693 952
018 427 387 904
036 854 775 808
z/Architecture Reference Summary
Symbol
K (kilo)
M (mega)
G (giga)
T (tera)
P (peta)
E (exa)
SA22-7871-08.book Page 95 Thursday, February 19, 2015 3:46 PM
m
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
n
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
5
10
21
42
85
170
340
1
2
5
10
20
41
83
166
332
664
329
658
316
633
267
535
070
141
282
1
2
5
10
20
40
81
162
324
649
298
596
192
384
769
538
076
153
306
613
227
455
911
823
647
295
591
183
366
1
2
4
9
19
39
79
158
316
633
267
535
070
141
282
564
129
259
518
037
074
148
296
593
187
374
749
499
998
997
995
991
983
966
932
865
730
460
920
1
2
4
9
19
38
77
154
309
618
237
475
951
903
807
614
228
456
912
825
650
301
602
204
409
819
638
276
553
107
214
429
858
717
434
868
736
473
946
892
784
569
139
279
558
117
234
469
938
1
2
4
9
18
37
75
151
302
604
208
417
835
671
342
685
371
742
485
970
940
880
760
520
040
081
162
325
650
300
600
200
400
801
603
207
414
829
658
316
633
267
534
069
139
278
557
114
228
457
915
831
663
326
653
307
615
231
463
18
36
73
147
295
590
180
361
722
444
889
778
557
115
231
462
925
851
703
406
813
626
252
504
009
019
039
078
157
314
628
257
514
028
057
114
228
456
912
825
651
303
606
213
426
853
706
413
827
655
310
621
242
484
968
936
872
745
491
983
966
932
865
731
463
446
893
786
573
147
295
591
183
366
732
465
931
863
727
454
909
819
639
278
556
113
227
455
910
821
642
285
570
141
283
566
132
264
528
057
114
229
458
917
835
670
340
681
363
726
453
907
814
628
257
514
028
056
112
225
451
903
807
615
230
460
921
843
687
374
744
488
976
952
905
810
620
241
482
965
931
862
725
451
903
807
614
229
458
917
834
668
336
672
345
690
380
760
521
042
084
168
337
675
350
700
401
802
605
211
423
847
695
391
783
566
132
265
530
060
121
243
487
975
951
903
807
614
228
456
912
825
651
303
607
073
147
294
589
179
358
717
434
869
739
478
957
914
828
657
314
629
258
516
033
066
133
267
534
068
137
274
549
099
199
398
796
593
187
374
748
496
993
986
973
947
894
789
578
156
312
624
248
496
992
985
970
941
882
765
530
060
120
241
482
964
928
857
715
431
2m and 16n
709 551 616
419 103 232
838 206 464
676 412 928
352 825 856
705 651 712
411 303 424
822 606 848
645 213 696
290 427 392
580 854 784
161 709 568
323 419 136
646 838 272
293 676 544
587 353 088
174 706 176
349 412 352
698 824 704
397 649 408
795 298 816
590 597 632
181 195 264
362 390 528
724 781 056
449 562 112
899 124 224
798 248 448
596 496 896
192 993 792
385 987 584
771 975 168
543 950 336
087 900 672
175 801 344
351 602 688
703 205 376
406 410 752
812 821 504
625 643 008
251 286 016
502 572 032
005 144 064
010 288 128
020 576 256
041 152 512
082 305 024
164 610 048
329 220 096
658 440 192
316 880 384
633 760 768
267 521 536
535 043 072
070 086 144
140 172 288
280 344 576
560 689 152
121 378 304
242 756 608
485 513 216
971 026 432
942 052 864
884 105 728
768 211 456
Symbol
Z (zetta)
Y (yotta)
(see note)
(see note)
(see note)
(see note)
Note: No Système international d'unités (SI) symbols greater than Y (yotta) are defined.
95
SA22-7871-08.book Page 96 Thursday, February 19, 2015 3:46 PM
96
z/Architecture Reference Summary
SA22-7871-08.book Page i Thursday, February 19, 2015 3:46 PM
.
SA22-7871-08.book Page ii Thursday, February 19, 2015 3:46 PM
IBMr
File Number: S-390-00
Printed in the United States of America on recycled paper
containing 10% recovered post-consumer fiber.
SA22-7871-08
*07SA22787108*