DATASHEET

DG211
®
Data Sheet
November 19, 2007
FN3118.5
SPST 4-Channel Analog Switch
Features
The DG211 is a low cost, CMOS monolithic, Quad SPST
analog switch. It can be used in general purpose switching
applications for communications, instrumentation, process
control and computer peripheral equipment and provides
true bi-directional performance in the ON condition and
blocks signals to 30VP-P in the OFF condition.
• Switches ±15V Analog Signals
Ordering Information
PART
NUMBER
PART
TEMP.
MARKING RANGE (°C)
• TTL Compatibility
• Logic Inputs Accept Negative Voltages
• rON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω
• Pb-Free Available (RoHS Compliant)
Functional Block Diagram
PACKAGE
PKG.
DWG. #
DG211CJ
DG211CJ
0 to +70
16 Ld PDIP
E16.3
DG211CJZ
(Note)
DG211CJZ
0 to +70
16 Ld PDIP*
(Pb-free)
E16.3
DG211CY**
DG211CY
0 to +70
16 Ld SOIC
M16.15
DG211CYZ** DG211CYZ
(Note)
0 to +70
16 Ld SOIC
(Pb-free)
M16.15
DG211CVZ** DG211 CVZ
(Note)
0 to +70
16 Ld TSSOP
(Pb-free)
M16.173
DG211
S1
IN1
D1
S2
IN2
D2
S3
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
**Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
IN3
D3
S4
IN4
D4
TRUTH TABLE
LOGIC
DG211
0
ON
1
OFF
Logic “0” ≤0.8V, Logic “1” ≥ 2.4V
Pinout
DG211
(16 LD PDIP, SOIC, TSSOP)
TOP VIEW
IN1
1
16 IN2
D1
2
15 D2
S1
3
14 S2
V-
4
13 V+ (SUBSTRATE)
GND
5
12 VL (+5V)
S4
6
11 S3
D4
7
10 D3
IN4
8
9 IN3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
DG211
Schematic Diagram
DG211 (1/4 AS SHOWN)
TTL IN
-15V
GND
+15V
+5V
VL
-15V
V-
-15V
+15V
IN
2
OUT
FN3118.5
November 19, 2007
DG211
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
VIN to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+
VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
VS or VD to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to -36V
VS or VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 36V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Current, any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, V- = -15V, VL = +5V, GND, TA = +25°C
MIN
(Notes 2, 6)
TYP
(Note 3)
-
460
-
ns
tOFF1
-
360
-
ns
tOFF2
-
450
-
ns
-
70
-
dB
-
-90
-
dB
-
5
-
pF
Drain OFF-Capacitance, CD(OFF)
-
5
-
pF
Channel ON-Capacitance, CD(ON) + CS(ON)
-
16
-
pF
VIN = 2.4V
-1.0
-0.0004
-
µA
VIN = 15V
-
0.003
1.0
µA
VIN = 0V
-1.0
-0.0004
-
µA
-15
-
15
V
PARAMETER
TEST CONDITIONS
MAX
(Notes 2, 6) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
See Figure 1
VS = 10V, RL = 1kΩ, CL = 35pF
Turn-OFF Time
OFF Isolation, OIRR (Note 5)
Crosstalk (Channel-to-Channel), CCRR
Source OFF-Capacitance, CS(OFF)
VIN = 5V, RL = 1kΩ, CL = 15pF, VS = 1VRMS ,
f = 100kHz
VD = VS = 0V, VIN = 5V, f = 1MHz
DIGITAL INPUT CHARACTERISTICS
Input Current with Voltage High, IIH
Input Current with Voltage Low, IIL
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Drain-Source ON-Resistance, rDS(ON)
VD = ±10V, IS = 1mA, VIN = 0.8V
-
150
175
Ω
Source OFF Leakage Current, IS(OFF)
VIN = 2.4V
VS = 14V, VD = -14V
-
0.01
5.0
nA
VS = -14V, VD = 14V
-5.0
-0.02
-
nA
VS = -14V, VD = 14V
-
0.01
5.0
nA
VS = 14V, VD = -14V
-5.0
-0.02
-
nA
VS = VD = 14V
-
0.1
5.0
nA
VS = VD = -14V
-5.0
-0.15
-
nA
Drain OFF Leakage Current, ID(OFF)
Drain ON Leakage Current, ID(ON)
(Note 4)
3
VIN = 0.8V
FN3118.5
November 19, 2007
DG211
Electrical Specifications
V+ = +15V, V- = -15V, VL = +5V, GND, TA = +25°C (Continued)
MIN
(Notes 2, 6)
TYP
(Note 3)
-
0.1
10
µA
Negative Supply Current, I-
-
0.1
10
µA
Logic Supply Current, IL
-
0.1
10
µA
PARAMETER
TEST CONDITIONS
MAX
(Notes 2, 6) UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
VIN = 0V or 2.4V
NOTES:
2. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
3. For design reference only, not 100% tested.
4. ID(ON) is leakage from driver into ON switch.
VS
5. OFF Isolation = 20 log -------- , V S = Input to OFF switch, V D = output .
VD
6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Test Circuits and Waveforms
Switch output waveform shown for VS = constant with logic
input waveform as shown. Note the VS may be + or - as per
switching time test circuit. VO is the steady state output with
switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
5V
15V
VL
LOGIC†
INPUT (IN1)
tr < 20ns
tf < 20ns
50%
0V
V+
S1
SWITCH
OUTPUT
VO
D1
VS = 10V
tOFF1
SWITCH
V
INPUT S
SWITCH
OUTPUT (VO)
SWITCH
INPUT
90%
90%
LOGIC
INPUT
RL
1kΩ
IN1
10%
tOFF2
tON
GND
(REPEAT TEST FOR
IN2 , IN3 AND IN4)
V-15V
VO = VS
CL
35pF
RL
RL + rDS(ON)
† Logic shown for DG211.
FIGURE 1. SWITCHING TIME MEASUREMENT POINTS
4
FIGURE 2. SWITCHING TIME TEST CIRCUIT
FN3118.5
November 19, 2007
DG211
Metallization Mask Layout
DG211
PIN 1
IN1
PIN 16
IN2
PIN 2
D1
PIN 15
D2
PIN 3
S1
PIN 14
S2
PIN 4
V-
PIN 13
V+ (SUBSTRATE)
PIN 5
GND
PIN 12
VL
PIN 11
S3
PIN 6
S4
PIN 7
D4
PIN 8
IN 4
5
PIN 9
IN 3
PIN 10
D3
FN3118.5
November 19, 2007
DG211
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
B M
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
L
A
D
-C-
e
α
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
α
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
E1
e
A2
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
6.50
-
0.70
6
16
8o
0o
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
6
FN3118.5
November 19, 2007
DG211
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
E1
INDEX
AREA
1 2 3
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
MILLIMETERS
MIN
MAX
MIN
MAX
A
-
A1
0.015
NOTES
0.210
-
5.33
4
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
L
0.115
0.150
2.93
3.81
4
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
N
16
16
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
7
FN3118.5
November 19, 2007
DG211
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN3118.5
November 19, 2007
Similar pages