DATASHEET

Medium-Voltage, Single Supply, Single SPDT Analog
Switch
ISL43210A
Features
The Intersil ISL43210A device is a precision, bidirectional,
single SPDT analog switch designed to operate from a single
+2.7V to +15V supply. Targeted applications include
applications that require a +15V single supply such as
3D TV/Eyeware products and single supply +3.0V/+5V battery
powered equipment that benefit from the devices’ low power
consumption (5µW), low leakage currents (10nA max), and fast
switching speeds (tON = 28ns, tOFF = 20ns). Cell phones, for
example, often face ASIC functionality limitations. The number
of analog input or GPIO pins may be limited and digital
geometries are not well suited to analog switch performance.
This device may be used to “mux-in” additional functionality
while reducing ASIC design risk. It’s small package alleviates
board space limitations, making it an ideal solution.
• Fully specified at 12V, 5V, and 3.3V supplies for 10%
tolerances
The ISL43210A is a single committed SPDT, which is perfect for
use in 2-to-1 multiplexer applications.
12V rON
11Ω
12V tON/tOFF
25ns/17ns
5V rON
19Ω
5V tON/tOFF
28ns/20ns
3.3V rON
32Ω
3.3V tON/tOFF
40ns/20ns
Package
6 Ld SOT-23
• Guaranteed break-before-make switching
• Minimum 2000V ESD protection per method 3015.7
• TTL, CMOS compatible
• Battery-powered, handheld, and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Communications systems
- Radios, ADSL Modems
- PBX, PABX
• Test and measurement equipment
- Ultrasound
- Computerized Tomography (CT) Scanner
- Magnetic Resonance Image (MRI)
- Position Emission Tomography (PET) Scanner
- Electrocardiograph
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
• Low leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA
• Fast switching action
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17ns
Applications
Related Literature
June 24, 2011
FN7876.0
• Single supply operation . . . . . . . . . . . . . . . . . . . . . . +2.7V to +15V
• Pb-free (RoHS compliant)
ISL43210A
SPDT or
2x1 MUX
• Low charge injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pC
• Available in 6 Ld SOT-23 package
TABLE 1. FEATURES AT A GLANCE
SW 1/SW 2
• ON-resistance (rON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Ω
• rON matching between channels . . . . . . . . . . . . . . . . . . . . . . . <1Ω
• Audio and Video switching
- 3D TV
- 3D Eyeware
• Various circuits
- +3V/+5V DACs and ADCs
- Sample and hold circuits
- Digital filters
- Operational amplifier gain switching networks
- High frequency analog switching
- High speed multiplexing
- Integrator reset circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL43210A
Pin Configuration
(Note 1)
ISL43210A
(6 LD SOT-23)
TOP VIEW
IN 1
6 NO
V+ 2
5 COM
GND 3
4 NC
NOTE:
1. Switch Shown for Logic “0” Input.
Ordering Information
Truth Table
ISL43210A
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING TEMP. RANGE
(Note 5)
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
LOGIC
PIN NC
PIN NO
0
ON
OFF
ISL43210AIHZ-T
210A
-40 to +85
6 Ld SOT-23 P6.064
1
OFF
ON
ISL43210AIHZ-T7A
210A
-40 to +85
6 Ld SOT-23 P6.064
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
NOTES:
2. Please refer to TB347 for details on reel specifications.
Pin Descriptions
PIN
NAME
PIN
NUMBER
FUNCTION
V+
2
System Power Supply Input (+2.7V to +15V)
GND
3
Ground Connection
IN
1
Digital Control Input
COM
5
Analog Switch Common Pin
NO
6
Analog Switch Normally Open Pin
NC
4
Analog Switch Normally Closed Pin
2
3. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information
page for ISL43210A. For more information on MSL please see
techbrief TB363.
5. The part marking is located on the bottom of the part.
FN7876.0
June 24, 2011
ISL43210A
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 16.5V
Input Voltages
IN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
NO, NC (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 100V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
6 Ld SOT-23 Package (Notes 7, 8) . . . . . . .
175
95
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Maximum Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications - 12V Supply Test Conditions: V+ = +10.8V to +15V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
MAX
TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 10V
(see Figure 5)
rON Matching Between Channels, ΔrON
rON Flatness, RFLAT(ON)
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 10V
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V
(Note 12)
NO or NC OFF Leakage Current, INO(OFF) V+ = 15V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V
or INC(OFF)
COM OFF Leakage Current, ICOM(OFF)
COM ON Leakage Current, ICOM(ON)
V+ = 15V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V
V+ = 15V, VCOM = 1V, 12V, or VNO or VNC = 1V, 12V or
floating
Full
0
-
V+
V
25
-
11
20
Ω
Full
-
15
25
Ω
25
-
0.8
2
Ω
Full
-
1
4
Ω
25
-
1
4
Ω
Full
-
-
6
Ω
25
-3
0.01
3
nA
Full
-5
-
5
nA
25
-3
0.01
3
nA
Full
-5
-
5
nA
25
-5
-
5
nA
Full
-10
-
10
nA
25
-
25
-
ns
Full
-
35
-
ns
25
-
17
-
ns
Full
-
26
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 10V, RL = 1kΩ, CL = 35pF, VIN = 0V to
4V
(see Figure 1)
Turn-OFF Time, tOFF
VNO or VNC = 10V, RL = 1kΩ, CL = 35pF, VIN = 0V to 4V
(see Figure 1)
Break-Before-Make Time Delay, tD
RL = 300Ω, CL = 35pF, VNO or VNC = 10V,
VIN = 0V to 4V (see Figure 3)
Full
-
2
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
-
5
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 4)
25
-
76
-
dB
3
FN7876.0
June 24, 2011
ISL43210A
Electrical Specifications - 12V Supply Test Conditions: V+ = +10.8V to +15V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
MAX
TYP (Notes 10, 11) UNITS
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 6)
25
-
105
-
dB
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
63
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
8
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
28
-
pF
V+ = 15V, VIN = 0V or V+, all channels on or off
Full
-1.8
-
1.8
µA
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
4
-
-
V
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 15V, VIN = 0V or V+
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
MAX
TYP
(Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V
(See Figure 5)
rON Matching Between Channels, ΔrON
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V
Full
0
-
V+
V
25
-
19
30
Ω
Full
-
23
40
Ω
25
-
0.8
2
Ω
Full
-
1
4
Ω
rON Flatness, RFLAT(ON)
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V
(Note 12)
Full
-
7
8
Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V
25
-3
0.01
3
nA
Full
-5
-
5
nA
COM OFF Leakage Current, ICOM(OFF)
V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V
25
-3
-
3
nA
Full
-5
-
5
nA
25
-5
-
5
nA
Full
-10
-
10
nA
25
-
28
-
ns
Full
-
40
-
ns
25
-
20
-
ns
Full
-
30
-
ns
COM ON Leakage Current, ICOM(ON)
V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V,
4.5V or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 3V, RL = 1kΩ, CL = 35pF,
VIN = 0V to 3V (See Figure 1)
VNO or VNC = 3V, RL = 1kΩ, CL = 35pF,
VIN = 0V to 3V (See Figure 1)
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
RL = 300Ω, CL = 35pF, VNO = VNC = 3V,
VIN = 0V to 3V (See Figure 3)
Full
-
10
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
25
-
3
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 1MHz (See Figure 4)
25
-
76
-
dB
4
FN7876.0
June 24, 2011
ISL43210A
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
MAX
TYP
(Notes 10, 11) UNITS
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
60
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
8
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
28
-
pF
Full
2.7
-
15
V
Full
-1
0.0001
1
µA
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, VIN = 0V or V+, all channels on or off
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 5.5V, VIN = 0V or V+
Electrical Specifications - 2.7V to 5.5V Supply
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 9),Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
(see Figure 5)
rON Matching Between Channels, ΔrON
rON Flatness, RFLAT(ON)
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 1.5V
(Note 12)
Full
0
-
V+
V
25
-
32
50
Ω
Full
-
40
60
Ω
25
-
0.8
2
Ω
Full
-
1
4
Ω
25
-
6
10
Ω
Full
-
7
12
Ω
25
-3
0.01
3
nA
NO or NC OFF Leakage Current, INO(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V
or INC(OFF)
Full
-5
-
5
nA
COM OFF Leakage Current, ICOM(OFF)
25
-3
0.01
3
nA
Full
-5
-
5
nA
COM ON Leakage Current, ICOM(ON)
V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V
V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V or
floating
25
-5
-
5
nA
Full
-10
-
10
nA
25
-
40
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 1.5V, RL = 1kΩ, CL = 35pF,
VIN = 0V to 3V (see Figure 1)
Turn-OFF Time, tOFF
VNO or VNC = 1.5V, RL = 1kΩ, CL = 35pF,
VIN = 0V to 3V (see Figure 1)
Break-Before-Make Time Delay, tD
RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V,
VIN = 0V to 3V (see Figure 3)
Full
-
60
-
ns
25
-
20
-
ns
Full
-
30
-
ns
Full
-
20
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
-
1
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 4)
25
-
76
-
dB
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
56
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
8
-
pF
5
FN7876.0
June 24, 2011
ISL43210A
Electrical Specifications - 2.7V to 5.5V Supply
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 9),Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
TEST CONDITIONS
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
28
-
pF
V+ = 3.6V, VIN = 0V or V+, all channels on or off
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
Full
-1
-
1
µA
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
NOTES:
9. VIN = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
12. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
3V OR 4V
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
VOUT
NO OR NC
COM
IN
90%
SWITCH
OUTPUT
C
90%
0V
LOGIC
INPUT
CL
35pF
RL
1kΩ
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
--------------------V OUT = V
(NO or NC) R + r
L
ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
C
ΔVOUT
RG
NO OR NC
VOUT
COM
V+
LOGIC
INPUT
ON
ON
OFF
0V
VG
Q = ΔVOUT x CL
GND
IN
CL
LOGIC
INPUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
6
FN7876.0
June 24, 2011
ISL43210A
Test Circuits and Waveforms (Continued)
V+
3V OR 4V
LOGIC
INPUT
0V
C
NO
VNX
VOUT
COM
NC
90%
SWITCH
OUTPUT
VOUT
RL
300Ω
IN
0V
tD
CL
35pF
GND
LOGIC
INPUT
CL includes fixture and stray capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
V+
C
C
rON = V1/1mA
SIGNAL
GENERATOR
NO OR NC
NO OR NC
VNX
INX
0V OR VINH
1mA
0.8V OR VINH
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 5. rON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO1 OR NC1
COM1
50Ω
NO OR NC
IN1
COM2
ANALYZER
INX
IN2 0V OR VINH
0V OR 2.4V
NO2 OR NC2
GND
0V OR VINH
IMPEDANCE
ANALYZER
COM
NC
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
7
FIGURE 7. CAPACITANCE TEST CIRCUIT
FN7876.0
June 24, 2011
ISL43210A
Detailed Description
The ISL43210A bidirectional, single SPDT analog switch offers
precise switching capability from a single 2.7V to 15V supply
with low ON-resistance (11Ω) and high speed operation.
The device is especially well suited for 3D TV and 3D eyeware
equipment thanks to the high single supply operating voltage
(15V), low power consumption (27µW max), fast switching
speed (tON = 25ns, tOFF = 17ns), and the tiny SOT-23
packaging. High frequency applications also benefit from the
wide bandwidth and the very high off isolation rejection.
Supply Sequencing and Overvoltage
Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
that might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and GND (see
Figure 8). To prevent forward biasing these diodes, V+ must be
applied before any input signals, and input signal voltages
must remain between V+ and GND. If these conditions cannot
be guaranteed, then one of the following two protection
methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ resistor in
series with the input (see Figure 8). The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
limit the analog signal from 1V below V+ to 1V above GND. The
low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
The minimum recommended supply voltage is 2.7V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specification” tables beginning on page 3 and
“Typical Performance Curves” beginning on page 9 for details.
V+ and GND also power the internal logic and level shifter. The
level shifter converts the input logic levels to switch V+ and
GND signals to drive the analog switch gate terminals.
This device cannot be operated with bipolar supplies because
the input switching point becomes negative in this
configuration.
Logic-Level Thresholds
This switch is TTL compatible (0.8V and 2.4V) over a supply
range of 3V to 11V (see Figure 15). At 12V the VIH level is
about 2.5V. This is still below the TTL guaranteed high output
minimum level of 2.8V, but noise margin is reduced. For best
results with a 12V supply, use a logic family the provides a VOH
greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
300MHz (see Figure 16). Figure 16 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off isolation is the
resistance to this feed-through. Figure 17 details the high off
isolation rejection provided by this part. At 10MHz, off isolation
is about 50dB in 50Ω systems, decreasing approximately
20dB per decade as frequency increases. Higher load
impedances decrease off isolation rejection due to the voltage
divider action of the switch OFF impedance and the load
impedance.
Leakage Considerations
VNO OR NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43210A construction is typical of most CMOS analog
switches, except that it has only two supply pins: V+ and GND.
V+ and GND drive the internal CMOS switches and set their
analog voltage limits. Unlike switches with a 13V absolute
maximum voltage, the ISL43210A 16.5V absolute maximum
supply voltage provides plenty of room for the 10% tolerance
of 15V supplies, as well as room for overshoot and noise
spikes.
8
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these diodes
conducts if any analog signal exceeds V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given signal
pin are identical and therefore fairly well balanced, they are
reverse biased differently. Each is biased by either V+ or GND and
the analog signal. This means their leakages will vary as the
signal varies. The difference in the two diode leakages to the V+
and GND pins constitutes the analog-signal-path leakage current.
All analog leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the same or
opposite polarity. There is no connection between the analog
signal paths and V+ or GND.
FN7876.0
June 24, 2011
ISL43210A
Typical Performance Curves TA = +25°C, Unless Otherwise Specified.
45
40
35
40
35
V+ = 3.3V
30
+85°C
20
25
rON (Ω)
rON (Ω)
+85°C
+25°C
25
30
20
+25°C
15
-40°C
10
-40°C
15
30
25
20
15
10
20
+85°C
15
V+ = 5V
+85°C
+25°C
-40°C
V+ = 12V
+25°C
10
5
3
4
5
6
7
8
9
10
11
12
5 -40°C
0
13
4
2
6
VCOM (V)
V+ (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE
0.50
0.40
0.30
8
10
12
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
60
V+ = 3.3V
+25°C
50
+85°C
0.10
0
0.25
0.20
0.15
40
-40°C
+25°C
0.10
+85°C
+85°C
0.05
0
0.15
20
V+ = 5V
V+ = 12V
10
V+ = 3.3V
-40°C
0
V+ = 12V
+25°C
0.10
-40°C
0.05
0
30
V+ = 5V
Q (pC)
ΔrON (Ω)
0.20
-10
+85°C
+25°C
-40°C
0
4
2
6
8
10
-20
12
2
0
4
6
VCOM (V)
VCOM (V)
FIGURE 11. rON MATCH vs SWITCH VOLTAGE
8
10
12
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
100
35
90
80
30
+85°C
tOFF (ns)
tON (ns)
70
60
+85°C
50
25
-40°C
-40°C
40
20
-40°C
+25°C
30
20
+25°C
2
3
4
5
6
7
8
9
10
V+ (V)
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE
9
11
12
15
2
3
4
5
6
7
V+ (V)
8
9
10
11
12
FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
FN7876.0
June 24, 2011
ISL43210A
Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)
2.5
-40°C
+85°C
C
2.0
+85°C
5°
1.5
+2
VINH AND VINL (V)
VINH
V+ = 3.3V TO 12V
0
GAIN
-3
-6
20
40
-40°C
60
+25°C
1.0
RL = 50Ω
VIN = 0.2VP-P TO 2.5VP-P (V+ = 3.3V)
VIN = 0.2VP-P TO 4VP-P (V+ = 5V)
VIN = 0.2VP-P TO 5VP-P (V+ = 12V)
VINL
+85°C
0.5
2
3
4
6
5
7
8
V+ (V)
9
10
11
12
1
13
10
100
FREQUENCY (MHz)
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
10
100
600
RL = 50Ω
V+ = 3V TO 13V
20
0
30
10
40
20
50
30
V+ = 3.3V, SWITCH OFF
60
ISOLATION
70
90
70
100
80
100k
1M
10M
FREQUENCY (Hz)
FIGURE 17. OFF ISOLATION
100M 500M
V+ = 12V, SWITCH ON
50
60
10k
V+ = 12V, SWITCH OFF
40
80
110
1k
80
FIGURE 16. FREQUENCY RESPONSE
±PSRR (dB)
OFF ISOLATION (dB)
0
PHASE
PHASE (°)
NORMALIZED GAIN (dB)
3.0
0.3
V+ = 3.3V, SWITCH ON
1
10
100
FREQUENCY (MHz)
1000
FIGURE 18. ±PSRR vs FREQUENCY
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL43210A: 58
PROCESS:
Si Gate CMOS
10
FN7876.0
June 24, 2011
ISL43210A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
June 24, 2011
FN7876.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL43210A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN7876.0
June 24, 2011
ISL43210A
Package Outline Drawing
P6.064
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 4, 2/10
0-8°
1.90
0.95
0.08-0.22
D
A
6
5
4
2.80
PIN 1
INDEX AREA
1.60 +0.15/-0.10
3
3
(0.60)
1
2
3
0.20 C
2x
0.40 ±0.10
B
SEE DETAIL X
3
0.20 M C A-B D
END VIEW
TOP VIEW
10° TYP
(2 PLCS)
2.90 ±0.10
3
1.15 +0.15/-0.25
C
0.10 C
SEATING PLANE
0.00-0.15
SIDE VIEW
(0.25)
GAUGE
PLANE
1.45 MAX
DETAIL "X"
0.45±0.1
4
(0.95)
(0.60)
(1.20)
(2.40)
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
Package conforms to JEDEC MO-178AB.
TYPICAL RECOMMENDED LAND PATTERN
12
FN7876.0
June 24, 2011
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