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Data Sheet
D RE
N OT R
MENDE 43L210
R E C OM
ISL
Ultra Low ON-Resistance, Low Voltage,
Single Supply, DPDT Analog Switch
The Intersil ISL43L410 device is a low ON-resistance, low
voltage, bidirectional, double-pole/double-throw (DPDT)
analog switch designed to operate from a single +1.65V to
+3.6V supply. It is equipped with an inhibit pin to
simultaneously open all signal paths.
Targeted applications include battery powered equipment that
benefit from low RON (0.25 and fast switching speeds
(tON = 12ns, tOFF = 5ns). The digital logic input is 1.8V logiccompatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL43L410 is offered in small form factor packages, alleviating
board space limitations.
The ISL43L410 is a committed double-pole/double-throw
(DPDT) that consists of two normally open (NO) and two
normally closed (NC) switches. This configuration is perfect
for use in differential 2-to-1 multiplexer applications.
TABLE 1. FEATURES AT A GLANCE
ISL43L410
July 28, 2006
FN6090.2
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(see Ordering Info)
• ON Resistance (RON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4
• RON Matching Between Channels . . . . . . . . . . . . . . . .0.03
• RON Flatness Across Signal Range . . . . . . . . . . . . . . .0.03
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <0.2W
• Fast Switching Action (V+ = +2.7V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >9kV
• Guaranteed Break-before-Make
• 1.8V Logic Compatible (+3V supply)
• Available in 10 Ld 3x3 thin DFN and 10 Ld MSOP
Packages
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
ISL43L410
Number of Switches
2
SW
DPDT
3V RON
0.25
3V tON/tOFF
12ns/5ns
1.8V RON
0.4
1.8V tON/tOFF
20ns/8ns
Packages
10Ld 3x3 thin DFN, 10Ld MSOP
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL43L410
Pinout
Truth Table
(Note 1)
ISL43L410 (TDFN, MSOP)
TOP VIEW
INH
ADD
SWITCH ON
1
X
NONE
0
0
NCX
0
1
NOX
10 NO2
V+ 1
9 COM2
NO1 2
COM1 3
8 INH
ADD 4
7 NC2
NC1 5
6 GND
NOTE:
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Pin Descriptions
PIN
LOGIC
V+
NOTE:
1. Switches Shown for Logic “0” Input.
FUNCTION
System Power Supply Input (+1.65V to +3.6V)
GND
Ground Connection
INH
Digital Control Input. Connect to GND for Normal
Operation. Connect to V+ to turn all switches off.
ADD
Address Input Pin
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ISL43L410IR
L40
-40 to 85
10 Ld 3x3 thin DFN
L10.3x3A
ISL43L410IR-T
L40
-40 to 85
10 Ld 3x3 thin DFN Tape and Reel
L10.3x3A
ISL43L410IU
L410
-40 to 85
10 Ld MSOP
M10.118
ISL43L410IU-T
L410
-40 to 85
10 Ld MSOP Tape and Reel
M10.118
ISL43L410IRZ
(See Note)
L40Z
-40 to 85
10 Ld 3x3 thin DFN
(Pb-free)
L10.3x3A
ISL43L410IRZ-T
(See Note)
L40Z
-40 to 85
10 Ld 3x3 thin DFN Tape and Reel
(Pb-free)
L10.3x3A
ISL43L410IUZ
(See Note)
L410Z
-40 to 85
10 Ld MSOP
(Pb-free)
M10.118
ISL43L410IUZ-T
(See Note)
L410Z
-40 to 85
10 Ld MSOP Tape and Reel
(Pb-free)
M10.118
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6090.2
July 28, 2006
ISL43L410
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, ADD, INH (Note 2) . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical, Note 3)
JA (°C/W)
10 Ld 3x3 DFN Package . . . . . . . . . . . . . . . . . . . . .
110
10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . .
190
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL43L410IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, ADD, INH, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current
ratings.
3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
-
V+
V
25
-
0.29
0.4

Full
-
-
0.4

25
-
0.03
0.06

TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
See Figure 5
RON Matching Between Channels,
RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC= Voltage at max
RON, Note 9
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
Note 7
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V
Full
-
-
0.06

25
-
0.03
0.1

Full
-
-
0.1

nA
25
-2
-
2
Full
-40
-
40
nA
25
-3
-
3
nA
Full
-60
-
60
nA
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF,
See Figure 1, Note 8
25
-
14
20
Full
-
-
25
ns
25
-
6
12
ns
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF,
See Figure 1, Note 8
Full
-
-
17
ns
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF,
See Figure 3, Note 8
Full
2
7
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2
25
-
95
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 4
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 6
25
-
-95
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.003
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
115
-
pF
COM ON Capacitance, CCOM(ON)
25
-
224
-
pF
3
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
FN6090.2
July 28, 2006
ISL43L410
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4, 6),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
1.65
3.6
V
25
-
-
40
nA
Full
-
-
750
nA
Full
-
-
0.5
V
TYP
(NOTE 5)
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +1.65 to 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+ (Note 8)
Full
1.4
-
-
V
Full
-0.5
-
0.5
A
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed but not tested.
9. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
value.
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
-
V+
V
25
-
0.4
0.6

TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+,
See Figure 5, Note 8
Full
-
-
0.6

NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 2.0V, VCOM = 0.3V, 1.8V, VNO or VNC = 1.8V, 0.3V
25
-2
-
2
nA
Full
-40
-
40
nA
COM ON Leakage Current,
ICOM(ON)
V = 2.0V, VCOM = 0.3V, 1.8V, or VNO or VNC = 0.3V,
1.8V
25
-3
-
3
nA
Full
-60
-
60
nA
V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF,
See Figure 1, Note 8
25
-
22
28
ns
Full
-
-
33
ns
V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF,
See Figure 1, Note 8
25
-
9
15
ns
Full
-
-
20
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
V+ = 2.0V, VNO or VNC = 1.0V, RL =50, CL = 35pF,
See Figure 3, Note 8
Full
2
9
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2
25
-
49
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 4
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 6
25
-
-95
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
115
-
pF
COM ON Capacitance, CCOM(ON)
25
-
224
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1.0
-
-
V
Full
-0.5
-
0.5
A
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 8)
4
FN6090.2
July 28, 2006
ISL43L410
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 5ns
tf < 5ns
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
COM
ADD
90%
SWITCH
OUTPUT
VOUT
NO or NC
90%
0V
LOGIC
INPUT
GND
INH
CL
35pF
RL
50
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R L + R  ON 
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO or NC
VOUT
VG
INH
GND
ADD
CL
V+
ON
ON
LOGIC
INPUT
OFF
LOGIC
INPUT
0V
Q = VOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
VNX
V+
NO
0V
RL
50
ADD
LOGIC
INPUT
VOUT
COM
NC
LOGIC
INPUT
SWITCH
OUTPUT
VOUT
C
GND
CL
35pF
INH
90%
0V
tD
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5
FN6090.2
July 28, 2006
ISL43L410
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
RON = V1/100mA
NO or NC
NO or NC
ADD
VNX
0V or V+
100mA
0V or V+
ADD
V1
COM
ANALYZER
GND INH
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
INH
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50
NO or NC
ADD
ADD 0V or V+
0V or V+
IMPEDANCE
ANALYZER
NC or NO
COM
ANALYZER
GND
INH
COM
N.C.
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
INH
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
Supply Sequencing And Overvoltage Protection
The ISL43L410 is a bidirectional, double pole/double throw
(DPDT) analog switch that offers precise switching capability
from a single 1.65V to 3.6V supply with low on-resistance
(0.25) and high speed operation (tON = 12ns, tOFF = 5ns).
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.65V), low power consumption (2.7W max), low leakage
currents (60nA max), and the tiny DFN and MSOP packages.
The ultra low on-resistance and Ron flatness provide very low
insertion loss and distortion to applications that require signal
reproduction.
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
6
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
FN6090.2
July 28, 2006
ISL43L410
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (See Figure 15). At 3.6V
the VIH level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50 systems, the signal response is reasonably flat
even past 30MHz with a -3dB bandwidth of 120MHz (See
Figure 16). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 17 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 68dB in 50 systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Power-Supply Considerations
The ISL43L410 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL43L410 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
7
FN6090.2
July 28, 2006
ISL43L410
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
0.32
0.7
V+ = 1.5V
0.6
V+ = 2.7V
ICOM = 100mA
ICOM = 100mA
0.3
85°C
0.28
RON ()
RON ()
0.5
0.4
V+ = 1.8V
0.3
V+ = 3.6V
V+ = 2.7V
0.26
25°C
0.24
0.22
0.2
V+ = 3V
0.1
0.18
0
-40°C
0.2
1
2
3
4
0
0.5
1
VCOM (V)
0.5
2.5
3
100
V+ = 1.8V
ICOM = 100mA
75
85°C
V+ = 3V
0.4
50
0.35
Q (pC)
RON ()
2
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.45
1.5
VCOM (V)
25
V+ = 1.8V
0.3
0
25°C
-40°C
0.25
-25
0.2
0
0.5
1
1.5
-50
2
VCOM (V)
0
0.5
1
1.5
2
2.5
3
VCOM (V)
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
60
14
13
12
50
10
40
tOFF (ns)
tON (ns)
11
30
85°C
8
-40°C
7
85°C
25°C
6
20
25°C
5
-40°C
10
9
1
1.5
4
2
2.5
3
V+ (V)
3.5
4
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
8
4.5
3
1
1.5
2
2.5
3
3.5
4
4.5
V+ (V)
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
FN6090.2
July 28, 2006
ISL43L410
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
1.4
1.3
VINH AND VINL (V)
1.2
1.1
VINH
1
0.9
V+ = 3V
0
GAIN
-20
0
PHASE
20
0.8
40
VINL
0.7
60
0.6
80
0.5
0.4
0.3
RL = 50
VIN = 0.2VP-P to 2VP-P
1
1.5
2
2.5
3
3.5
4
4.5
V+ (V)
1
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
-10
100
600
FIGURE 16. FREQUENCY RESPONSE
10
V+ = 3V
-20
20
Die Characteristics
-30
30
SUBSTRATE POTENTIAL (POWERED UP):
-40
40
-50
50
-60
60
ISOLATION
-70
70
-80
80
CROSSTALK
-90
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
90
-100
-110
1k
GND
OFF ISOLATION (dB)
CROSSTALK (dB)
10
100
FREQUENCY (MHz)
PHASE (DEGREES)
NORMALIZED GAIN (dB)
1.5
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 17. CROSSTALK AND OFF ISOLATION
9
FN6090.2
July 28, 2006
ISL43L410
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
0.25
1
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
NOMINAL
D2/2
(DATUM A)
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
10
FN6090.2
July 28, 2006
ISL43L410
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
E
INCHES
SYMBOL
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X 
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X 
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
-A-
e
D
0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-B-
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
e
L1
MIN
0.020 BSC
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
10
10
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-

5o
15o
5o
15o
-

0o
6o
0o
6o
-
END VIEW
Rev. 0 12/02
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
FN6090.2
July 28, 2006
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