DATASHEET

ISL54056
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August 15, 2007
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ISL5
FN6357.4
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Quad SPDT (Dual DPDT)
Analog Switch
Features
The Intersil ISL54056 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.65V to +4.5V
supply. Targeted applications include battery powered
equipment that benefit from low rON (0.39 and fast
switching speeds (tON = 30ns, tOFF = 16ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 12µA max of ICC
current.
• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54056 is offered in small form factor package, alleviating
board space limitations.
The ISL54056 consists of four SPDT switches. It is configured
as a dual double-pole/double-throw (DPDT) device with two
logic control inputs that control two SPDT switches each. The
configuration can be used as a dual differential 2-to-1
multiplexer/demultiplexer. The ISL54056 is pin compatible
with the NLAS3799 and NLAS3799L.
TABLE 1. FEATURES AT A GLANCE
• Pin Compatible Replacement for the NLAS3799 and
NLAS3799L
• rON Matching between Channels . . . . . . . . . . . . . . . . . 0.05
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.68W
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns
• Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 16 Ld 2.6mmx1.8mmx0.5mm µTQFN
• ESD HBM Rating
- COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• Pb-Free Available (RoHS Compliant)
Applications
ISL54056
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
Number of Switches
4
SW
Quad SPDT (Dual DPDT)
4.3V rON
0.39
4.3V tON/tOFF
30ns/16ns
3.0V rON
0.45
3.0V tON/tOFF
34ns/18ns
1.8V rON
0.65
Related Literature
1.8V tON/tOFF
48ns/23ns
Package
16 Ld 2.6x1.8x0.5mm µTQFN
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54056
Pinouts
Truth Table
(Note 1)
8
NC3
9
NC SW
NO SW
0
ON
OFF
1
OFF
ON
NO3
GND
NC2
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Pin Descriptions
PIN
V+
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
4
7
IN3-4
10
COM
COM2
3
NO2
2
COM3
6
NO4
11
NC1
LOGIC
NOTE:
5
COM4
13
14
1
COM1
IN1-2
NO1
15
V+
16
NC4
12
ISL54056
(16 LD ΜTQFN)
TOP VIEW
NOTE:
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
1. Switches Shown for Logic “0” Input.
Ordering Information
PART NUMBER
ISL54056IRUZ-T* (Note)
PART MARKING
TEMP. RANGE (°C)
GAA
-40 to +85
PACKAGE
16 Ld TQFN Tape and Reel (Pb-free)
PKG. DWG. #
L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6357.4
August 15, 2007
ISL54056
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA
ESD Rating
Human Body Model (COMX) . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
Human Body Model (NOX, NCX, INX, V+, GND) . . . . . . . . . .>6kV
Machine Model (COMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700V
Machine Model (NOX, NCX, INX, V+, GND) . . . . . . . . . . . . .>300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical)
JA (°C/W)
TQFN Package (Note 3) . . . . . . . . . . . . . . . . . . . .
93
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL54056IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 8)
Full
0
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5)
rON Matching Between Channels,
rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Note 7)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V
V+
V
25
0.4
0.55

Full
0.45
0.65

25
0.05
0.12

Full
0.06
0.15

25
0.05
0.15

Full
0.05
0.15

25
-70
70
nA
Full
-165
165
nA
25
-70
70
nA
Full
-165
165
nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 1)
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 1)
Turn-OFF Time, tOFF
25
33
ns
Full
38
ns
25
16
ns
Full
21
ns
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL =
35pF (See Figure 3)
Full
3
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
248
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
65
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
0.008
%
3
FN6357.4
August 15, 2007
ISL54056
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
38
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
102
pF
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
4.5
V
25
0.15
A
Full
1.4
A
25
12
A
Input Voltage Low, VINL
Full
0.5
V
Input Voltage High, VINH
Full
1.6
Full
-0.5
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
1.65
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
V
0.5
A
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 8)
Full
0
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5)
rON Matching Between Channels,
rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Note 7)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
0.45
Full
25
0.05
Full
25
0.07
Full
V+
V
0.55

0.65

0.12

0.15

0.15

0.15

25
1.1
nA
Full
30
nA
25
1.5
nA
Full
45
nA
25
34
ns
Full
39
ns
25
18
ns
Full
23
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1)
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL =
35pF (See Figure 3)
Full
3
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2)
25
126
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
65
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
0.012
%
4
FN6357.4
August 15, 2007
ISL54056
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
38
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
102
pF
25
0.021
A
Full
0.72
A
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
Input Voltage High, VINH
Full
1.4
Full
-0.5
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
0.5
V
V
A
0.5
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 8)
Full
0
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5)
ON-Resistance, rON
25
0.65
Full
V+
V
0.8

0.85

DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50,
CL = 35pF (See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50,
CL = 35pF (See Figure 1)
25
50
ns
Full
55
ns
25
25
ns
Full
30
ns
Break-Before-Make Time Delay, tD V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF
(See Figure 3)
Full
8
ns
Charge Injection, Q
25
48
pC
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
Input Voltage High, VINH
Full
1.0
Full
-0.5
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
0.4
V
V
A
0.5
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
5
FN6357.4
August 15, 2007
ISL54056
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
VOUT
NO or NC
COM
IN
90%
SWITCH
OUTPUT
C
50%
90%
LOGIC
INPUT
0V
CL
35pF
RL
50
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------R L + r ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
VOUT
V+
LOGIC
INPUT
ON
ON
OFF
C
VG
VOUT
COM
NO or NC
GND
IN
CL
0V
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
VNX
NO
RL
50
IN
SWITCH
OUTPUT
VOUT
90%
0V
LOGIC
INPUT
VOUT
COM
NC
0V
C
CL
35pF
GND
tD
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6357.4
August 15, 2007
ISL54056
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V1/100mA
SIGNAL
GENERATOR
NO OR NC
NO OR NC
VNX
IN
0V OR V+
100mA
0V OR V+
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO OR NC
COM
50
NO OR NC
IN1
IN
0V OR V+
NC OR NO
COM
ANALYZER
0V OR V+
IMPEDANCE
ANALYZER
GND
COM
NC
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54056 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
ON-resistance (0.39) and high speed operation
(tON = 30ns, tOFF = 16ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(6.3µW max), low leakage currents (165nA max), and the tiny
µTQFN package. The ultra low ON-resistance and rON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100 resistor in series with the V+
power supply pin of the ISL54056 IC (see Figure 8).
7
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation the sub-microamp IDD current of the
IC produces an insignificant voltage drop across the 100
series resistor resulting in no impact to switch operation or
performance.
FN6357.4
August 15, 2007
ISL54056
V+
OPTIONAL
PROTECTION
RESISTOR
C
OPTIONAL
SCHOTTKY
DIODE
V+
100
OPTIONAL
PROTECTION
RESISTOR
NOx
COMx
NCx
INX
VNX
VCOM
INx
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
GND
FIGURE 9. OVERVOLTAGE PROTECTION
Supply Sequencing and Overvoltage Protection
Power-Supply Considerations
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
The ISL54056 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4.7V maximum supply voltage, the ISL54056 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1k resistor in series
with the logic input (see Figure 9). The resistor limits the input
current below the threshold that produces permanent damage,
and the sub-microamp input current produces an insignificant
voltage drop during normal operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins as shown in Figure 9 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” table on page 5 and “Typical
Performance Curves” on page 9 for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 3.0V to 4.5V (see Figure 19). At 3.0V
the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
The ISL54056 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply
the device draws only 12A of current (see Figure 17 for
VIN = 2.85V).
8
FN6357.4
August 15, 2007
ISL54056
High-Frequency Performance
Leakage Considerations
In 50 systems, the ISL54056 has a -3dB bandwidth of
104MHz (see Figure 22). The frequency response is very
consistent over a wide V+ range, and for varying analog
signal levels.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 23 details the high off isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 65dB
in 50 systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog signal
path leakage current. All analog leakage current flows between
each pin and one of the supply terminals, not to the other
switch terminal. This is why both sides of a given switch can
show leakage currents of the same or opposite polarity.
There is no connection between the analog signal paths and
V+ or GND.
Typical Performance Curves TA = +25°C, unless otherwise specified
0.40
0.46
ICOM = 100mA
0.39
0.44
0.38
0.43
V+ = 2.7V
0.42
rON ()
rON ()
0.37
0.36
0.35
0.41
0.40
V+ = 3V
0.39
V+ = 3.9V
0.34
0.38
V+ = 4.3V
0.33
0.32
ICOM = 100mA
0.45
V+ = 4.5V
0
1
V+ = 3.3V
0.37
2
3
4
0.36
5
0
0.5
1.0
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
1.5
2.0
VCOM (V)
2.5
3.0
3.5
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.45
0.8
V+ = 4.3V
ICOM = 100mA
ICOM = 100mA
V+ = 1.65V
0.40
0.7
+85°C
rON ()
rON ()
V+ = 1.8V
0.6
0.35
+25°C
V+ = 2V
0.30
0.5
-40°C
0.25
0.4
0
0.5
1.0
1.5
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
9
2.0
0
1
2
3
4
5
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6357.4
August 15, 2007
ISL54056
Typical Performance Curves TA = +25°C, unless otherwise specified (Continued)
0.55
0.50
V+ = 3.3V
ICOM = 100mA
0.45
V+ = 2.7V
ICOM = 100mA
0.50
0.40
+85°C
+85°C
0.40
+25°C
+25°C
0.35
0.30
rON ()
rON ()
0.45
0.35
-40°C
0
0.5
1.0
1.5
2.0
2.5
3.0
0.30
3.5
-40°C
0
0.5
1.0
VCOM (V)
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
0.70
+25°C
2.5
200
3.0
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
150
-40°C
0.55
ION (A)
rON ()
0.60
2.0
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
V+ = 1.8V
ICOM = 100mA
+85°C
0.65
1.5
VCOM (V)
0.50
0.45
100
50
0.40
0.35
0
0
0.5
1.0
VCOM (V)
1.5
1
2.0
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
1.0
200
0.9
0.8
VINH AND VINL (V)
150
Q (pC)
4
5
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
250
100
50
V+ = 4.3V
0
VINH
0.7
0.6
VINL
0.5
0.4
V+ = 1.8V
V+ = 3V
-50
-100
2
3
VIN1, VIN 2 (V)
0.3
0
1
2
3
4
5
VCOM (V)
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
10
0.2
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6357.4
August 15, 2007
ISL54056
Typical Performance Curves TA = +25°C, unless otherwise specified (Continued)
250
40
35
200
30
tOFF (ns)
100
25
+85°C
20
+85°C
50
+25°C
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
10
1.0
4.5
-10
V+ = 3V
GAIN
-20
0
PHASE
20
60
80
1M
PHASE (°)
40
RL = 50
VIN = 0.2VP-P to 2VP-P
100
10M
100M
FREQUENCY (Hz)
FIGURE 22. FREQUENCY RESPONSE
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
600M
CROSSTALK (dB)
NORMALIZED GAIN (dB)
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
0
-40°C
15
-40°C
0
1.0
+25°C
10
V+ = 4.3V
-20
20
-30
30
-40
40
-50
-60
50
ISOLATION
60
-70
70
-80
80
CROSSTALK
-90
90
-100
-110
1k
OFF ISOLATION (dB)
tON (ns)
150
100
10k
100k
1M
10M
FREQUENCY (Hz)
110
100M 500M
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
11
FN6357.4
August 15, 2007
ISL54056
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
L16.2.6x1.8A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
2X
A
N
SYMBOL
E
0.10 C
1 2
2X
0.10 C
0.10 C
C
A
A1
SIDE VIEW
e
PIN #1 ID
0.55
-
-
0.05
-
0.127 REF
BOTTOM VIEW
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
0.40 BSC
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
0
-
12
4
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
L
5
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
e
SECTION "C-C"
-
Rev. 4 8/06
NX b 5
16X
0.10 M C A B
0.05 M C
(DATUM A)
NX (b)
0.50
-
NX L
(DATUM B)
NOTES
0.45

1 2
L1
MAX
A
e
SEATING PLANE
NOMINAL
A1
A3
TOP VIEW
0.05 C
MIN
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.20
0.50
0.20
0.40
10 LAND PATTERN
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN6357.4
August 15, 2007
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