DATASHEET

ISL84582
®
Data Sheet
May 6, 2009
Low-Voltage, Single and Dual Supply,
Differential 4-to-1 Multiplexer
Features
• Pb-Free (RoHS Compliant)
The Intersil ISL84582 device is made of precision,
bi-directional, analog switches configured as a differential
4-Channel multiplexer/demultiplexer. It is designed to operate
from a single +2V to +12V supply or from a ±2V to ±6V dual
supplies. The device has an inhibit pin to simultaneously open
all signal paths.
ON-resistance of 39Ω with a ±5V supply and 125Ω with a
single +3.3V supply. Each switch can handle rail-to-rail
analog signals. The off-leakage current is only 0.02nA at
+25°C or 0.2nA at +85°C.
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single 3.3V or
+5V supply or dual ±5V supplies.
The ISL84582 is a differential 4-to-1 multiplexer device.
Table 1 summarizes the performance of this part.
DIFF 4:1 Mux
±5V rON
39Ω
±5V tON/tOFF
32ns/18ns
12V rON
32Ω
12V tON/tOFF
23ns/15ns
5V rON
65Ω
5V tON/tOFF
43ns/20ns
3.3V rON
125Ω
3.3V tON/tOFF
70ns/32ns
Package
16 Ld TSSOP
• ON-resistance (rON), VS = ±4.5V . . . . . . . . . . . . . . . . 44Ω
• ON-resistance (rON), VS = +3V . . . . . . . . . . . . . . . . 175Ω
• rON Matching Between Channels, VS = ±5V . . . . . . . . . <2Ω
• Low Charge Injection, VS = ±5V . . . . . . . . . . . . . 1pC (Max)
• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V
• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . ±2V to ±6V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<3µW
• Fast Switching Action (VS = +5V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
• Guaranteed Break-Before-Make
• TTL, CMOS Compatible
Applications
• Battery Powered, Handheld, and Portable Equipment
• Communications Systems
- Radios
- Telecom Infrastructure
- ADSL, VDSL Modems
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
• Application Note AN520 “CMOS Analog Multiplexers and
Switches; Specifications and Application Considerations.”
• Application Note AN1034 “Analog Switch and Multiplexer
Applications”
1
• Fully Specified at 3.3V, 5V, ±5V, and 12V Supplies for 10%
Tolerances
• Guaranteed Max Off-Leakage . . . . . . . . . . . . . . . . . . . 2.5nA
TABLE 1. FEATURES AT A GLANCE
CONFIGURATION
FN6213.3
• Test Equipment
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners (MRI)
- ATE
- Electrocardiograph
• Audio and Video Signal Routing
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84582
Pinout
ISL84582
(16 LD TSSOP)
TOP VIEW
B0 1
16 V+
B1 2
15 A1
COMB 3
14 A2
B3 4
13 COMA
B2 5
12 A0
INH 6
11 A3
V- 7
GND 8
Truth Table
LOGIC
10 ADDB
9 ADDA
Pin Descriptions
ISL84582
PIN
FUNCTION
INH
ADDB
ADDA
SWITCH ON
V+
Positive Power Supply Pin
1
X
X
NONE
V-
0
0
0
A0, B0
Negative Power Supply Pin. Connect to GND for Single
Supply Configurations.
0
0
1
A1, B1
0
1
0
A2, B2
0
1
1
A3, B3
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 3V and
10V. X = Don’t Care.
GND
Ground Connection
INH
Digital Control Input. Connect to GND for Normal
Operation. Connect to V+ to turn all switches off.
COMx
Analog Mux Common Pin
Ax, Bx
Analog Mux Signal Pin
ADDx
Address Input Pin
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
ISL84582IVZ
84582 IVZ
-40 to +85
16 Ld TSSOP M16.173
ISL84582IVZ-T* 84582 IVZ
-40 to +85
16 Ld TSSOP M16.173
Tape and Reel
PACKAGE
(Pb-Free)
PKG.
DWG. #
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2
FN6213.3
May 6, 2009
ISL84582
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
Input Voltages
INH, NO, NC, ADD (Note 1) . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating
Human Body Model (Per Mil-STD-883, Method 3015.7) . . . >2kV
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
150
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on NC, NO, COM, ADD, INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications: ±5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 4, 10)
TYP
MAX
(Notes 4, 10) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
(Note 9)
Full
V-
-
V+
V
ON-resistance, rON
VS = ±4.5V, ICOM = 2mA, VNO or VNC = 3V,
(See Figure 5)
25
-
44
60
Ω
Full
-
-
80
Ω
rON Matching Between Channels, VS = ±4.5V, ICOM = 2mA, VNO or VNC = 3V, (Note 5)
ΔrON
25
-
1.3
4
Ω
Full
-
-
6
Ω
rON Flatness, RFLAT(ON)
25
-
7.5
9
Ω
Full
-
-
12
Ω
25
-
0.02
-
nA
Full
-
0.2
-
nA
25
-
0.02
-
nA
Full
-
0.2
-
nA
25
-
0.02
-
nA
Full
-
0.2
-
nA
Input Voltage High, VINHH,
VADDH
Full
2.4
-
-
V
Input Voltage Low, VINHL, VADDL
Full
-
-
0.8
V
VS = ±5.5V, VINH, VADD = 0V or V+, (Note 9)
Full
-0.5
0.03
0.5
µA
Inhibit Turn-ON Time, tON
VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3 (see Figure 1, Note 9)
25
-
35
50
ns
Inhibit Turn-OFF Time, tOFF
VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3 (see Figure 1, Note 9)
VS = ±4.5V, ICOM = 2mA, VNO or VNC = ±3V, 0.1V,
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V,
(Note 7)
COM OFF Leakage Current,
ICOM(OFF)
VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V,
(Note 7)
COM ON Leakage Current,
ICOM(ON)
VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, (Note 7)
DIGITAL INPUT CHARACTERISTICS
Input Current, IADDH, IADDL,
IINHH, IINHL
DYNAMIC CHARACTERISTICS
Address Transition Time, tTRANS
3
VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3 (see Figure 1, Note 9)
Full
-
-
60
ns
25
-
22
35
ns
Full
-
-
40
ns
25
-
43
60
ns
Full
-
-
70
ns
FN6213.3
May 6, 2009
ISL84582
Electrical Specifications: ±5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 4, 10)
TYP
MAX
(Notes 4, 10) UNITS
Break-Before-Make Time, tBBM
VS = ±5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 3, Note 9)
Full
2
7
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2, Note 9)
25
-
0.3
1
pC
NO/NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
3
-
pF
COM OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
12
-
pF
COM ON Capacitance,
CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
-
18
-
pF
OFF-Isolation
RL = 50Ω, CL = 15pF, f = 100kHz,
VNOx = 1VRMS (see Figures 4, 6 and 19)
25
-
92
-
dB
25
-
≤110
-
dB
25
-
-105
-
dB
Full
±4.5
-
±5.5
V
Full
-1
-
1
µA
Full
-1
-
1
µA
Crosstalk, (Note 8)
All Hostile Crosstalk, (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
VS = ±5.5V, VINH, VADD = 0V or V+, Switch On or Off,
(Note 9)
Positive Supply Current, I+
Negative Supply Current, I-
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 4, 10)
MAX
TYP (Notes 4, 10) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
(Note 9)
Full
0
-
V+
V
ON-resistance, rON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V,
(See Figure 5)
25
-
37
45
Ω
Full
-
-
55
Ω
rON Matching Between Channels,
ΔrON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V, (Note 5)
Full
-
1.2
2
Ω
rON Flatness, RFLAT(ON)
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V,
(Note 6)
Full
-
5
-
Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V,
(Note 7)
25
-
0.02
-
nA
Full
-
0.2
-
nA
COM OFF Leakage Current,
ICOM(OFF)
V+ = 13.2V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V,
(Note 7)
25
-
0.02
-
nA
Full
-
0.2
-
nA
COM ON Leakage Current,
ICOM(ON)
V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V,
or floating, (Note 7)
25
-
0.02
-
nA
Full
-
0.2
-
nA
Input Voltage High, VINHH, VADDH
Full
3.7
-
-
V
Input Voltage Low, VINHL, VADDL
Full
-
-
0.8
V
Full
-0.5
-
0.5
µA
DIGITAL INPUT CHARACTERISTICS
Input Current, IADDH, IADDL,
IINHH, IINHL
V+ = 13.2V, VINH, VADD = 0V or V+
4
FN6213.3
May 6, 2009
ISL84582
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 4, 10)
MAX
TYP (Notes 4, 10) UNITS
DYNAMIC CHARACTERISTICS
V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 4, (See Figure 1, Note 9)
Inhibit Turn-ON Time, tON
25
-
24
40
ns
Full
-
-
45
ns
25
-
15
30
ns
Full
-
-
35
ns
25
-
27
50
ns
Full
-
-
55
ns
Break-Before-Make Time Delay, tD V+ = 13.2V, RL = 300Ω, CL = 35pF, VNO or VNC = 10V,
VIN = 0 to 4, (See Figure 3, Note 9)
Full
2
5
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2, Note 9)
25
-
2.7
5
pC
OFF-Isolation
RL = 50Ω, CL = 15pF, f = 100kHz,
(See Figure 4, 6 and 19)
25
-
92
-
dB
Crosstalk, (Note 8)
25
-
≤110
-
dB
All Hostile Crosstalk, (Note 8)
25
-
-105
-
dB
V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 4, (See Figure 1, Note 9)
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 4, (See Figure 1, Note 9)
NO or NC OFF Capacitance,
COFF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
3
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
12
-
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
18
-
pF
Full
10.8
-
13.2
V
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
V+ = 13.2V, VINH, VADD = 0V or V+, all channels on or
off (Note 9)
Positive Supply Current, I+
Electrical Specifications: 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 4, 10) TYP (Notes 4, 10) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
(Note 9)
ON-Resistance, rON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,
(See Figure 5)
Full
0
-
V+
V
25
-
81
100
Ω
Full
-
-
120
Ω
25
-
2.2
4
Ω
Full
-
-
6
Ω
Full
-
11.5
-
Ω
Input Voltage High, VINHH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINHL, VADDL
Full
-
-
0.8
V
Input Current, IADDH, IADDL, IINHH, V+ = 5.5V, VINH, VADD = 0V or V+, (Note 9)
IINHL
Full
-0.5
-
0.5
µA
rON Matching Between Channels,
ΔrON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3V, (Note 5)
rON Flatness, RFLAT(ON)
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V,
(Note 6)
DIGITAL INPUT CHARACTERISTICS
5
FN6213.3
May 6, 2009
ISL84582
Electrical Specifications: 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 4, 10) TYP (Notes 4, 10) UNITS
DYNAMIC CHARACTERISTICS
V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 1, Note 9)
Inhibit Turn-ON Time, tON
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
25
-
43
60
ns
Full
-
-
70
ns
V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 1, Note 9)
25
-
20
35
ns
Full
-
-
40
ns
V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 1, Note 9)
25
-
51
70
ns
Full
-
-
85
ns
Break-Before-Make Time, tBBM
V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, (See Figure 3, Note 9)
Full
2
9
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2, Note 9)
25
-
0.6
1.5
pC
OFF-Isolation
RL = 50Ω, CL = 15pF, f = 100kHz,
VNOx = 1VRMS (see Figures 4, 6 and 19)
25
-
92
-
dB
25
-
≤110
-
dB
25
-
-105
-
dB
Full
4.5
-
5.5
V
Full
-1
-
1
µA
Crosstalk, (Note 8)
All Hostile Crosstalk, (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+,
Switch On or Off, (Note 9)
Electrical Specifications: 3.3V Supply Test Conditions: V+ = +3V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3) Unless
Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 4, 10) TYP (Notes 4, 10) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
(Note 9)
Full
0
-
V+
V
ON-Resistance, rON
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V
(See Figure 5)
25
-
175
180
Ω
Full
-
-
200
Ω
25
-
3.4
8
Ω
Full
-
-
10
Ω
Full
-
55
-
Ω
Input Voltage High, VINHH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINHL, VADDL
Full
-
-
0.8
V
V+ = 3.6V, VINH, VADD = 0V or V+, (Note 9)
Full
-0.5
-
0.5
µA
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 1, Note 9)
25
-
82
100
ns
Full
-
-
120
ns
25
-
37
50
ns
Full
-
-
60
ns
25
-
96
120
ns
Full
-
-
145
ns
rON Matching Between Channels,
ΔrON
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V, (Note 5)
rON Flatness, RFLAT(ON)
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 2V,
(Note 6)
DIGITAL INPUT CHARACTERISTICS
Input Current, IADDH, IADDL,
IINHH, IINHL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, tON
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 1, Note 9)
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
6
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 1, Note 9)
FN6213.3
May 6, 2009
ISL84582
Electrical Specifications: 3.3V Supply Test Conditions: V+ = +3V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3) Unless
Otherwise Specified. (Continued)
PARAMETER
TEMP
MIN
MAX
(°C) (Notes 4, 10) TYP (Notes 4, 10) UNITS
TEST CONDITIONS
Break-Before-Make Time, tBBM
V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V (see Figure 3, Note 9)
Full
3
13
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2, Note 9)
25
-
0.3
1
pC
OFF-Isolation
RL = 50Ω, CL = 15pF, f = 100kHz,
VNO or VNC = 1VRMS (see Figures 4, 6 and 19)
25
-
92
-
dB
25
-
≤110
-
dB
25
-
-105
-
dB
Full
3.0
-
3.6
V
Full
-1
-
1
µA
Crosstalk, (Note 8)
All Hostile Crosstalk, (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+,
Switch On or Off, (Note 9)
NOTES:
3. VIN = Input logic voltage to configure the device in a given state.
4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. ΔrON = rON (MAX) - rON (MIN).
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C.
8. Between any two switches.
9. Limits established by characterization and are not production tested.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Test Circuits and Waveforms
V+
3V
LOGIC
INPUT
tr < 20ns
tf < 20ns
50%
C
C
C
ISL84582
0V
V+
tON
NO0x
NO1x-NO3x
VNO0
SWITCH
OUTPUT
V-
90%
VOUT
INH
90%
LOGIC
INPUT
COMx
GND ADDA-B
VOUT
RL
300Ω
CL
35pF
0V
tOFF
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
7
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) ---------------------------R L + r ( ON )
FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
FN6213.3
May 6, 2009
ISL84582
Test Circuits and Waveforms (Continued)
3V
LOGIC
INPUT
tr < 20ns
tf < 20ns
50%
V+
C
V-
C
C
0V
tTRANS
V+
VOUT
VNO0
SWITCH
OUTPUT
NO0x
VC
90%
ISL84582
NO3x
ADDA-B
0V
VOUT
COMx
NO1x-NO2x
GND
EN
LOGIC
INPUT
10%
VNOX
CL
35pF
RL
300Ω
tTRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------R L + r ON
FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
V-
C
C
3V
LOGIC
INPUT
OFF
OFF
VOUT
RG
ON
COM
NO OR NC
0V
0Ω
ADDX
SWITCH
OUTPUT
VOUT
ΔVOUT
VG
GND
INH
CL
1nF
LOGIC
INPUT
Q = ΔVOUT x CL
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2A. Q MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
3V
COMx
NO0x-NO3x
V+
0V
V-
C
C
tr < 20ns
tf < 20ns
LOGIC
INPUT
C
ISL84582
VOUT
CL
35pF
RL
300Ω
ADDA-B
80%
SWITCH
OUTPUT
VOUT
LOGIC
INPUT
GND
INH
0V
tBBM
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 3A. tBBM MEASUREMENT POINTS
FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
8
FN6213.3
May 6, 2009
ISL84582
Test Circuits and Waveforms (Continued)
V+
V-
C
V+
C
V-
C
C
rON = V1/1mA
SIGNAL
GENERATOR
NO OR NC
NO OR NC
VNX
0V OR V+
1mA
ADDX
COM
ANALYZER
0V OR V+
GND
0V OR V+
V1
ADDX
COM
INH
INH
GND
RL
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
V+
SIGNAL
GENERATOR
V-
C
NOA OR NCA
FIGURE 5. rON TEST CIRCUIT
C
V+
V-
C
C
50Ω
COMA
NO OR NC
0V OR V+
ADDX
ADDX
IMPEDANCE
ANALYZER
NOB OR NCB
ANALYZER
0V OR V+
ISL84582
COMB
GND
INH
NC
COM
GND
INH
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
9
FIGURE 7. CAPACITANCE TEST CIRCUIT
FN6213.3
May 6, 2009
ISL84582
Detailed Description
Power-Supply Considerations
The ISL84582 multiplexer offers precise switching capability
from a bipolar ±2V to ±6V or a single 2V to 12V supply with
low ON-resistance (39Ω) and high speed operation
(tON = 38ns, tOFF = 19ns) with dual 5V supplies. The device
is especially well suited to portable battery-powered
equipment thanks to the low operating supply voltage (2V),
low power consumption (3µW), low leakage currents (0.2nA).
High frequency applications also benefit from the wide
bandwidth, and the very high off-isolation and crosstalk
rejection.
The ISL84582 construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V absolute maximum voltage, the ISL84582 15V
absolute maximum voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 8). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1kΩ
OPTIONAL PROTECTION
DIODE
V+
LOGIC
VNO OR NC
VCOM
VOPTIONAL PROTECTION
DIODE
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
10
The ISL84582 performs equally well when operated with
bipolar or single voltage supplies. The minimum
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
“Electrical Specification” tables beginning on page 5 and
“Typical Performance Curves” beginning on page 11 for
details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This ISL84582 is TTL compatible
(0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At
12V the VIH level is about 3.3V. This is still below the CMOS
guaranteed high output minimum level of 4V, but noise
margin is reduced. For best results with a 12V supply, use a
logic family that provides a VOH greater than 4V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figures 17 and 18). Figures 17 and 18 also
illustrates that the frequency response is very consistent
over varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off-Isolation is the
resistance to this feed-through, while Crosstalk indicates the
amount of feed through from one switch to another. Figure 19
details the high Off-Isolation and Crosstalk rejection
provided by this family. At 10MHz, Off-Isolation is about
55dB in 50Ω systems, decreasing approximately 20dB per
decade as frequency increases. Higher load impedances
decrease Off-Isolation and Crosstalk rejection due to the
voltage divider action of the switch OFF impedance and the
load impedance.
FN6213.3
May 6, 2009
ISL84582
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified.
70
VCOM = (V+) - 1V
ICOM = 1mA
V- = -5V
60
50
+85°C
40
+25°C
30
-40°C
20
400
rON (Ω)
rON (Ω)
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and GND.
V- = 0V
300
200
+85°C
120
110
100
90
80
70
60
50
90
80
70
60
50
40
30
60
+25°C
3
5
6
7
V+ (V)
8
9
+25°C
-40°C
VS = ±5V
+85°C
+25°C
10
11
-40°C
20
-5
12
-4
-3
-2
-1
0
1
VCOM (V)
2
4
3
5
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
60
225
200
ICOM = 1mA
ICOM = 1mA
55
175
150
+85°C
125
100
+25°C
V+ = 12V
V- = 0V
50
V+ = 2.7V
V- = 0V
-40°C
45
rON (Ω)
rON (Ω)
VS = ±3V
+85°C
30
4
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE
75
160
140
120
100
80
60
100
90
80
70
60
50
40
-40°C
40
-40°C
2
VS = ±2V
+85°C
+25°C
50
100
0
ICOM = 1mA
+85°C
+25°C
V+ = 3.3V
-40°C
V- = 0V
+85°C
40
35
+25°C
30
V+ = 5V
+85°C
V- = 0V
25
+25°C
-40°C
-40°C
0
1
3
2
4
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
11
20
5
0
2
4
6
VCOM (V)
8
10
12
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
FN6213.3
May 6, 2009
ISL84582
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
200
500
400 -40°C
+25°C
200
50
+85°C
tOFF (ns)
tON (ns)
+25°C
+25°C
-40°C
V- = 0V
200
V- = 0V
80
50
20
0
3
5
4
6
7
V+ (V)
9
8
10
11
300
0
12
-40°C
2
3
4
6
5
8
7
V+ (V)
VCOM = (V+) - 1V
V- = 0V
200
tRANS (ns)
200
150
150
100
+25°C
100
+25°C
+85°C
+85°C
50
50
-40°C
-40°C
0
3
4
5
6
7
8
V+ (V)
9
10
11
12
3
4
5
6
V± (V)
NORMALIZED GAIN (dB)
FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY
VOLTAGE
VIN = 0.2VP-P to 5VP-P
3
GAIN
0
-3
0
PHASE
VS = ±3V
VIN = 0.2VP-P to 4VP-P
3
GAIN
0
-3
0
PHASE
45
45
90
90
135
180
RL = 50Ω
PHASE (°)
NORMALIZED GAIN (dB)
VS = ±5V
2
13
FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY
VOLTAGE
1M
12
11
250
VCOM = (V+) - 1V
250
0
2
10
9
FIGURE 14. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE
FIGURE 13. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE
tRANS (ns)
+25°C
40
-40°C
2
+85°C
60
+25°C
100
+85°C
-40°C
0
100
+85°C
150
+25°C
100
100
0
250
VCOM = (V+) - 1V
V- = -5V
-40°C
150
135
180
PHASE (°)
300
VCOM = (V+) - 1V
V- = -5V
RL = 50Ω
10M
100M
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE
12
600M
1M
10M
100M
600M
FREQUENCY (Hz)
FIGURE 18. FREQUENCY RESPONSE
FN6213.3
May 6, 2009
ISL84582
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
-10
20
2
30
40
-50
50
-60
60
ISOLATION
-70
70
CROSSTALK
-80
80
-90
90
-100
100
V+ = 3.3V
V- = 0V
1
Q (pC)
-40
OFF-ISOLATION (dB)
CROSSTALK (dB)
3
10
V+ = 3V to 12V or
-20 VS = ±2V to ±5V
RL = 50Ω
-30
V+ = 12V
V- = 0V
0
V+ = 5V
V- = 0V
-1
VS = ±5V
-2
-3
ALL HOSTILE CROSSTALK
-110
1k
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 19. CROSSTALK AND OFF-ISOLATION
-4
-5
-2.5
0
2.5
5
7.5
10
12
VCOM (V)
FIGURE 20. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL84582: 193
PROCESS:
Si Gate CMOS
13
FN6213.3
May 6, 2009
ISL84582
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
B M
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
L
A
D
-C-
e
α
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
α
NOTES:
0.006
E1
e
A2
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
0.70
6
16
8o
0o
-
6.50
7
8o
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6213.3
May 6, 2009
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