DATASHEET

High-Speed USB 2.0 (480Mbps) DPST Switch with
Overvoltage Protection (OVP)
ISL54228
Features
The Intersil ISL54228 is a single supply, dual SPST
(Single Pole/Single Throw) switch that is configured as a
DPST. It can operate from a single 2.7V to 5.25V supply.
The part was designed for switching or isolating a USB
high-speed source or a USB high-speed and full-speed
source in portable battery powered products.
• High-Speed (480Mbps) and Full-Speed (12Mbps)
Signaling Capability per USB 2.0
The 3.5SPST switches were specifically designed to
pass USB full speed and USB high speed data signals.
They have high bandwidth and low capacitance to pass
USB high speed data signals with minimal distortion.
The device has two logic control pins (OE and LP) to
control the SPST switches.
The ISL54228 has OVP detection circuitry on the COM
pins to open the SPST switches when the voltage at
these pins exceeds 3.8V or goes negative by -0.45V. It
isolates fault voltages up to +5.25V or down to -5V from
getting passed to the other-side of the switch, thereby
protecting the USB down-stream transceiver.
The ISL54228 is available in 8 Ld 1.2mmx1.4mm
µTQFN and 8 Ld 2mmx2mm TDFN packages. It operates
over a temperature range of -40°C to +85°C.
• 1.8V Logic Compatible (2.7V to +3.6V Supply)
• Low Power State
• Power OFF Protection
• COM Pins Overvoltage Detection and Protection for
+5.25V and -5V Fault Voltages
• -3dB Frequency . . . . . . . . . . . . . . . . . . 790MHz
• Low ON Capacitance @ 240MHz . . . . . . . . . . 2pF
• Low ON-Resistance . . . . . . . . . . . . . . . . . . 3.5
• Single Supply Operation (VDD) . . . . 2.7V to 5.25V
• Available in µTQFN and TDFN Packages
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit and
Overvoltage Requirements Without Additional
External Components
Applications*(see page 15)
• MP3 and other Personal Media Players
• Cellular/Mobile Phones, PDA’s
• Digital Cameras and Camcorders
• USB Switching
Typical Application
USB 2.0 HS Eye Pattern with
Switches in the Signal Path
3.3V
USB CONNECTOR
VDD
LOGIC
CONTROL
VBUS
D-
LP
OE
D-
COM -
USB
OVP
DET
D+
GND
D+
COM +
ISL54228
µP
HIGH-SPEED
TRANSCEIVER
VOLTAGE SCALE (0.1V/DIV)
500Ω
GND
TIME SCALE (0.2ns/DIV)
July 29, 2010
FN7628.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54228
ESIGNS
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ISL54228
Pin Configurations
ISL54228
(8 LD 2x2 TDFN)
TOP VIEW
GND
COM +
7
6
8
COM -
ISL54228
(8 LD 1.2x1.4 µTQFN)
TOP VIEW
PD
LP 1
OVP
LOGIC
4MΩ
4MΩ
D+ 2
D-
8
VDD
7
OE
6
D-
5
COM-
5 D+
1
COM+ 3
LOGIC
OVP
GND 4
3
4
VDD
LP
OE
2
4MΩ
4MΩ
NOTE: Switches Shown for OE = Logic “0”.
Pin Descriptions
µTQFN
TDFN
PIN NAME
4
1
LP
Low Power Input
DESCRIPTION
5
2
D+
USB Data Port
6
3
COM+
USB Data Port
7
4
GND
Ground Connection
8
5
COM-
USB Data Port
1
6
D-
USB Data Port
2
7
OE
Switch Enable
3
8
VDD
-
PD
PD
Power Supply
Thermal Pad. Tie to Ground or Float
Truth Table
INPUT
OUTPUT
SIGNAL AT COM PINS
LP
OE
D-, D+
STATE
0V to 3.6V
0
0
OFF
Normal
0V to 3.6V
0
1
ON
Normal
0V to 3.6V
1
0
OFF
Low Power
0V to 3.6V
1
1
ON
Normal
Overvoltage Range
0
0
OFF
OVP
Overvoltage Range
0
1
OFF
OVP
Overvoltage Range
1
0
OFF
Neg OVP
Limited Positive OVP
No Persistence Checking
Low Power
Overvoltage Range
1
1
OFF
OVP
NOTE: Logic “0” when  0.5V, Logic “1” when  1.4V with a 2.7V to 3.6V Supply.
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July 29, 2010
ISL54228
TABLE 1. USB - OVP POSSIBLE SITUATIONS AND TRIP POINT VOLTAGE
TRIP POINT
CODEC SUPPLY
SWITCH SUPPLY (VDD)
COMS SHORTED TO
PROTECTED
MIN
MAX
2.7V to 3.3V
2.7V to 5.25V
VBUS
Yes
3.62V
3.95V
2.7V to 3.3V
2.7V to 5.25V
-5V
Yes
-0.6V
-0.29V
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
ISL54228IRUZ-T (Note 1, 3)
U6
-40 to +85
8 Ld 1.2mmx1.4mm µTQFN (Tape and Reel)
L8.1.4x1.2
ISL54228IRUZ-T7A (Note 1, 3)
U6
-40 to +85
8 Ld 1.2mmx1.4mm µTQFN (Tape and Reel)
L8.1.4x1.2
ISL54228IRTZ-T (Note 1, 2)
228
-40 to +85
8 Ld 2mmx2mm TDFN (Tape and Reel)
L8.2x2C
ISL54228IRTZ-T7A (Note 1, 2)
228
-40 to +85
8 Ld 2mmx2mm TDFN (Tape and Reel)
L8.2x2C
ISL54228IRUZEVAL1Z
PACKAGE
(Pb-Free)
PKG.
DWG. #
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials
and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54228. For more information on MSL please
see techbrief TB363.
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July 29, 2010
ISL54228
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
VDD to COMx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V
COMx to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.6V
Input Voltages
D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to 6.5V
COM+, COM- . . . . . . . . . . . . . . . . . . . . . . . - 5V to 6.5V
OE, LP . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Continuous Current (COM-/D-, COM+/D+) . . . . . . . ±40mA
Peak Current (COM-/D-, COM+/D+)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±100mA
ESD Rating:
Human Body Model (Tested per JESD22-A114-F). . . . >2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . >150V
Charged Device Model (Tested per JESD22-C101-D) . >2kV
Latch-up Tested per JEDEC; Class II Level A . . . . . at +85°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld µTQFN Package (Note 6, 8) . .
210
165
8 Ld TDFN Package (Notes 5, 7). . .
96
19
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range. . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Normal Operating Conditions
Temperature Range . . . . . .
VDD Supply Voltage Range .
Logic Control Input Voltage
Analog Signal Range
VDD = 2.7V to 5.25V . . .
. . . . . . . . . . . . -40°C to +85°C
. . . . . . . . . . . . . 2.7V to 5.25V
. . . . . . . . . . . . . . . 0V to 5.25V
. . . . . . . . . . . . . . . . 0V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VLP = GND,
VOEH = 1.4V, VOEL = 0.5V, (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
(High-Speed)
VDD = 2.7V, OE = 1.4V, IDx = 17mA,
VCom+ or VCOM- = 0V to 400mV
(see Figure 2, Note 14)
rON Matching Between
VDD = 2.7V, OE = 1.4V, IDx = 17mA,
Channels, rON (High-Speed) VCom+ or VCOM- = Voltage at max rON,
(Notes 13, 14)
25
-
3.5
5

Full
-
-
7

25
-
0.2
0.45

Full
-
-
0.55

25
-
0.26
1

Full
-
-
1.2

rON Flatness, RFLAT(ON)
(High-Speed)
VDD = 2.7V, OE = 1.4V, IDx = 17mA,
VCom+ or VCOM- = 0V to 400mV
(Notes 12, 14)
ON-Resistance, rON
VDD = 3.3V, OE = 1.4V, ICOMx = 17mA,
VCom+ or VCOM- = 3.3V
(see Figure 2, Note 14)
+25
-
6.8
17

Full
-
-
22

VDD = 5.25V, OE = 0V, VDx = 0.3V, 3.3V,
VCOMX = 3.3V, 0.3V
25
-20
1
20
nA
Full
-
30
-
nA
25
-9
-
9
µA
Full
-12
-
12
µA
25
-
-
11
µA
Power OFF Logic Current, IOE VDD = 0V, OE = 5.25V
25
-
-
22
µA
Power OFF D+/D- Current,
ID+, ID-
25
-
-
1
µA
OFF Leakage Current, IDx(OFF)
ON Leakage Current, IDx(ON) VDD = 5.25V, OE = 5.25V, VDx = 0.3V,
3.3V, VCOMX = 0.3V, 3.3V
VDD = 0V, VCOM+ = 5.25V, VCOM- = 5.25V,
OE = 0V
Power OFF Leakage Current,
ICOM+, ICOM-
VDD = 0V, OE = VDD, VD+ = VD- = 5.25V
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FN7628.0
July 29, 2010
ISL54228
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VLP = GND,
VOEH = 1.4V, VOEL = 0.5V, (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
OVERVOLTAGE PROTECTION DETECTION
Positive Fault-Protection Trip
Threshold, VPFP
VDD = 2.7V to 5.25V, OE = VDD
(see Table 1 on page 3)
25
3.62
3.8
3.95
V
Negative Fault-Protection Trip VDD = 2.7V to 5.25V, OE = VDD
Threshold, VNFP
(see Table 1 on page 3)
25
-0.6
-0.45
-0.29
V
Negative OVP Response: VDD = 2.7V,
SEL = 0V or VDD, OE = VDD, VDx = 0V to
-5V, RL = 15k
25
-
102
-
ns
Positive OVP Response: VDD = 2.7V,
SEL = 0V or VDD, OE = VDD, VDx = 0V to
5.25V, RL = 15k
25
-
2
-
µs
VDD = 2.7V, OE = VDD, VDx = 0V to 5.25V
or 0V to -5V, RL = 15k
25
-
45
-
µs
OFF Persistence Time
Fault Protection Response Time
ON Persistence Time
Fault Protection Recovery Time
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 3.3V, Vinput = 3V, RL = 50,
CL = 50pF (see Figure 1)
25
-
160
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, Vinput = 3V, RL = 50,
CL = 50pF (see Figure 1)
25
-
60
-
ns
Skew, (tSKEWOUT - tSKEWIN)
VDD = 3.3V, OE = 3.3V, RL = 45,
CL = 10pF,tR = tF = 500ps at 480Mbps,
(Duty Cycle = 50%) (see Figure 5)
25
-
50
-
ps
Rise/Fall Degradation
(Propagation Delay), tPD
VDD = 3.3V, OE = 3.3V, RL = 45,
CL = 10pF,see Figure 5)
25
-
250
-
ps
Crosstalk
VDD = 3.3V, RL = 50, f = 240MHz
(see Figure 4)
25
-
-39
-
dB
OFF-Isolation
VDD = 3.3V, OE = 0V, RL = 50, f = 240MHz
25
-
-23
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.2VDC offset, RL = 50
25
-
790
-
MHz
OFF Capacitance, COFF
f = 1MHz, VDD = 3.3V, LP = 0V, OE = 0V
(Figure 3)
25
-
2.5
-
pF
COM ON Capacitance, C(ON)
f = 1MHz, VDD = 3.3V, LP = 0V, OE = 3.3V
(Figure 3)
25
-
4
-
pF
COM ON Capacitance, C(ON)
f = 240MHz, VDD = 3.3V, LP = 0V, OE = 3.3V
25
-
2
-
pF
Full
2.7
5.25
V
25
-
45
56
µA
Full
-
-
59
µA
25
-
23
30
µA
Full
-
-
34
µA
25
-
5
6
µA
Full
-
-
10
µA
25
-
35
45
µA
Full
-
-
50
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
VDD = 5.25V, OE = 5.25V, LP = GND
Positive Supply Current, IDD
Positive Supply Current, IDD
VDD = 3.6V, OE = 3.6V, LP = GND
Positive Supply Current, IDD
(Low Power State)
VDD = 3.6V, OE = 0V, LP = VDD
Positive Supply Current, IDD
VDD = 4.3V, OE = 2.6V, LP = GND
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July 29, 2010
ISL54228
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VLP = GND,
VOEH = 1.4V, VOEL = 0.5V, (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
TEST CONDITIONS
Positive Supply Current, IDD
VDD = 3.6V, OE = 1.4V, LP = GND
25
-
25
32
µA
Full
-
-
38
µA
Input Voltage Low, VOEL, VLPL VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VOEH, VLPH VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, VOEL, VLPL VDD = 3.7V to 4.2V
Full
-
-
0.7
V
Input Voltage High, VOEH, VLPH VDD = 3.7V to 4.2
Full
1.7
-
-
V
Input Voltage Low, VOEL, VLPL VDD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High, VOEH, VLPH VDD = 4.3V to 5.25V
Full
2.0
-
-
V
Input Current, IOEL, ILPL
VDD = 5.25V, OE = 0V, LP = 0V
Full
-
-8.2
-
nA
Input Current, IOEH, ILPH
VDD = 5.25V, OE = 5.25V, LP = 5.25V,
4M Pull-down
Full
-
1.4
-
µA
DIGITAL INPUT CHARACTERISTICS
NOTES:
9. VLOGIC = Input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value.
14. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
VDD
LOGIC
INPUT
50%
C
0V
VINPUT
tOFF
SWITCH
VINPUT
INPUT
SWITCH
INPUT
Dx
COMx
VOUT
OE
VOUT
90%
SWITCH
OUTPUT
VDD
tr < 20ns
tf < 20ns
90%
VIN
GND
0V
RL
50
CL
50pF
tON
Logic input waveform is inverted for switches that have the
opposite logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(INPUT) R + r
L
ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
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July 29, 2010
ISL54228
Test Circuits and Waveforms (Continued)
VDD
C
rON = V1/17mA
COMx
VHSDX
OE
V1
17mA
VDD
Dx
GND
Repeat test for all switches.
FIGURE 2. rON TEST CIRCUIT
VDD
VDD
C
C
COMx
SIGNAL
GENERATOR
COM+
50
D+
OE
IMPEDANCE
ANALYZER
OE
0V OR
VDD
Dx
VIN
GND
COM-
D-
ANALYZER
NC
GND
RL
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. CAPACITANCE TEST CIRCUIT
7
FIGURE 4. CROSSTALK TEST CIRCUIT
FN7628.0
July 29, 2010
ISL54228
Test Circuits and Waveforms (Continued)
VDD
C
tri
90%
DIN+
DIN-
10%
50%
VDD
tskew_i
90%
OE
15.8
COM-
DIN+
50%
143
10%
DIN-
tfi
tro
15.8
OUT+
D-
45
CL
COM+
OUT-
D+
45
CL
143
90%
OUT+
OUT-
10%
50%
GND
tskew_o
50%
90%
10%
tf0
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5B. TEST CIRCUIT
FIGURE 5. SKEW TEST
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ISL54228
Application Block Diagram
3.3V
500Ω
VDD
µCONTROLLER
VBUS
USB CONNECTOR
LP
Logic
Control
OE
4MΩ
D-
COM -
D+
OVP
DET
COM +
4MΩ
D-
D+
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
GND
ISL54228
GND
Detailed Description
The ISL54228 device is a dual single pole/single throw
(SPST) analog switch configured as a DPST that
operates from a single DC power supply in the range of
2.7V to 5.25V.
It was designed for switching a USB high-speed source
or full-speed source in portable battery powered
products. It is offered in small µTQFN and TDFN
packages for use in MP3 players, cameras, PDAs,
cellphones, and other personal media players.
The part consists of two 3.5 high speed SPST
switches. These switches have high bandwidth and low
capacitance to pass USB high-speed (480Mbps)
differential data signals with minimal edge and phase
distortion. They can also swing from 0V to 3.6V to pass
USB full speed (12Mbps) differential data signals with
minimal distortion.
The device has a single logic control pin (OE) to open
and close the two SPST switches. The part has an LP
control pin to put the part in a low power state.
PORTABLE MEDIA DEVICE
applications that need to switch a high-speed or fullspeed transceiver source. A typical application block
diagram of this functionality is previously shown.
A detailed description of the SPST switches is provided
in the following section.
High-Speed (Dx) SPST Switches
The Dx switches are bi-directional switches that can
pass USB high-speed and USB full-speed signals when
VDD is in the range of 2.7V to 5.25V.
When powered with a 2.7V supply, these switches have
a nominal rON of 3.5 over the signal range of 0V to
400mV with a rON flatness of 0.26. The rON matching
between the switches over this signal range is only
0.2 ensuring minimal impact by the switches to USB
high speed signal transitions. As the signal level
increases, the rON switch resistance increases. At a
signal level of 3.3V, the switch resistance is nominally
9.8. See Figures 8, 9, 10, 11, 12, 13 in the “Typical
Performance Curves” beginning on page 12.
The part contains special overvoltage protection (OVP)
circuitry on the COM+ and COM- pins. This circuitry
acts to open the SPST switches when the part senses a
voltage on the COM pins that is >3.8V (typ) or
< -0.45V (typ). It isolates voltages up to 5.25V and
down to -5V from getting through to the other side of
the switches (D-, D+) to protect the USB down-stream
transceiver connected at the D+ and D- pins.
The Dx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals in the
range of 0V to 400mV. They have low capacitance and
high bandwidth to pass the USB high-speed signals
with minimum edge and phase distortion to meet USB
2.0 high speed signal quality specifications. See
Figure 14 in the “Typical Performance Curves” on
page 13 for USB High-speed Eye Pattern taken with
switch in the signal path.
The ISL54228 was designed for MP3 players, cameras,
cellphones, and other personal media player
The Dx switches can also pass USB full-speed signals
(12Mbps) in the range of 0V to 3.6V with minimal
9
FN7628.0
July 29, 2010
ISL54228
distortion and meet all the USB requirements for USB
2.0 full-speed signaling. See Figure 15 in the “Typical
Performance Curves” on page 14 for USB Full-speed
Eye Pattern taken with switch in the signal path.
The switches are active (turned ON) whenever the OE
voltage is logic “1” (High) and the LP voltage is logic
“X” (Don’t Care) and OFF when the OE voltage is logic
“0” (Low) and the LP voltage is logic “X” (Don’t Care).
When the OE voltage is logic “0” (Low) and the LP
voltage is logic “1” (High) the part goes into low power
mode.
situation and has been found to prevent latch-up or
destructive damage for many overvoltage transient
events.
Under normal operation, the low microamp IDD
current of the IC produces an insignificant voltage
drop across the series resistor resulting in no impact
to switch operation or performance.
VSUPPLY
PROTECTION
RESISTOR
100Ω to 1kΩ
OVERVOLTAGE PROTECTION (OVP)
However, in the event that a positive voltage >3.8V
(typ) to 5.25V, such as the USB 5V VBUS voltage, gets
shorted to one or both of the COM+ and COM- pins or
a negative voltage < -0.45V (typ) to -5V gets shorted
to one or both of the COM pins, the ISL54228 has OVP
circuitry to detect the overvoltage condition and open
the SPST switches to prevent damage to the USB
down-stream transceiver connected at the signal pins
(D-, D+).
The OVP and power-off protection circuitry allows the
COM pins (COM-, COM+) to be driven up to 5.25V
while the VDD supply voltage is in the range of 0V to
5.25V. In this condition, the part draws < 100µA of
ICOMx and IDD current and causes no stress to the IC.
In addition, the SPST switches are OFF and the fault
voltage is isolated from the other side of the switch.
External VDD Series Resistor to Limit IDD
Current During Negative OVP Condition
A 100Ω to 1kΩ resistor in series with the VDD pin (see
Figure 6) is required to limit the IDD current draw from
the system power supply rail during a negative OVP
fault event.
With a negative -5V fault voltage at both COM pins, the
graph in Figure 7 shows the IDD current draw for
different external resistor values for supply voltages of
5.25V, 3.6V, and 2.7V. Note: With a 500Ω resistor, the
current draw is limited to around 5mA. When the
negative fault voltage is removed, the IDD current will
return to it’s normal operation current of 25µA to 45µA.
The series resistor also provides improved ESD and
latch-up immunity. During an overvoltage transient
event (such as occurs during system level IEC 61000
ESD testing), substrate currents can be generated in
the IC that can trigger parasitic SCR structures to
turn ON, creating a low impedance path from the
VDD power supply to ground. This will result in a
significant amount of current flow in the IC, which
can potentially create a latch-up state or
permanently damage the IC. The external VDD
resistor limits the current during this over-stress
10
COM+
-5V
FAULT
VOLTAGE
COMOE
IDD
VDD
OVP
LOGIC
LP
GND
D+
D-
LOW
TO
INDICATE
OVP
ALM
INT
FIGURE 6. VDD SERIES RESISTOR TO LIMIT IDD
CURRENT DURING NEGATIVE OVP AND
FOR ENHANCED ESD AND LATCH-UP
IMMUNITY
25
20
IDD (mA)
The maximum normal operating signal range for the Dx
switches is from 0V to 3.6V. For normal operation, the
signal voltage should not be allowed to exceed these
voltage levels or go below ground by more than -0.3V.
C
VCOM+ = VCOM- = -5V
5.25V
15
10
5
0
100
3.6V
2.7V
200
300
400 500 600 700
RESISTOR (Ω)
800
900 1k
FIGURE 7. NEGATIVE OVP IDD CURRENT vs
RESISTOR VALUE vs VSUPPLY
ISL54228 Operation
The following will discuss using the ISL54228 shown
in the “Application Block Diagram” on page 9.
POWER
The power supply connected at the VDD pin provides
the DC bias voltage required by the ISL54228 part for
proper operation. The ISL54228 can be operated with
a VDD voltage in the range of 2.7V to 5.25V.
For lowest power consumption you should use the
lowest VDD supply.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out
any power supply noise from entering the part. The
capacitor should be located as close to the VDD pin
as possible.
FN7628.0
July 29, 2010
ISL54228
In a typical application, VDD will be in the range of
2.8V to 4.3V and will be connected to the battery or
LDO of the portable media device.
LOGIC CONTROL
The state of the ISL54228 device is determined by the
voltage at the OE pin, LP pin, and the signal voltage at
the COM pins. Refer to “Truth Table” on page 2.
The OE and LP pins are internally pulled low through a
4Mresistor to ground and can be tri-stated or left
floating.
The ISL54228 is designed to minimize IDD current
consumption when the logic control voltage is lower than
the VDD supply voltage. With VDD = 3.6V and the OE
logic pin is at 1.4V, the part typically draws only 25µA.
With VDD = 4.3V and the OE logic pin is at 2.6V, the part
typically draws only 35µA. Driving the logic pin to the
VDD supply rail minimizes power consumption.
The OE and LP pin can be driven with a voltage higher
than the VDD supply voltage. It can be driven up to
5.25V with a VDD supply in the range of 2.7V to 5.25V.
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS
VDD SUPPLY
RANGE
LOGIC = “0” (LOW)
LOGIC = “1”
(HIGH)
OE
LP
OE
LP
2.7V to 3.6V
0.5V
or
floating
0.5V
or
floating
1.4V
1.4V
3.7V to 4.2V
0.7V
or
floating
0.7V
or
floating
1.7V
1.7V
4.3V to 5.25V
0.8V
or
floating
0.8V
or
floating
2.0V
2.0V
11
Low Power Mode
If the OE pin = Logic “0”, and the LP pin = Logic “1” the
switches will turn OFF (high impedance) and the part
will be put in a low power mode. In this mode, the part
draws only 10µA (max) of current across the operating
temperature range.
Normal Operation Mode
With a signal level in the range of 0V to 3.6V and with
the LP pin = Logic “0” the switches will be ON when the
OE pin = Logic “1” and will be OFF (high impedance)
when the OE pin = Logic “0”.
USB 2.0 VBUS Short Requirements
The USB specification in section 7.1.1 states a USB
device must be able to withstand a VBUS short (4.4V to
5.25V) or a -1V short to the D+ or D- signal lines when
the device is either powered off or powered on for at
least 24 hours.
The ISL54228 part has special power-off protection and
OVP detection circuitry to meet these short circuit
requirements. This circuitry allows the ISL54228 to
provide protection to the USB down-stream transceiver
connected at its signal pins (D-, D+) to meet the USB
specification short circuit requirements.
The power-off protection and OVP circuitry allows the
COM pins (COM-, COM+) to be driven up to 5.25V or
down to -5V while the VDD supply voltage is in the range
of 0V to 5.25V. In these overvoltage conditions, the part
draws < 55µA of current into the COM pins and causes
no stress/damage to the IC. In addition, all switches are
OFF and the shorted VBUS voltage will be isolated from
getting through to the other side of the switch channels,
thereby protecting the USB transceiver.
FN7628.0
July 29, 2010
ISL54228
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified
16
3.4
ICOM = 17mA
12
3.2
10
3.0V
rON ()
rON ()
3.3
3.3V
3.1
3.0
0.1
0.2
VCOM (V)
3.3V
5.25V
2
0.3
0
0.4
FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0
0.6
1.2
16
+85°C
3.6
V+ = 2.7V
ICOM = 17mA
14
rON ()
+25°C
-40°C
2.5
10
8
+85°C
+25°C
6
4
2.0
-40°C
2
0.1
0.2
VCOM (V)
0.3
0
0.4
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.5
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
4.0
9
V+ = 3.3V
8 ICOM = 17mA
+85°C
7
3.5
6
+25°C
rON ()
rON ()
3.0
12
3.0
3.0
-40°C
5
+85°C
4
+25°C
3
2.5
V+ = 3.3V
ICOM = 17mA
2.0
0
2.4
18
3.5
1.5
0
1.8
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
V+ = 2.7V
ICOM = 17mA
4.0
rON ()
3.0V
4
5.25V
2.9
0
2.7V
8
6
3.6V
4.3V
4.5
ICOM = 17mA
14
2.7V
0.1
-40°C
2
0.2
VCOM (V)
0.3
0.4
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
12
1
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.6
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN7628.0
July 29, 2010
ISL54228
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 14. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
13
FN7628.0
July 29, 2010
ISL54228
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
1
-10
0
-20
-1
-30
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
FIGURE 15. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
-2
-3
-4
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
-40
-50
-60
-70
-80
-90
-100
1M
10M
100M
FREQUENCY (Hz)
FIGURE 16. FREQUENCY RESPONSE
14
1G
-110
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
100
500
FIGURE 17. OFF-ISOLATION
FN7628.0
July 29, 2010
ISL54228
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
Die Characteristics
-10
NORMALIZED GAIN (dB)
-20
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
SUBSTRATE AND TDFN THERMAL PAD
POTENTIAL (POWERED UP):
-30
GND
-40
-50
TRANSISTOR COUNT:
-60
1297
-70
PROCESS:
-80
Submicron CMOS
-90
-100
-110
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 18. CROSSTALK
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
7/29/10
FN7628.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL54228
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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15
FN7628.0
July 29, 2010
ISL54228
Package Outline Drawing
L8.2x2C
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD
Rev 0, 07/08
2.00
6
PIN #1 INDEX AREA
A
B
6
PIN 1
INDEX AREA
8
1
0.50
2.00
1.45±0.050
Exp.DAP
(4X)
0.15
0.10 M C A B
0.25
( 8x0.30 )
TOP VIEW
0.80±0.050
Exp.DAP
BOTTOM VIEW
( 8x0.20 )
Package Outline
( 8x0.30 )
SEE DETAIL "X"
( 6x0.50 )
1.45
2.00
0.10 C
0 . 75 ( 0 . 80 max)
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 8x0.25 )
0.80
2.00
TYPICAL RECOMMENDED LAND PATTERN
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN7628.0
July 29, 2010
ISL54228
Package Outline Drawing
L8.1.4x1.2
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/09
0.80
REF
4X 0.40 BSC
1.40
A
PIN 1
INDEX AREA
PIN 1
B
1.20
6
INDEX AREA
8
0.30
C0.10
5
1
0.40
0.60
7X 0.30
0.10
2X
±0.05
2
4
0.10 M C A B
0.40 BSC
TOP VIEW
0.05 M C
4 8 X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.80
REF
MAX. 0.50
4X 0.40
PKG OUTLINE
0.10
C
C
SEATING PLANE
0.08
8 X 0.20
C
SIDE VIEW
0.60
0.60
7X 0.50
C
0 . 2 REF
0.70
0.60
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
17
FN7628.0
July 29, 2010
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