an1447

ISL54230EVAL2Z, ISL54230EVAL3Z Evaluation
Board User’s Manual
®
Application Note
Description
March 26, 2009
AN1447.0
Picture of Evaluation Board (Top View)
The ISL54230EVAL2Z, ISL54230EVAL3Z evaluation board
is designed to provide a quick and easy method for
evaluating the ISL54230 IC.
The ISL54230 IC is a single supply Quad Double-Pole
Double Throw (DPDT) analog switch featuring two USB 2.0
Full-Speed/High-Speed compliant switches and two general
purpose analog switches. The ISL54230 is designed for
applications that require switching, muxing, and/or routing of
analog and digital signals. The ISL54230EVAL2Z,
ISL54230EVAL3Z evaluation board is developed to evaluate
the ISL54230 IC, integrating many features for ease of use
in examining the performance of the device under various
operating conditions. To help understand the operation of the
evaluation board, it is recommended to study the evaluation
board schematics found on page 4 of this document and the
data sheet for the ISL54230 IC.
The ISL54230 IC is a Quad DPDT analog switch that is
operational with a +2.0 to +5.5V supply voltage. The
ISL54230 integrates four logic control pins for independent
control of each DPDT switch and also includes two output
enable pins for disabling certain switches, giving the
ISL54230 IC multiple configurations. The evaluation board
contains standard BNC connectors, USB Type A and USB
Type B connectors to allow the user to easily interface with
the IC to evaluate its functions, features, and performance.
This application note will guide the user through the process
of configuring and using the evaluation board to evaluate the
ISL54230 device.
Key Features
• Quad DPDT Analog Switch for Signal
Switching/Muxing/Routing
• Standard BNC Connectors and USB Type A/B connectors
• Convenient Test Points and Connections for Test
Equipment
• Manual or External Logic Input Control
FIGURE 1. ISL540230EVAL2Z, ISL540230EVAL3Z
EVALUATION BOARD
Board Architecture/Layout
Basic Layout of Evaluation Board
A picture of the evaluation board is located in Figure 1. For
the ISL54230EVAL2Z the ISL54230 IC sits inside the socket
located at U1 in the center of the evaluation board. The pin 1
indicator dot of the IC must be aligned with the pin 1
indicator dot inside the socket housing for proper operation.
For the ISL54230EVAL3Z, the ISL54230 IC is soldered onto
the evaluation board located at the center labeled U1. The
evaluation board integrates the necessary connections and
components to interface with the ISL54230 for ease of
operation.
Note: The ISL54230EVAL2Z and ISL54230EVAL3Z are
equivalent evaluation boards except that the
ISL54230EVAL2Z uses a socket, while the
ISL54230EVAL3Z has the part soldered onto the board to
evaluate the IC. In addition, the ISL54230EVAL2Z has
toggle switch S3 mislabeled. In the UP position it should be
labeled as “TOGGLE” and in the DOWN position it should be
labeled as “REMOTE”.
Power Supply
The ISL54230 IC requires a supply voltage in the range of
+2.0V to +5.5V for proper operation. Banana jacks for VCC
(J1) and GND (J2) are located at the top of the board. The
evaluation board contains a 4.7µF bulk capacitor, 0.1µF
decoupling capacitor and a 0.01µF high frequency local
decoupling capacitor at the supply lines.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1447
Logic Control
The evaluation board contains two types of logic control to
the digital logic inputs of the ISL54230 IC available to the
user. The logic pins can be controlled either through manual
(TOGGLE) or external (REMOTE) operation. The logic
control pins are manually toggled by the SPDT switches
mounted on the evaluation board (S1-S7). When the switch
is in the up position (H) the associated logic pin is pulled to
VDD for logic HIGH. When the switch is in the down position
(L) the associated logic pin is pulled to GND for logic LOW.
For manual operation, the jumpers JP1-JP2 need to be in
the 1-2 position.
Note: For manual control, leave the toggle switch in the UP
position (REMOTE for ISL54230EVAL2Z and TOGGLE for
ISL54230EVAL3Z).
For external control via a function generator or switched
source, set the jumpers JP1-JP2 in the 2-3 position and
place the toggle switch in the DOWN position (TOGGLE for
ISL54230EVAL2Z and REMOTE for ISL54230EVAL3Z).
This by-passes the S1-S2 and S4-S7 SPDT toggle switches
and routes the logic control to the header pin connectors
J9-J10 located on the right side of the board. This allows for
interfacing a microcontroller or function generator via a
ribbon cable connector for remote control.
evaluation board requires a +2.0V to +5.5V DC power
supply for proper operation. The power supply should be
capable of delivering 100µA of current.
Logic Input Voltage
The state of the ISL54230 device is determined by the Truth
Table as defined in the ISL54230 data sheet. When in
manual operation mode, the logic being toggled by the
SPDT switches (S1-S2 and S4-S7) will always drive the
voltage of the logic pin to VDD for a HIGH and GND for a
LOW. In external control mode, the voltages being driven by
an external source must meet appropriate VIH and VIL levels
as defined in the data sheet.
The control pins are 1.8V logic compatible up to a +3.3V
supply, which allows for control via a standard µcontroller.
Logic “0” (LOW) when ≤ 0.5V
Logic “1” (HIGH) when ≥1.4V
When operating above +3.3V supply, refer to the data sheet
for appropriate logic levels to drive the logic pins. It is always
recommended to drive the logic pins to the positive supply
rail (VDD) and GND to minimize power consumption.
Logic States
INPUT SELECT (INX) PINS
Note: The logic control pins of the ISL54230 have 1MΩ logic
pull down resistors to ground to bias the logic pins to ground
when the pins are externally left floating.
If the INx Pins are logic “HIGH”, then the NOx switches are
turned ON and the NCx switches are turned OFF. If the INx
Pins are logic “LOW”, then the NCx switches are turned ON
and the NCx switches are turned OFF.
Switch Terminals
OUTPUT ENABLE (OEX) PINS
The evaluation board contains components to interface with
all terminals of the Quad DPDT switch. The general purpose
analog switches (COM1x and COM4x) are interfaced with
BNC connectors. The USB 2.0 compatible switches (COM2x
and COM3x) are interfaced with USB Type A/B connectors.
The Output Enable pins allow disabling sections of the Quad
DPDT switch. Under typical operation, the OE pin should be
biased logic “HIGH”. This enables all four of the DPDT
switches to be active. Refer to the OE Control Truth Table in
the data sheet for a list of the possible combinations of
switch disable.
NOTE: All switch terminals can be interfaced to the header
pin connectors J9 to J11. Connector J9 interfaces with
switches 1 and 2. Connector J10 interfaces with switches 3
and 4. Connector J11 interfaces with the logic control pins
OEX and INX. For connecting signals from switch 2 and
switch 3 (the signals that are connected to the USB
connectors) please see the evaluation board schematic on
page 4 for populating the necessary resistor to make the
connection.
NOTE: All switch terminals that are interfaced with the
standard BNC connectors contain a place holder that can
have a surface mount resistor or capacitor placed there. The
place holder is connected to the switch terminal on one side
and ground on the other side for simulating a resistive or
capacitive load. Refer to the evaluation board schematic on
page 4 for these place holders.
Power Supply
The DC power supply connected at banana jacks J1 (VDD)
and J2 (GND) provides power to the evaluation board. The
2
USB Connections
USB Type B connectors J3 and J6 connect to the USB host
which contains the VBUS power line. USB Type A
connectors J4-J5 and J7-J8 connect to a USB device. The
VBUS power must be routed to the USB device for proper
operation. To prevent both USB devices from receiving
VBUS power simultaneously, which may cause connectivity
errors, jumpers JP3 and JP4 route power to the USB
connectors. When JP3 is in the 1-2 position, VBUS is routed
to J5 and when it is in the 2-3 position, VBUS is routed to J4.
When JP4 is in the 1-2 position, VBUS is routed to J7 and
when it is in the 2-3 position, VBUS is routed to J8.
Note: It is recommended to have the place holders R23,
R24, R25-R28, R33, R34, and R37-R40 on the evaluation
board unpopulated when sending USB signals through the
switches. Failure to do so may result in poor USB signal
performance.
AN1447.0
March 26, 2009
Application Note 1447
Applications
The ISL54230 is designed to be a Quad DPDT switch for
switching, routing, or multiplexing of analog and digital
signals. Such applications include cell phones and PDAs
and other personal media devices that may utilize
USB2.0/UART/Audio/Power signals.
FIGURE 2. ISL54230EVAL3Z TOP VIEW
FIGURE 3. ISL54230EVAL3Z BOTTOM VIEW
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
AN1447.0
March 26, 2009
ISL54230EVAL2Z, ISL54230EVAL3Z Evaluation Board Schematic
J1
J2
J9-23
VDD
J9-17
0
0
MOUNT
3
1
S2
S1
2
COM3A
3
2
OE2
2
TP23
J6
COM2A
R35
1
R22
1
3
USB
COM2B
R36
R21
3
897-43-004-90-000 4
0.1UF
COM3B
COM2
1
2
DNP
R33
DNP
0
R34
DNP
R26
DNP
R25
4
OE1
56
J3
USB
4.7UF
3
2
C2
GND
56
897-43-004-90-000
1
4
TP1
4
MOUNT
23
V+
C1
MOUNT
1
J10-23
MOUNT
COM3
TP22
R1
TP2
J10-17
0
0
J24
2
2
1
J11-11
1
2
J11-9
JP2
JP1
3
1
2
J21
1
34
34
3
4
J9-9
J10-9
1
1M
0
TP3
DNP
J10-1
J9-1
R51
0
TP11
DNP
J10-3
J9-3
R52
24
TP13
DNP
J10-7
R16
1
2
J13
NC4B
0
7
18
8
17
J9-7
R54
0
33
TP5
J10-11
4
3
9
10
11
12
13
14
15
16
R55
2
J10-21
S4
0
R38
1M
R30
S5
MOUNT
NC2
5
MOUNT
1
3
1
1
2
0
IN2
3
3
4
1
UTQFN16
4
2
MOUNT
NO3
U2
2
3
11
10
9
NO2A
12
TP9
11
10
9
11
13
15
17
19
21
23
5
6
7
8
J11-3
J11
IN1
3
20
19 20
22
21 22
AN1447.0
March 26, 2009
23 24
2
1
S7
24
LEFT PLANE
4
2
6
MOUNT
NO2
J10
12
11 12
14
13 14
16
15 16
18
17 18
3
0
J26
1
34
S6
5
6
7
8
J9 -3
J9 -5
J9 -7
J9 -9
J9 -11
J9 -13
J9 -15
J9 -17
J9 -19
J9 -21
J9 -23
1
2
1 2
34
3 4
56
5 6
78
7 8
9
10
9 10
2
0
NO2B
J9
J9 -1
R44
R42
A
2
34
12
1M
J11-5
R20
R29
A
1
2
TYPE
16
15
14
13
MOUNT
J5
6
J8
USB
2
USB TYPE
1
234
NO3B
J9-15
J9-21
TP8
4
J25
1
34
R18
0
J23
DNP
0
16
15
14
13
DNP
R28
DNP
2
1
1
3
DNP
MOUNT
R24
IN3
1
6
2
0
3
5
4
R43
R41
NC2B
J11-7
NO3A
3
MOUNT
A
J10-15
3
NC2A
2
34
2
DNP
R39
R37
1M
TP7
3
1
NC3
JP4
1
IN4
1
0
NC3B
DNP
R40
6
2
R32
R19
3
0
J22
1
5
J7
4
4
R31
A
1
V+
R11
1M
MOUNT
TYPE
0.01UF
C3
DNP
R27
DNP
2
R23
1
NC3A
3
4
J9-13
USB TYPE
1
234
J4
J9-19
TP6
1
USB
DNP
V+
J10-19
5
2
NO1B
5
TP21
0
J10-13
3
J20
R50
DNP
JP3
1
2
0
R2
TP15
1
NC1B
5
J9-11
0
R10
J19
DNP
EP
R17
1
2
5
1
2
R49
TP20
DNP
J14
5
DNP
TP14
NO4B
J18 NO1A
1
2
R48
TP19
19
0
R9
4
3
5
20
QFN32
6
3
4
5
0
R8
4
3
5
R53
21
3
4
J12
DNP
J9-5
22
U1
4
3
4
3
NO4A
TP18
23
2
J10-5
R15
1
2
5
R47
J11-1
J11-3
J11-5
J11-7
J11-9
J11-11
1
2
1 2
34
3 4
56
5 6
78
7 8
9
10
9 10
11 11 12 12
CONN12
LOGIC INPUT
J11-1
J10-1
J10-3
J10-5
J10-7
J10-9
J10-11
J10-13
J10-15
J10-17
J10-19
J10-21
J10-23
1
2
1 2
34
3 4
56
5 6
78
7 8
10
9
9 10
11
12
11 12
13 13 14 14
15
17
19
21
23
16
15 16
18
17 18
20
19 20
22
21 22
23 24
24
RIGHT PLANE
TOGGLE
3
2
1
V+
Application Note 1447
1
DNP
J17 COM1A
1
2
0
TP12
3
4
0
R7
2
5
5
DNP
R14
1
2
J29
4
3
COM4A
R46
TP17
32
31
30
29
28
27
26
25
4
3
R6
3
4
0
2
J16 NC1A
1
2
R13
1
5
TP16
TP10
DNP
NC4A J28
5
J15
2
R45
3
4
R4
1M
TP4
0
R5
4
3
R3
1
2
COM1B
R56
R12
COM4B J27
5
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