DATASHEET

ISL14010, ISL14017
®
Data Sheet
April 16, 2007
Low Jitter Clock Generators for Set-Top
Box
The ISL14010 series of devices are general purpose
integrated Clock Synthesizers and Generators suited for
consumer applications such as Set-top Box, and various
other consumer applications.
The selectable reference input accepts 30MHz signal either
from crystal or an external source. It is specified to operate
with a nominal 3.3V supply and is offered in 16 Ld QFN
package.
Contact Factory for other output frequency options.
• LVTTL Outputs
• Selectable Crystal or Ref. Clock for Inputs
• Period Jitter ~50ps RMS
• Single Supply; 3.3V nominal
• Extended Temperature Range: -40ºC to +85ºC
• Available in small foot print package
- 16 Ld QFN 3mmx3mm
• Pb-Free plus anneal available (RoHS Compliant)
ISL14017IRZ*
17IZ
-40 to +85
16 LD QFN
L16.3x3
Pinout
ISL14010, ISL14017
(16 LD QFN)
TOP VIEW
*Add "-T" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Selection Table
PART
INPUT
NUMBER OF
OUTPUT
OPTIONS FREQUENCY OUTPUTS FREQUENCY PACKAGE
ISL14010
30MHz
4 LVTTL
25, 30, 48, 54 16 LD QFN
ISL14017
30MHz
4 LVTTL
25, 30, 40, 50 16 LD QFN
1
CLK4
L16.3x3
16
15
14
13
VCC 1
12 NC
X1 2
11 CLK3
X2 3
10 CLK2
GND 4
9
5
6
7
8
CLK1
16 LD QFN
VCC
-40 to +85
GND
10IZ
NC
ISL14010IRZ*
• Set-Top Boxes
NC
PACKAGE
PKG.
DWG. #
VCC
TEMP.
RANGE (°C)
GND
PART
MARKING
Features
Applications
Ordering Information
PART
NUMBER
FN6407.1
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL14010, ISL14017
Functional Block Diagram
CLK1
OSC.
M1
PHASE FREQ DET.
VCO1
CLK2
30MHz
CRYSTAL
N1
CLK3
M2
PHASE FREQ DET.
VCO2
CLK4
N2
Pin Description
16 LD QFN
SYMBOLS
1,14,16
VCC
2
X1
The X1 pin is the terminal 1 of an external 30MHz crystal. This pin is grounded for external CK input.
3
X2
The X2 pin is the terminal 2 of external 30MHz crystal, or external clock input.
4, 5, 7
GND
Ground
8
CLK1
CLK1 Output: 25MHz
10
CLK2
CLK2 Output: 30MHz
11
CLK3
CLK3 Output: 48MHz (40MHz for ISL14017)
13
CLK4
CLK4 Output: 54MHz (50MHz for ISL14017)
6, 9, 12, 15
NC
2
PIN DESCRIPTION
Supply Voltage
No Connect
FN6407.1
April 16, 2007
ISL14010, ISL14017
Absolute Maximum Ratings
Thermal Information
Voltage on VCC, CLK pins (respect to Gnd) . . . . . . . . -0.3V to 4.0V
Voltage on X1, X2 pins (respect to Gnd) . . . . . . . . . . . -0.3V to 2.5V
ESD Rating
MIL STD-883, Method 3014 . . . . . . . . . . . . . . . . . . . . . . . . .>±5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
θJC (°C/W)
16 Ld QFN Package. . . . . . . . . . . . . . .
58
11
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65ºC to +150ºC
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
DC Electrical Specifications
SYMBOL
VCC = 3.3V ±10%, TA = -40ºC to +85ºC, Typical values are at TA = +25ºC and VCC = 3.3V,
Unless otherwise noted
SYMBOL
CONDITIONS
Supply Voltage
VCC
Supply Voltage
Supply Current
ICC
Supply Current CL = 5pF on all outputs
MIN
TYP
MAX
UNIT
3.0
3.3
3.6
V
11
15
mA
2.4
V
0.5
V
CLOCK INPUT X2 (X1 GROUNDED) FOR EXTERNAL CLOCK MODE
Input High Level
VIH
Input Level Low
VIL
Input Current
1.5
IIL, IIH
VX2 to Ground
VOH
IOH = -100µA
0.5
mA
CLOCK OUTPUTS (CLK)
Output High Level
Output Low Level
VOL
Output Short Circuit Current
IOSC
AC Electrical Specifications
SYMBOL
VCC - 0.2
V
IOH = -4mA
2.4
V
IOH = -6mA
2.1
V
IOL = 100µA
0.2
V
IOL = 4mA
0.4
V
IOL = 6mA
0.75
V
CLK = VCC or Gnd
13
30
mA
MIN
TYP
MAX
UNIT
CL = 5pF on all outputs
SYMBOL
Crystal Frequency
6
CONDITIONS
fIN
30
MHz
CLOCK OUTPUTS
Rise Time
tR
20% to 80% VCC
1.8
ns
Fall Time
tF
80% to 20% VCC
1.8
ns
Duty Cycle
40
60
%
Period Jitter
JP
RMS
50
ps
Power Up Time
tPO
VCC >2.7V
2
ms
3
FN6407.1
April 16, 2007
ISL14010, ISL14017
Typical Performance Curves (Period Jitter)
70
PERIOD JITTER SIGMA (ps)
65
60
VSUPPLY = 3.3V
TEMPERATURE +23ºC
CK1
55
CK2
50
45
CK4
40
CK3
35
30
25
20
0
2
4
6
8
10
12
14
LOAD CAPACITANCE (pF)
FIGURE 1. STANDARD DEVIATION vs LOAD CAPACITANCE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
4
FN6407.1
April 16, 2007
ISL14010, ISL14017
Package Outline Drawing
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 4/07
4X 1.5
3.00
12X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
13
1
3.00
12
1 .50 ± 0 . 15
9
4
0.15
(4X)
5
8
0.10 M C A B
+ 0.07
4 16X 0.23 - 0.05
TOP VIEW
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0.1
BASE PLANE
( 2. 80 TYP )
(
SEATING PLANE
0.08 C
1. 50 )
SIDE VIEW
( 12X 0 . 5 )
( 16X 0 . 23 )
C
( 16X 0 . 60)
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
5
FN6407.1
April 16, 2007
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