ESIGNS NEW D R O F PART ED E ME N T MMEND C O A C L E P R D RE N OT ME N D E 0 R E C OM ISL4384 Data Sheet August 2004 ISL43841 FN6055.1 Low-Voltage, Single and Dual Supply, Dual 4 to 1 Multiplexer Analog Switch with Latch Features The Intersil ISL43841 device is a precision, bidirectional, analog switches configured as a a dual 4 channel multiplexer/ demultiplexer designed to operate from a single +2V to +12V supply or from a 2V to 6V supply. The device has a latch bar pin to lock in the last switch address. • ON Resistance (RON) Max, VS = 4.5V. . . . . . . . . . . 50 ON resistance of 39 with a 5V supply and 125 with a +3.3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25oC or 2.5nA at +85oC. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single 3.3V or +5V supply or dual 5V supplies. The ISL43841 is a dual 4 to 1 multiplexer device. Table 1 summarizes the performance of this part. TABLE 1. FEATURES AT A GLANCE CONFIGURATION • Fully Specified at 3.3V, 5V, 5V, and 12V Supplies for 10% Tolerances • ON Resistance (RON) Max, VS = +3V . . . . . . . . . . . 155 • RON Matching Between Channels, VS = 5V . . . . . . . . <2 • Low Charge Injection, VS = 5V . . . . . . . . . . . . . 1pC (Max) • Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V • Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . 2V to 6V • Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns • Guaranteed Max Off-leakage . . . . . . . . . . . . . . . . . . . . 2.5nA • Guaranteed Break-Before-Make • TTL, CMOS Compatible • Pb-free available DUAL 4:1 MUX 5V RON 39 Applications 5V tON/tOFF 32ns/18ns 12V RON 32 12V tON/tOFF 23ns/15ns 5V RON 65 • Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems 5V tON/tOFF 38ns/19ns 3.3V RON 125 3.3V tON/tOFF 70ns/32ns Package 20 Ld 4x4 QFN • Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph Related Literature • Audio and Video Signal Routing • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits • Application Note AN557 “Recommended Test Procedures for Analog Switches” • Application Note AN520 “CMOS Analog Multiplexers and Switches; Specifications and Application Considerations.” • Application Note AN1034 “Analog Switch and Multiplexer Applications” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved ISL43841 Pinout NO1B NO0B N.C. +V NO1A ISL43841 (QFN) TOP VIEW 20 19 18 17 16 COMB 1 15 NO2A NO3B 2 14 COMA NO2B 3 13 NO0A LATCH A 4 12 NO3A LATCH B 5 7 8 9 10 GND ADD2B ADD1B ADD2A Ordering Information ISL43841 LATCH ADD2 ADD1 SWITCH ON 0 X X Last Switch Selected 1 0 0 NO0 1 0 1 1 1 1 1 PACKAGE PKG. DWG. # 20 Ld QFN L20.4x4 ISL43841IRZ (43841IR) (See Note) -40 to 85 20 Ld QFN (Pb-free) L20.4x4 NO1 0 NO2 *Add “-T” suffix to part number for tape and reel packaging. 1 NO3 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. FUNCTION V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. COM TEMP. RANGE (oC) -40 to 85 Pin Descriptions PIN PART NO. (BRAND) ISL43841IR (43841IR) NOTE: Applies to either A or B switch. Logic “0” 0.8V. Logic “1” 2.4V, with V+ between 2.7V and 10V. X = Don’t Care. LATCH 11 ADD1A 6 Truth Table (Note) GND LOGIC -V LOGIC Ground Connection Digital Control Input. Connect to +V for Normal Operation. Connect to GND to latch the last switch state. Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin ADD Address Input Pin N.C. No Internal Connection 2 ISL43841 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V Input Voltages LATCH, NO, ADD (Note 1) . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical, Note 2) JA (oC/W) 20 Ld 4x4 QFN Package . . . . . . . . . . . . . . . . . . . . . 45 Maximum Junction Temperature (Plastic Package). . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Temperature Range ISL43841IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on NO, COM, ADD, or LATCH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications: 5V Supply Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEMP (oC) (NOTE 4) MIN TYP Full V- - V+ V 25 - 44 50 Full - - 80 25 - 1.3 4 Full - - 6 25 - 7.5 9 Full - - 12 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VLATCHH, VADDH Full 2.4 - - V Input Voltage Low, VLATCHL, VADDL Full - - 0.8 V VS = 5.5V, VLATCHH, VADD = 0V or V+ Full -0.5 0.03 0.5 A VS = 4.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) 25 - 43 60 ns Full - - 70 ns Full 2 7 - ns PARAMETER TEST CONDITIONS (NOTE 4) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG VS = 4.5V, ICOM = 2mA, VNO = 3V, (See Figure 6) ON Resistance, RON RON Matching Between Channels, RON VS = 4.5V, ICOM = 2mA, VNO = 3V, (Note 5) RON Flatness, RFLAT(ON) VS = 4.5V, ICOM = 2mA, VNO = 3V, 0V, (Note 6) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = 5.5V, VCOM = 4.5V, VNO = +4.5V, (Note 7) COM OFF Leakage Current, ICOM(OFF) VS = 5.5V, VCOM = 4.5V, VNO = +4.5V, (Note 7) COM ON Leakage Current, ICOM(ON) VS = 5.5V, VCOM = VNO = 4.5V, (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS VS = 5.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) Break-Before-Make Time, tBBM 3 ISL43841 Electrical Specifications: 5V Supply PARAMETER Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS Latch Setup Time, tS (See Figure 4) Latch Hold Time, tH (See Figure 4) Latch Pulse Width, tWPW (See Figure 4) TEMP (oC) (NOTE 4) MIN TYP 25 25 - - ns Full 35 - - ns 25 0 - - ns Full 0 - - ns 25 15 - - ns Full 25 - - ns (NOTE 4) MAX UNITS Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - 0.3 1 pC NO/NC OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V, (See Figure 8) 25 - 3 - pF COM OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V, (See Figure 8) 25 - 12 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) 25 - 18 - pF OFF Isolation RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 - 92 - dB 25 - 110 - dB 25 - -105 - dB Full 2 - 6 V 25 -1 0.1 1 A Full -1 - 1 A 25 -1 0.1 1 A Full -1 - 1 A Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) POWER SUPPLY CHARACTERISTICS Power Supply Range VS = 5.5V, VLATCHH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- NOTES: 3. VIN = logic voltage to configure the device in a given state. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. RON = RON (MAX) - RON (MIN). 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 8. Between any two switches. Electrical Specifications + 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP Full 0 - V+ V 25 - 37 45 Full - 55 25 - 1.2 2 Full - - 2 25 - 5 7 Full - - 7 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA (NOTE 4) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 10.8V, ICOM = 1.0mA, VNO = 9V, (See Figure 6) ON Resistance, RON RON Matching Between Channels, RON V+ = 10.8V, ICOM = 1.0mA, VNO = 9V, (Note 5) RON Flatness, RFLAT(ON) V+ = 10.8V, ICOM = 1.0mA, VNO = 3V, 6V, 9V, (Note 6) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) 4 V+ = 13.2V, VCOM = 1V, 12V, VNO = 12V, 1V, (Note 7) ISL43841 Electrical Specifications + 12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP COM OFF Leakage Current, ICOM(OFF) V+ = 13.2V, VCOM = 12V, 1V, VNO = 1V, 12V, (Note 7) 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA COM ON Leakage Current, ICOM(ON) V = 13.2V, VCOM = 1V, 12V, VNO = 1V, 12V, or floating, (Note 7) 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VLATCHH, VADDH Full 3.7 3.3 - V Input Voltage Low, VLATCHL, VADDL Full - 2.7 0.8 V V+ = 13.2V, VLATCHH, VADD = 0V or V+ Full -0.5 0.03 0.5 A V+ = 10.8V, VNO = 10V, RL = 300, CL = 35pF, VIN = 0 to 4, (See Figure 1) 25 - 27 50 ns Full - 55 ns PARAMETER (NOTE 4) MAX UNITS DIGITAL INPUT CHARACTERISTICS Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS Break-Before-Make Time Delay, tD V+ = 13.2V, RL = 300, CL = 35pF, VNO = 10V, VIN = 0 to 4, (See Figure 3) Full 2 5 - ns Latch Setup Time, tS (See Figure 4) 25 25 - - ns Full 35 - - ns 25 0 - - ns Full 0 - - ns 25 15 - - ns Full 25 - - ns Latch Hold Time, tH (See Figure 4) Latch Pulse Width, tWPW (See Figure 4) Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - 2.7 5 pC OFF Isolation RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 - 92 - dB 25 - 110 - dB All Hostile Crosstalk, (Note 8) 25 - -105 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V, (See Figure 8) 25 - 3 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) 25 - 12 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) 25 - 18 - pF Full 2 - 12 V Full -1 - 1 A Full -1 - 1 A Crosstalk, (Note 8) POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 13.2V, VLATCHH, VADD = 0V or V+, all channels On or Off Positive Supply Current, I- 5 ISL43841 Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEMP (oC) MIN (NOTE 4) TYP Full 0 - V+ V 25 - 81 90 Full - - 120 25 - 2.2 4 Full - - 6 25 - 11.5 17 Full - - 24 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VLATCHH, VADDH Full 2.4 - - V Input Voltage Low, VLATCHL, VADDL Full - - 0.8 V V+ = 5.5V, VLATCHH, VADD = 0V or V+ Full -0.5 0.03 0.5 A V+ = 4.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) 25 - 51 70 ns Full - - 85 ns PARAMETER TEST CONDITIONS MAX (NOTE 4) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 4.5V, ICOM = 1.0mA, VNO = 3.5V, (See Figure 6) ON Resistance, RON RON Matching Between Channels, RON V+ = 4.5V, ICOM = 1.0mA, VNO = 3V, (Note 5) RON Flatness, RFLAT(ON) V+ = 4.5V, ICOM = 1.0mA, VNO = 1V, 2V, 3V, (Note 6) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO = 4.5V, 1V, (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO = 4.5V, 1V, (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = VNO = 4.5V, (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 5.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) Full 2 9 - ns Latch Setup Time, tS (See Figure 4) 25 25 - - ns Full 35 - - ns 25 0 - - ns Full 0 - - ns 25 15 - - ns Full 25 - - ns (See Figure 4) Latch Hold Time, tH (See Figure 4) Latch Pulse Width, tWPW Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0(See Figure 2) 25 - 0.6 1.5 pC OFF Isolation RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 - 92 - dB 25 - 110 - dB 25 - -105 - dB Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) 6 ISL43841 Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP Full 2 - 12 V 25 -1 -0.1 1 A Full -1 - 1 A 25 -1 -0.1 1 A Full -1 - 1 A MAX (NOTE 4) UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 5.5V, V- = 0V, VLATCHH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Positive Supply Current, I- Electrical Specifications: 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP Full 0 - V+ V 25 - 135 155 MAX (NOTE 4) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3.0V, ICOM = 1.0mA, VNO = 1.5V, (See Figure 6) RON Matching Between Channels, RON V+ = 3.0V, ICOM = 1.0mA, VNO = 1.5V, (Note 5) RON Flatness, RFLAT(ON) V+ = 3.0V, ICOM = 1.0mA, VNO = 0.5V, 1V, 2V, (Note 6) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 0V, 4.5V, VNO = 3V, 1V, (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 0V, 4.5V, VNO = 3V, 1V, (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = VNO = 3V, (Note 7) Full - - 200 25 - 3.4 8 Full - - 10 25 - 34 40 Full - - 50 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VLATCHH, VADDH Full 2.4 - - V Input Voltage Low, VLATCHL, VADDL Full - - 0.8 V V+ = 3.6V, VLATCHH, VADD = 0V or V+ Full -0.5 0.03 0.5 A V+ = 3.0V, VNO = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) 25 - 96 120 ns Full - - 145 ns DIGITAL INPUT CHARACTERISTICS Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 3.6V, VNO = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) Full 3 13 - ns Latch Setup Time, tS (See Figure 4) 25 50 - - ns Full 60 - - ns 25 0 - - ns Full 0 - - ns (See Figure 4) Latch Hold Time, tH 7 ISL43841 Electrical Specifications: 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS Latch Pulse Width, tWPW (See Figure 4) TEMP (oC) MIN (NOTE 4) TYP 25 30 - - ns Full 40 - - ns 0.3 1 pC MAX (NOTE 4) UNITS Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0(See Figure 2) 25 - OFF Isolation RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 - 92 - dB 25 - 110 - dB 25 - -105 - dB Full 2 - 12 V Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 3.6V, V- = 0V, VLATCHH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Positive Supply Current, I- 25 -1 0.1 1 A Full -1 - 1 A 25 -1 0.1 1 A Full -1 - 1 A Test Circuits and Waveforms 3V LOGIC INPUT tr < 20ns tf < 20ns 50% V- C C 0V tTRANS NO0 LATCH V+ V- VOUT VNO0 SWITCH OUTPUT V+ C NO1, NO2 90% 0V COM ADD1, 2 GND VOUT RL 300 LOGIC INPUT 10% VNOX NO3 C tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V -----------------------------(NO) R + R L FIGURE 1A. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1B. ADDRESS tTRANS TEST CIRCUIT FIGURE 1. SWITCHING TIMES 8 ON CL 35pF ISL43841 Test Circuits and Waveforms (Continued) V+ V- C C 3V LOGIC INPUT OFF OFF ON VOUT LATCH RG 0V NO COM 0 SWITCH OUTPUT VOUT ADD1, 2 VOUT VG GND CL 1nF LOGIC INPUT Q = VOUT x CL Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ tr < 20ns tf < 20ns 3V LATCH 0V VOUT COM CL 35pF RL 300 NO0-NO3 V+ ADD1, 2 80% 0V C C LOGIC INPUT SWITCH OUTPUT VOUT V- C LOGIC INPUT tBBM GND Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME tr < 20ns tf < 20ns tMPW LOGIC INPUT LATCH V+ 3V 50% 0V 50% tH tH 50% 50% ADD1, 2 LOGIC INPUT LATCH 0V tON, tOFF VOUT 90% Logic input waveform is inverted for switches that have the opposite logic sense. V+ NO0 GND COM FIGURE 4A. LATCH tS, tH, tMPW MEASUREMENT POINTS VOUT RL 300 LOGIC INPUT Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO) R + R L ON FIGURE 4B. LATCH tS, tH, tMPW TEST CIRCUIT FIGURE 4. LATCH SETUP AND HOLD TIMES 9 C NO1-NO3 3V VNOX SWITCH OUTPUT 0V C 50% tS LOGIC INPUT ADDX V- C CL 35pF ISL43841 Test Circuits and Waveforms (Continued) V+ SIGNAL GENERATOR V- C V+ C RON = V1/1mA LATCH V- C C LATCH NOX NOX VNX 1mA 0V or V+ ADDX COMX ANALYZER 0V or V+ V1 ADDX COMX GND GND RL FIGURE 6. RON TEST CIRCUIT FIGURE 5. OFF ISOLATION TEST CIRCUIT V+ C V- C LATCH SIGNAL GENERATOR 50 NOA 0V or V+ V+ C NOX 0V or V+ ADDX ADDX IMPEDANCE ANALYZER COMB V- LATCH COMA NOB ANALYZER C N.C. GND COMX GND RL FIGURE 7. CROSSTALK TEST CIRCUIT FIGURE 8. CAPACITANCE TEST CIRCUIT Detailed Description Supply Sequencing And Overvoltage Protection The ISL43841 analog switch offers a precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on-resistance (39) and high speed operation (tON = 38ns, tOFF = 19ns) with dual 5V supplies. With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V+(see Figure 9). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. It has an latch bar pin to lock in the last switch address. The device is especially well suited for applications using 5V supplies. With 5V supplies the performance (RON, Leakage, Charge Injection, ect.) is best in class. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. 10 Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. ISL43841 This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 9). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1k OPTIONAL PROTECTION DIODE LOGIC VCOM VOPTIONAL PROTECTION DIODE FIGURE 9. INPUT OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL43841 construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL43841 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (6V or 12V single supply), as well as room for overshoot and noise spikes. This switch device performs equally well when operated with bipolar or single voltage supplies.The minimum recommended supply voltage is 2V or 2V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance Curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. 11 V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.3V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance V+ VNO Logic-Level Thresholds In 50 systems, signal response is reasonably flat even past 100MHz (see Figures 16 and 17). Figures 16 and 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. ISL43841 Typical Performance Curves TA = 25oC, Unless Otherwise Specified 70 VCOM = (V+) - 1V ICOM = 1mA V- = -5V 60 50 85oC 40 25oC 30 -40oC RON () RON () 20 400 V- = 0V 300 200 85oC -40oC -40oC VS =3V 85oC 25oC -40oC VS =5V 85oC 25oC 30 3 2 4 5 6 7 V+ (V) 8 9 10 11 20 12 -40oC -5 -4 -3 -1 -2 1 0 VCOM (V) 3 2 FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 225 200 60 ICOM = 1mA 55 50 25oC V+ = 2.7V V- = 0V -40oC 45 85oC V+ = 5V 85oC 25oC V+ = 3.3V -40oC V- = 0V 35 25oC V- = 0V 25 25oC -40oC -40oC 1 0 85oC 40 30 3 2 VCOM (V) 20 5 4 300 0 2 4 6 8 12 FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE 250 VCOM = (V+) - 1V VCOM = (V+) - 1V V- = 0V 250 10 VCOM (V) FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE 200 tRANS (ns) 200 150 100 150 100 25oC 25oC 85oC 85oC 50 50 -40oC -40oC 0 ICOM = 1mA 85oC RON () 75 160 140 120 100 80 60 100 90 80 70 60 50 40 V+ = 12V V- = 0V 5 4 FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE 125 100 RON () VS =2V 85oC 25oC 50 25oC 175 150 tRANS (ns) ICOM = 2mA 40 100 0 120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 FIGURE 14. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE 12 13 0 2 3 4 V (V) 5 FIGURE 15. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE 6 ISL43841 VIN = 0.2VP-P to 5VP-P GAIN 0 -3 0 PHASE 45 90 135 180 VS = 3V GAIN 0 -3 0 PHASE 45 90 135 180 RL = 50 1 VIN = 0.2VP-P to 4VP-P 3 RL = 50 10 100 600 1 10 FREQUENCY (MHz) -10 600 FIGURE 17. FREQUENCY RESPONSE 3 10 V+ = 3V to 12V or -20 VS = 2V to 5V RL = 50 -30 20 2 30 -50 50 -60 60 ISOLATION -70 70 CROSSTALK 80 V+ = 3.3V V- = 0V 1 -90 90 -100 100 V+ = 12V V- = 0V 0 Q (pC) 40 OFF ISOLATION (dB) -40 -80 100 FREQUENCY (MHz) FIGURE 16. FREQUENCY RESPONSE CROSSTALK (dB) PHASE (DEGREES) NORMALIZED GAIN (dB) VS = 5V 3 PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) V+ = 5V V- = 0V -1 VS =5V -2 -3 ALL HOSTILE CROSSTALK -110 1k 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 18. CROSSTALK AND OFF ISOLATION Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS 13 -4 -5 -2.5 0 2.5 5 7.5 10 VCOM (V) FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE 12 ISL43841 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 9 A3 b 0.20 REF 0.18 D 0.30 5, 8 4.00 BSC D1 D2 0.23 9 - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.50 BSC - k 0.25 - - - L 0.35 0.60 0.75 8 L1 - - 0.15 10 N 20 Nd 2 5 3 Ne 5 5 3 P - - 0.60 9 - - 12 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14