DATASHEET

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DatactSheet
November
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1-888-IN
Negative Signal Swing, High Off-Isolation,
Dual SPST Single Supply Switch
The Intersil ISL54066 device is a low ON-resistance, high
off-isolation, low voltage, dual single-pole/single-throw (SPST)
analog switch. It was designed to operate from a single +1.8V
to +6.5V supply and can pass signals that swing down to 6.5V
below the positive supply rail. Targeted applications include
battery powered equipment that benefit from low rON (1
high off-isolation (80dB) and fast switching speeds
(tON = 40ns, tOFF = 30ns). The digital logic input is 1.8V
logic-compatible when using a single +3V supply.
The ISL54066 incorporates a T-switch architecture. This
approach results in excellent signal off-isolation while
retaining a low impedance signal path when switches are ON.
The ISL54066 is offered in small form factor packages,
alleviating board space limitations. The ISL54066 is available
in 10Ld µTQFN and TDFN packages.
The ISL54066 is a dual single-pole/single-throw (SPST)
normally open (NO) switch with independent logic control.
2
Switch Type
SPST NO
4.3V rON
1
4.3V tON/tOFF
40ns/30ns
2.7V rON
1.5
2.7V tON/tOFF
60ns/30ns
1.8V rON
3
• Negative Signal Swing (Max 6.5V Below V+)
• T-switch Architecture
• ON-Resistance (rON)
- V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
• rON Matching Between Channels . . . . . . . . . . . . . . . . . 10m
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . . . 0.2
• Single Supply Operation . . . . . . . . . . . . . . . . .+1.8V to +6.5V
• Low Power Consumption @ 3V (PD). . . . . . . . . . . . 60nW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns
• Available in 10 Ld µTQFN and 10 Ld 3x3 TDFN
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
180ns/44ns
Packages
10 Ld µTQFN, 10 Ld TDFN
• Portable Test and Measurement
• Medical Equipment
ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
• Audio and Video Switching
V+ = 1.8V
Related Literature
2.2
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
2.0
rON ()
• Pb-free (RoHS Compliant)
• Low I+ Current when VinH is not at the V+ Rail
1.8V tON/tOFF
ICOM = 100mA
Features
• 1.8V Logic Compatible (+3V Supply)
ISL54066
Number of Switches
2.4
FN6584.1
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
TABLE 1. FEATURES AT A GLANCE
2.6
ISL54066
1.8
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1.6
V+ = 2.7V
1.4
1.2
V+ = 4.5V
1.0
0.8
-6
-5
-4
-3
-2
0
1
-1
VCOM (V)
1
2
3
4
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54066
Pinouts
Truth Table
(Note 1)
ISL54066
(10 LD TDFN)
TOP VIEW
CTL1 1
10 CTL2
200k
200k
NOTE:
OUT1 2
9 OUT2
GND1 3
8 GND2
IN1
10k
GND3 5
10k
6
OUT1
8
GND1
9
IN1
CTL2
7
6
200k
10k
10k
200k
10
1
2
GND3
V+
0
OPEN
1
CLOSED
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
PIN
V+
V+
ISL54066
(10 LD µTQFN)
TOP VIEW
CTL1
INx/OUTx
Pin Descriptions
7 IN2
4
CTLx
10k Input Shunt Ground
GND2
200k Output Shunt Ground
GND3
IC Ground Connection
CTLx
Digital Control Input
OUTx
OUT2
4
GND2
3
IN2
System Power Supply Input (+1.8V to +6.5V)
GND1
INx
5
FUNCTION
Switch x Input
Switch x Output
NOTE:
1. Switches Shown for CTLx = Logic “0”. Logic “0” 0.5V. Logic “1”
1.4V with a 3V supply.
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL54066IRZ
(Note 3)
4066
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54066IRZ-T
(Notes 2, 3)
4066
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54066IRUZ-T
(Notes 2, 4)
9
-40 to +85
10 Ld µTQFN (Tape and Reel)
L10.1.8x1.4A
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6584.1
November 3, 2009
ISL54066
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V
Input Voltages
INx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V)
CNTLx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
OUTx (Note 5) . . . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V)
Continuous Current INx or OUTx. . . . . . . . . . . . . . . . . . . . . ±300mA
Peak Current INx or OUTx
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
10 Ld 3x3 TDFN Package (Notes 6, 8)
55
18
10 Ld µTQFN Package (Note 7) . . . . .
155
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. Signals on NC, NO, IN, or COM exceeding V+ or GND by specified amount are clamped by internal diodes. Limit forward diode current to
maximum current ratings.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VCTL_H = 2.4V, VCTL_L = 0.8V (Note 9),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
TYP
MAX
(Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 4.5V, IOUT = 100mA, VIN = (V+ - 6.5) to V+,
(See Figure 4)
25
-
1
-

Full
-
1.2
-

rON Matching Between Channels,
rON
V+ = 4.5V, IOUT = 100mA, VIN = Voltage at max
rON, (Note 13)
25
-
5
-
m
Full
-
10
-
m
rON Flatness, RFLAT(ON)
V+ = 4.5V, IOUT = 100mA, VIN = (V+ - 6.5) to V+,
(Note 12)
25
-
0.21
-

Full
-
0.27
-

25
-
39
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 4.5V, VIN = 3.0V, RL = 50, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 4.5V, VIN = 3.0V, RL = 50, CL = 35pF
(See Figure 1)
Charge Injection, Q
VG = 0V, RG = 0, CL = 1.0nF (See Figure 2)
OFF-Isolation
Crosstalk (Channel-to-Channel)
Full
-
46
-
ns
25
-
27
-
ns
Full
-
33
-
ns
25
-
170
-
pC
RL = 50, CL = 5pF, f = 1MHz, VINx = 1VRMS
(See Figure 3)
25
-
70
-
dB
RL = 50, CL = 5pF, f = 1MHz, VIN1 = 1VRMS
(See Figure 5)
25
-
-80
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VOUT = 2VP-P, RL = 32
25
-
0.015
-
%
-3dB Bandwidth
RL = 50
25
-
30
-
MHz
INx OFF Capacitance, COFF
f = 1MHz, GND1 = float (See Figure 6)
25
-
33
-
pF
OUTx ON Capacitance, COUT(ON)
f = 1MHz, GND2 = float (See Figure 6)
25
-
124
-
pF
25
-
0.03
0.1
µA
Full
-
1.64
-
µA
POWER SUPPLY CHARACTERISTICS
V+ = +5.5V, VCTLx = 0V or V+
Positive Supply Current, I+
3
FN6584.1
November 3, 2009
ISL54066
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VCTL_H = 2.4V, VCTL_L = 0.8V (Note 9),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
TYP
MAX
(Notes 10, 11) UNITS
DIGITAL INPUT CHARACTERISTICS
Full
Input Voltage Low, VCTLx_L
Input Voltage High, VCTLx_H
Input Current, ICTLx_H, ICTLx_L
V+ = 5.5V, VCTLx = 0V or V+
-
-
0.8
V
Full
2.4
-
-
V
25
-0.1
-
0.1
µA
Full
-
0.9
-
µA
Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VCTL_H = 1.6V, VCTL_L = 0.5V (Note 9),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 4.3V, IOUT = 100mA, VIN = (V+ - 6.5) to V+,
(See Figure 4)
rON Matching Between Channels,
rON
V+ = 4.3V, IOUT = 100mA, VIN = Voltage at max
rON, (Note 13)
rON Flatness, RFLAT(ON)
V+ = 4.3V, IOUT = 100mA, VIN = (V+ - 6.5) to V+
(Note 12, 14)
25
-
1
-

Full
-
1.2
-

25
-
5
-
m
Full
-
10
-
m
25
-
0.2
-

Full
-
0.27
-

25
-
40
-
ns
Full
-
47
-
ns
25
-
31
-
ns
Full
-
34
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VIN = 3.0V, RL = 50, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VIN = 3.0V, RL = 50, CL = 35pF,
(See Figure 1)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
200
-
pC
OFF-Isolation
RL = 50, CL = 5pF, f = 1MHz, VINx = 1VRMS
(See Figure 3)
25
-
70
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 1MHz, VIN1 = 1VRMS
(See Figure 5)
25
-
-80
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32
25
-
0.02
-
%
INx OFF Capacitance, COFF
f = 1MHz, GND1 = float (See Figure 6)
25
-
33
-
pF
OUTx ON Capacitance, COUT(ON)
f = 1MHz, GND2 = float (See Figure 6)
25
-
124
-
pF
25
-
0.02
0.1
µA
Full
-
1.76
-
µA
25
-
0.95
12
µA
Input Voltage Low, VCTLx_L
Full
-
-
0.5
V
Input Voltage High, VCTLx_H
Full
1.6
-
-
V
25
-0.5
-
0.5
µA
Full
-
0.63
-
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +4.5V, VCTLx = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VCTL1 = VCTL2 = 2.85V
DIGITAL INPUT CHARACTERISTICS
Input Current, ICTLx_H, ICTLx_L
V+ = 4.5V, VCTLx = 0V or V+
4
FN6584.1
November 3, 2009
ISL54066
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VCTL_H = 1.4V, VCTL_L = 0.5V (Note 9),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 2.7V, IOUT = 100mA, VIN = (V+ - 6.5) to V+
(See Figure 4)
rON Matching Between Channels,
rON
V+ = 2.7V, IOUT = 100mA, VIN = Voltage at max
rON, (Note 13)
rON Flatness, RFLAT(ON)
V+ = 2.7V, IOUT = 100mA, VIN = (V+ - 6.5) to V+
(Notes 12, 14)
25
-
1.5
-

Full
-
1.9
-

25
-
10
-
m
Full
-
10
-
m
25
-
0.63
1

Full
-
0.68
1.35

25
-
60
-
ns
Full
-
68
-
ns
25
-
31
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VIN = 1.5V, RL = 50, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VIN = 1.5V, RL = 50, CL = 35pF
(See Figure 1)
Full
-
35
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
150
-
pC
OFF-Isolation
RL = 50, CL = 5pF, f = 1MHz, VINx = 1VRMS
(See Figure 3)
25
-
70
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 1MHz, VIN1 = 1VRMS
(See Figure 5)
25
-
-80
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VOUT = 2VP-P, RL = 32
25
-
0.04
-
%
INx OFF Capacitance, COFF
f = 1MHz, GND1 = float (See Figure 6)
25
-
33
-
pF
OUTx ON Capacitance, COUT(ON)
f = 1MHz, GND2 = float (See Figure 6)
25
-
124
-
pF
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VCTLx = 0V or V+
25
-
0.02
-
µA
Full
-
1.76
-
µA
Input Voltage Low, VCTLx_L
25
-
-
0.5
V
Input Voltage High, VCTLx_H
25
1.4
-
-
V
25
-0.5
-
0.5
µA
Full
-
0.55
-
µA
DIGITAL INPUT CHARACTERISTICS
Input Current, ICTLx_H, ICTLx_L
V+ = 3.3V, VCTL x = 0V or V+
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VCTL_H = 1.0V, VCTL_L = 0.4V (Note 9),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 1.8V, IOUT = 100mA, VIN = (V+ - 6.5V) to V+,
(See Figure 4)
rON Matching Between Channels,
RON
V+ = 1.8V, IOUT = 100mA, VIN = Voltage at max
rON, (Note 13)
rON Flatness, RFLAT(ON)
V+ = 1.8V, IOUT = 100mA, VIN = (V+ - 6.5) to V+,
(Note 12)
5
25
-
3
-

Full
-
3.2
-

25
-
20
-
m
Full
-
20
-
m
25
-
2.3
-

Full
-
2.5
-

FN6584.1
November 3, 2009
ISL54066
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VCTL_H = 1.0V, VCTL_L = 0.4V (Note 9),
Unless Otherwise Specified. (Continued)
PARAMETER
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
TEST CONDITIONS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VIN = 1.8V, RL = 50, CL = 35pF
(See Figure 1)
25
-
180
-
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VIN = 1.8V, RL = 50, CL = 35pF
(See Figure 1)
25
-
44
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
40
-
pC
-3dB Bandwidth
VCOM = 1VRMS, RL = 50CL = 5pF
25
-
30
-
MHz
INx OFF Capacitance, COFF
f = 1MHz, GND1 = float (See Figure 6)
25
-
33
-
pF
OUTx ON Capacitance, COUT(ON)
f = 1MHz, GND2 = float (See Figure 6)
25
-
124
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VCTLx_L
25
-
-
0.4
V
Input Voltage High, VCTLx_H
25
1.0
-
-
V
25
-0.5
-
-
µA
Full
-
0.5
-
µA
Input Current, ICTLx_H, ICTLx_L
V+ = 2.0V, VCTLx = 0V or V+
NOTES:
9. VCTL_x = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between IN1 and IN2.
14. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
50%
0V
SWITCH
INPUT
tOFF
OUT
IN
VOUT
CTL
SWITCH
INPUT VIN
VOUT
90%
SWITCH
OUTPUT
C
tr < 5ns
tf < 5ns
90%
LOGIC
INPUT
GNDx
RL
50
CL
35pF
0V
tON
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(IN) R + r
L
ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
6
FN6584.1
November 3, 2009
ISL54066
Test Circuits and Waveforms (Continued)
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
OUTx
INx
VOUT
VG
GNDx
CTLx
CL
V+
ON
ON
LOGIC
INPUT
OFF
LOGIC
INPUT
0V
Q = VOUT x CL
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
*50 SOURCE
SIGNAL
GENERATOR
V+
C
rON = V1/100mA
INx
INx
CTLx
VIN
0V
100mA
CTLx
V1
V+
OUTx
ANALYZER
GNDx
OUTx
RL
GNDx
Repeat test for all switches.
FIGURE 3. OFF-ISOLATION TEST CIRCUIT
FIGURE 4. rON TEST CIRCUIT
V+
C
V+
C
*50 SOURCE
SIGNAL
GENERATOR
IN1
OUT1
OUTx
50
CTLx
0V
OR V+
IMPEDANCE
ANALYZER
CTL1
V+
INx
OUT2
ANALYZER
IN2
GNDx
RL
FIGURE 5. CROSSTALK TEST CIRCUIT
7
GND3
*FLOAT GND1 and GND2
FIGURE 6. CAPACITANCE TEST CIRCUIT
FN6584.1
November 3, 2009
ISL54066
The ISL54066 is a dual single pole-single throw (SPST)
analog switch that offers precise switching from a single
1.8V to 6.5V supply with low ON-resistance (1.5), high
off-isolation, high speed operation (tON = 60ns, tOFF = 30ns)
and negative signal swing capability. The device is especially
well suited for portable battery powered equipment due to its
low operating supply voltage (1.8V), low power consumption
(30nA), and a tiny 1.8mmx1.4mm µTQFN package or a
3mmx3mm TDFN package. The low rON resistance and rON
flatness provide very low insertion loss and signal distortion
for applications that require signal switching with minimal
interference by the switch. In additon, the ISL54066 uses a
T-switch architecture to achieve superior off-isolation from the
input to output of the switch.
Input/Output Shunt Resistors
The ISL54066 contains input and output shunts resistors on
the switch terminals. On the INx pins, there are 10k shunts
to the GND1 pin. On the OUTx pins, there are 200k shunts
to the GND2 pin. The input shunts are designed to discharge
voltage that may be built up on the input pins, such as DC
offsets due to AC-coupled signals. The output shunts are
designed to bleed off any charge that may accumulate on
the output pins when the switch is turned off.
To have the shunt resistors enabled, connect the GND1 and
GND2 pins to GND3. The GND3 pin is the main ground of
the ISL54066 IC. The shunt resistors can be disconnected
from the IC by floating the appropriate GND1 and GND2 pin.
must be applied before any input signals, and the input
signal voltages must remain between (V+ - 6.5V) and V+.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a logic pin or switch terminal goes
above the V+ rail.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Alternatively, connecting
external Schottky diodes from the V+ rail to the signal pins
will shunt the fault current through the Schottky diode
instead of through the internal ESD diodes, thereby
protecting the switch. These Schottky diodes must be sized
to handle the expected fault current..
V+
+RING
VINx
VOUTx
Grounding Considerations
CLAMP
For maximum off-isolation performance, it is recommended
to follow a star ground configuration of the GNDx pins
(see Figure 7). Grounding the GND1, GND2 and GND3 pins
to a star ground ensures there are no cross conduction of
ground currents between the ground pins, which effect the
off-isolation capability of the switch.
V+
IN2
0.1µF
OUT2
GND1
CTL1
GND2
CTL2
GND
-RING
Power-Supply Considerations
OUT1
ISL54066
LOGIC
INPUTS
FIGURE 8. OVERVOLTAGE PROTECTION
VDD
IN1
1k
GND3
FIGURE 7. STAR GROUNDING CONFIGURATION
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND
(see Figure 8). To prevent forward biasing these diodes, V+
8
The ISL54066 construction is typical of most single supply
CMOS analog switches which have two supply pins: V+ and
GND. V+ and GND provide the CMOS switch bias and sets
their analog voltage limits. Unlike switches with a 5.5V
maximum supply voltage, the ISL54066 have a 6.5V
maximum supply voltage providing plenty of head room for
the 10% tolerance of 5V supplies due to overshoot and noise
spikes.
The minimum recommended supply voltage is +1.8V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the “Electrical Specifications” tables, beginning on page 3
and “Typical Performance Curves”, beginning on page 10 for
details.
FN6584.1
November 3, 2009
ISL54066
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to V+ and
GND signals levels to drive the analog switch gate terminals.
A high frequency decoupling capacitor placed as close to the
V+ and GND pin as possible is recommended for proper
operation of the switch. A value of 0.1µF is highly
recommended.
Negative Signal Swing Capability
The ISL54066 contains circuitry that allows the analog switch
signal to swing below ground. The device has an analog signal
range of 6.5V below V+ up to the V+ rail (see Figure 14) while
maintaining low rON performance. For example, if V+ = 5V,
then the analog input signal range is from -1.5V to +5V. If
V+ = 2.7V then the range is from -3.8V to +2.7V.
diodes conducts if any analog signal exceeds the
recommended analog signal range.
Virtually all the analog switch leakage current comes from
the ESD diodes and reversed biased junctions in the switch
cell. Although the ESD diodes on a given signal pin are
identical and therefore fairly well balanced, they are reverse
biased differently. Each is biased to either the +Ring or -Ring
and the analog input signal. This means their leakages will
vary as the signal varies. The difference in the two diode
leakages to the +Ring or -Ring and the reverse biased
junctions at the internal switch cell constitutes the
analog-signal-path leakage current.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.45V VOLMAX
and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V
(see Figure 16). At 3.3V the VIL level is 0.5V maximum. This
is still below the 1.8V CMOS guaranteed low output
maximum level of 0.45V, but noise margin is reduced. At
3.3V the VIH level is 1.4V minimum. While this is above the
1.8V CMOS guaranteed high output minimum of 1.35V
under most operating conditions the switch will recognize
this as a valid logic high.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation. The ISL54066 has been
designed to minimize the supply current whenever the digital
input voltage is not driven to the supply rails (0V to V+). For
example, driving the device with 2.85V logic high while
operating with a 4.2V supply, the device draws only 1µA of
current.
High-Frequency Performance
In 50 systems, the ISL54066 has a -3dB bandwidth of
30MHz (see Figure 19). The frequency response is very
consistent over a wide V+ range and for varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off-Isolation
is the resistance to this feed-through, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 20 details the high Off-Isolation and
Crosstalk rejection provided by this part. At 1MHz,
Off-Isolation is approximately 70dB in 50 systems,
decreasing approximately 40dB per decade as frequency
increases. Crosstalk is approximately -80dB at 1MHz in 50
systems.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin, V+ and GND. One of these
9
FN6584.1
November 3, 2009
ISL54066
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
1.4
2.6
ICOM = 100mA
2.4
IOUT = 100mA
1.2
2.2
T = +85°C
1.1
2.0
1.8
rON ()
rON ()
V+ = 4.5V
1.3
V+ = 1.8V
1.6
T = +25°C
0.9
0.8
V+ = 2.7V
1.4
1.0
0.7
1.2
V+ = 4.5V
T = -40°C
0.6
1.0
0.5
0.8
-6
-5
-3
-4
-2
-1
1
0
2
3
0.4
5
4
-3
-2
-1
0
1
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
1.4
2.0
1.7
T = +85°C
1.6
1.5
rON ()
rON ()
T = +25°C
0.8
1.4
1.3
1.2
T = +85°C
1.1
0.7
1.0
T = -40°C
0.5
0.4
-3
0.9
T = +25°C
0.8
T = -40°C
0.7
-2
-1
0
1
VOUT (V)
2
3
4
0.6
-5
5
-4
-3
-2
-1
0
VOUT (V)
1
2
3
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
4.0
6
V+ = 1.8V
IOUT = 100mA
3.0
2.5
2.0
1.5
T = 85°C
1.0
0.5
0.0
-6
T = 25°C
SIGNAL MAX
4
3
2
1
0
-1
-2
-3
SIGNAL MIN
-4
T = -40°C
-5
4
5
ANALOG SIGNAL RANGE (V)
3.5
rON ()
5
IOUT = 100mA
1.8
1.0
0.6
4
V+ = 2.7V
1.9
IOUT = 100mA
1.2
0.9
3
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
V+ = 4.3V
1.3
1.1
2
VOUT (V)
VCOM (V)
-5
-4
-3
-2
-1
VOUT (V)
0
1
2
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
10
3
-6
1.5
2.0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
6.0
FIGURE 14. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE
FN6584.1
November 3, 2009
ISL54066
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
1.6
700
1.5
V+ = 5.5V
650
1.4
1.3
ABSOLUTE VALUES
600
550
1.2
500
Q (pC)
450
400
350
V+ = 3.3V
300
250
200
1.0
0.9
0.8
0.7
0.4
0.3
0.2
V+ = 2.0V
50
0
-5
-4
-3
VCTL_L
0.6
0.5
150
100
VCTL_H
1.1
VCTL_H AND VCTL_L
V+ = 4.5V
0.1
-2
-1
0
1
VCOM (V)
2
3
4
5
0
1.5
6
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
2.0
2.5
3.0
V+ (V)
3.5
4.0
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
40
160
T = -40°C
140
T = -40°C
35
T = +25°C
T = +85°C
120
25
tOFF (ns)
tON (ns)
T = +25°C
T = +85°C
30
100
80
20
60
15
40
10
20
5
0
1.8
3.3
V+ (V)
4.5
0
5.5
1.8
3.3
4.5
5.5
V+ (V)
FIGURE 17. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 18. TURN-OFF TIME vs SUPPLY VOLTAGE
20
1
V+ = 1.8V to 5.5V
V+ = 1.8V to 5.5V
10
0
RL = 50
VIN = 1VRMS @ 0VDC OFFSET
0
-10
-1
-20
-2
CROSSTALK (dB)
NORMALIZED GAIN (dB)
4.5
-3
-4
-5
-30
-40
-50
OFF-ISOLATION
-60
-70
CROSSTALK
-80
-6
RL = 50
VIN = 1VRMS @ 0VDC OFFSET
-90
-100
-7
-110
-8
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 19. FREQUENCY RESPONSE
11
1G
-120
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 20. CROSSTALK AND OFF-ISOLATION
FN6584.1
November 3, 2009
ISL54066
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
0.09
Die Characteristics
0.08
SUBSTRATE POTENTIAL (POWERED UP):
707mVRMS
GND (DFN Paddle Connection: Tie to GND or Float)
0.07
360mVRMS
TRANSISTOR COUNT:
THD+N (%)
0.06
432
0.05
PROCESS:
177mVRMS
0.04
Submicron CMOS
0.03
0.02
V+ = 3.3V
VBIAS = 0VDC
0.01
0
20
RL = 32
100
200
1k
2k
FREQUENCY (Hz)
10k
20k
FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY
12
FN6584.1
November 3, 2009
ISL54066
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
L10.1.8x1.4A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
0.10 C
1
2X
2
0.10 C
TOP VIEW
C
A
0.05 C
SIDE VIEW
(DATUM A)
PIN #1 ID
1
2
NX L
NX b 5
10X
0.10 M C A B
0.05 M C
L1
5
(DATUM B)
7
MAX
NOTES
0.50
0.55
-
A1
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
A1
NOMINAL
0.45
A3
0.10 C
SEATING PLANE
MIN
A
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
-
N
10
2
Nd
2
3
Ne
3
3

0
-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
e
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
NX (b)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
5
L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
SECTION "C-C"
e
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
2.20
1.00
0.60
1.00
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.50
1.80
0.40
0.20
0.20
0.40
10 LAND PATTERN
13
FN6584.1
November 3, 2009
ISL54066
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
0.25
1
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
NOMINAL
D2/2
(DATUM A)
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6584.1
November 3, 2009
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