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ISL54302
ESIGNS
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March 19, 2008
E C OM
RData
ISL5405
12V, 1.5 Quad SPST Switch with Latched
Parallel Interface
The ISL54302 is a quad analog bidirectional switch device
targeted at industrial applications, including test and
measurement equipment. It features low resistance and low
leakage along with 12V operation and can be digitally
controlled via a latched parallel interface. This parallel
interface features a latch input pin that can be used to connect
multiple devices into a parallel arrangement.
FN6592.0
Features
• 4 independently controlled SPST switches
• ON-resistance @ 12V. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5
• Single or split supply voltage operation
• rON flatness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <1
• rON matching between channels . . . . . . . . . . . . . . . . . <0.2
• Turn-on/Turn-off time . . . . . . . . . . . . . . . . . . . . . . . 25ns/80ns
The ISL54302 can operate from a single, or split bipolar
power supply and has a 3V logic interface. The ISL54302 is
specified for use over the -40°C to +85°C temperature range
and is available in a 20 Ld 4x4 QFN Pb-free package.
• Switch bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60MHz
Table 1 summarizes the performance of this family.
• 20 Ld QFN package
TABLE 1. FEATURES AT A GLANCE
CONFIGURATION
QUAD SPST
rON
1.5
tON/tOFF
25ns/80ns
Package
20 Ld QFN 4x4
• Parallel data interface up to 40MHz
• 3V logic interface
• Pb-free (RoHS compliant)
Related Literature
• TB363 “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
• TB389 “PCB Land Pattern and Surface Mount Guidelines
for QFN Packages”
• AN557 “Recommended Test Procedures for Analog
Switches”
Pinout
ISL54302
(20 LD QFN)
TOP VIEW
NC
VSS
VDD
VLOGIC
VPLUS
Ordering Information
20
19
18
17
16
PART
NUMBER
(Note)
ISL54302IRZ*
14 3B
1B
3
13 4A
1A
4
12 4B
CS-LATCH
5
11 NC
6
7
8
9
10
S4-CTRL
2
S3-CTRL
2A
GND
15 3A
S2-CTRL
1
S1-CTRL
2B
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
54 302IRZ -40 to +85 20 Ld 4x4 QFN L20.4x4C
*Add “-T” for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
ISL54302 Block Diagram
VLOGIC
S1-CTRL
LATCHES
VDD
VPLUS
1 OF 4
S2-CTRL
S3-CTRL
S4-CTRL
GND
CS-LATCH
1
PKG.
DWG. #
LEVEL
SHIFTER
VSS
SW-A
SW-B
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54302
Pin Descriptions
PIN NUMBER
PIN NAME
1
2B
Switch 2 signal terminal
2
2A
Switch 2 signal terminal
3
1B
Switch 1 signal terminal
4
1A
Switch 1 signal terminal
5
CS-LATCH
6
S1-CTRL
Switch one logic control
7
S2-CTRL
Switch two logic control
8
GND
Device ground terminal
9
S3-CTRL
Switch three logic control
10
S4-CTRL
Switch four logic control
11
NC
Not internally connected
12
4B
Switch 4 signal terminal
13
4A
Switch 4 signal terminal
14
3B
Switch 3 signal terminal
15
3A
Switch 3 signal terminal
16
VPLUS
Positive analog power supply
17
VLOGIC
Logic supply voltage
18
VDD
Level shifter supply voltage
19
VSS
Negative analog power supply
20
NC
Not internally connected
2
PIN DESCRIPTION
Chip Select input
March 19, 2008
ISL54302
Absolute Maximum Ratings
Thermal Information
VPLUS to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to15V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VLOGIC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VSS to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to 0.3V
VPLUS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
All Other Pins (Note 1) . . . . . . . . ((VSS) - 0.3V) to ((VPLUS) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 35mA
Peak Current, 1A-4A,1B-4B
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
20 Ld QFN Package (Notes 2, 3) . . . . . .
32
1.4
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Analog Switch Signal Range . . . . . . . . VSS + 0.5V to VPLUS - 0.5V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on 1A-4A,1B-4B, exceeding VPLUS or VSS are clamped by internal diodes. DATA_IN, CLOCK_IN, CS_LATCH exceeding VLOGIC or
VSS are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, VINH = 2.2V, VINL = 0.8V,
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
(Note 10)
MAX
(Note 9)
UNITS
ANALOG SWITCH CHARACTERISTICS
ON-resistance, rON
ICOM = 10mA, VXA, VXB within analog signal
(see Figure 4)
rON Matching Between Channels,
rON
ICOM = 10mA, VXA, VXB within analog signal range
(Note 5)
rON Flatness, rFLAT(ON)
ICOM = 10mA, VXA, VXB within analog signal range
(Note 4)
OFF Leakage Current, INO(OFF)
VXA, VXB within analog signal range
25
2.0

Full
2.5

25
0.2

Full
0.3

25
0.4

Full
0.6

25
15
nA
Full
-200
+200
nA
Input Voltage High, Digital Interface SW-CTRL(1-4), CS_LATCH
Full
2.2
Input Voltage Low, Digital Interface
SW-CTRL(1-4), CS_LATCH
Full
1.75
SW-CTRL (1-4) Into CS_Latch
Setup Time
tSETUP (Note 6, Figure 5)
Full
1
ns
SW-CTRL (1-4) Into CS_Latch Hold tHOLD (Note 6, Figure 5)
Time
Full
3.5
ns
Input Current, IINH, IINL
VIN = 0V or VLOGIC
Full
CS_LATCH Rise, Fall Time
10% to 90% and 90% to 10%
Full
3
ns
CS_LATCH Minimum Pulse Width
Rising to Falling Edge 50% Points
Full
10
ns
25
50
ns
Full
55
ns
DIGITAL INPUT CHARACTERISTICS (Note 8)
-1
1.75
0.01
V
0.8
1
V
µA
SWITCH DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VXA, VXB = 3V, RL = 300, CL = 35pF, VIN = 0V to 3V,
(see Figure 1)
3
March 19, 2008
ISL54302
Electrical Specifications
Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, VINH = 2.2V, VINL = 0.8V,
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
Turn-OFF Time, tOFF
VXA, VXB = 3V, RL = 300, CL = 35pF, VIN = 0V to 3V,
(see Figure 1)
TEMP
(°C)
MIN
(Note 9)
TYP
(Note 10)
MAX
(Note 9)
UNITS
25
90
ns
Full
95
ns
OFF Capacitance, COFF
f = 1MHz, VXA or VXB = 0V
25
50
pF
ON Capacitance, CCOM(ON)
f = 1MHz, VXA or VXB = 0V
25
100
pF
OFF Isolation
RL = 50, CL = 15pF, f = 1MHz,
VXA or VXB = 1VP-P (see Figure 3)
25
-45
dB
25
-65
dB
60
MHz
25
125
pC
25
15
µA
Full
17
25
18
µA
Full
22
µA
25
16
µA
Full
22
25
1
mA
Full
1
mA
25
1
µA
Full
4
25
0.4
mA
Full
0.4
mA
25
0
µA
Full
1
25
3.5
mA
Full
3.5
mA
Crosstalk (Note 5)
Switch Contact 3dB Bandwidth
RL = 50, CL = 5pF
Charge Injection, Q
CL = 1nF, VG = 0V, RG = 0see Figure 2)
POWER SUPPLY CHARACTERISTICS
VPLUS Supply, I (Quiescent)
VPLUS Supply, I (40MHz)
VSS Supply, I (Quiescent)
VSS Supply, I (40MHz)
VDD Supply, I (Quiescent)
VDD Supply, I (40MHz)
VLOGIC Internal Logic Supply, I
(Quiescent)
VLOGIC Internal Logic Supply, I
(40MHz)
Electrical Specifications
45
µA
50
µA
10
µA
10
µA
Test Conditions: VPLUS = +7V, VSS = 0V Supply, VLOGIC= 3V, VDD = 3V, GND = 0V, VINH = 2.2V, VINL = 0.8V,
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
ICOM = 10mA, VXA, VXB within Analog Signal Range
(see Figure 4)
25
2.7

Full
3.5

rON Matching Between Channels,
rON
ICOM = 10mA, VXA, VXB within Analog Signal Range
(Note 5)
25
0.1

Full
0.15

rON Flatness, rFLAT(ON)
ICOM = 10mA, VXA, VXB within Analog Signal Range
(Note 4)
25
0.5

Full
0.6

VXA = 1V, 4.5V, VXB= 4.5V, 1V
25
3
nA
PARAMETER
MIN
(Note 9)
TYP
(Note 10)
MAX
(Note 9)
UNITS
ANALOG SWITCH CHARACTERISTICS
ON-resistance, rON
OFF Leakage Current, INO(OFF)
Full
-200
30
Input Voltage High, Digital Interface SW-CTRL(1-4), CS_LATCH
Full
2.2
1.75
Input Voltage Low, Digital Interface
Full
200
nA
DIGITAL INPUT CHARACTERISTICS (Note 8)
4
SW-CTRL(1-4), CS_LATCH
1.75
V
0.8
V
March 19, 2008
ISL54302
Electrical Specifications
Test Conditions: VPLUS = +7V, VSS = 0V Supply, VLOGIC= 3V, VDD = 3V, GND = 0V, VINH = 2.2V, VINL = 0.8V,
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
(Note 10)
MAX
(Note 9)
UNITS
tSETUP (Note 6, Figure 5)
Full
1
ns
SW-CTRL (1-4) Into CS_Latch Hold tHOLD (Note 6, Figure 5)
Time
Full
3.5
ns
SW-CTRL (1-4) Into CS_Latch
Setup Time
Input Current, IINH, IINL
VIN = 0V or VLOGIC
Full
CS_LATCH Rise, Fall Time
10% to 90% and 90% to 10%
Full
3
ns
CS_LATCH Minimum Pulse Width
Rising to Falling Edge 50% Points
Full
10
ns
Turn-ON Time, tON
VXA or VXB = 3V, RL = 300, CL = 35pF
(see Figure 1)
25
25
ns
Turn-OFF Time, tOFF
VXA or VXB = 3V, RL = 300, CL = 35pF
(see Figure 1)
-1
0.01
1
µA
DYNAMIC CHARACTERISTICS
Full
30
ns
25
80
ns
Full
85
ns
OFF Capacitance, COFF
f = 1MHz, VXA or VXB = VCOM = 0V
25
50
pF
ON Capacitance, CCOM(ON)
f = 1MHz, VXA or VXB = VCOM = 0V
25
100
pF
OFF Isolation
25
-45
dB
Crosstalk (Note 5)
RL = 50, CL = 15pF, f = 1MHz,
VXA or VXB= 1VP-P (see Figure 3)
25
-65
dB
Switch Contact 3dB Bandwidth
RL = 50, CL = 5pF
25
60
MHz
Charge Injection, Q
CL = 1nF, VG = 0V, RG = 0see Figure 2)
25
25
pC
25
13
µA
POWER SUPPLY CHARACTERISTICS
VPLUS Supply, I (Quiescent)
VPLUS Supply, I (40MHz)
VSS Supply, I (Quiescent)
VSS Supply, I (40MHz)
VDD Supply, I (Quiescent)
VDD Supply, I (40MHz)
Full
15
25
18
µA
Full
20
µA
25
14
Full
19
45
µA
µA
50
µA
25
0.7
mA
Full
0.7
mA
25
1
µA
Full
4
25
0.4
10
mA
µA
Full
0.5
mA
VLOGIC Internal Logic Supply, I
(Quiescent)
25
0
Full
1
µA
VLOGIC Internal Logic Supply, I
(40MHz)
25
3.2
mA
Full
3.2
mA
10
µA
NOTES:
4. Flatness is defined as the delta between the maximum and minimum rON values over the specified voltage range.
5. Between any two switches.
6. CS_LATCH must remain low when changing SW-CTRL(1-4) condition. Likewise, while CS_LATCH is being toggled, it is important to keep SWCTRL(1-4) in the intended switch condition.
7. Typical Values are not production tested
8. Digital Characteristics remain stable with respect to VPLUS and VSS variation. These parameters are controlled by the difference between VSS
and VDD, which the user should maintain at a constant spread of VDD = VSS + 3V.
9. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
10. Limits established by characterization and are not production tested.
5
March 19, 2008
ISL54302
Test Circuits and Waveforms
tr < 20ns
tf < 20ns
3V
CS-LATCH
INPUT
50%
VPLUS
VDD
C
C
VLOGIC
C
C
0V
tON
VNB
VNB
VOUT
25%
SWITCH
INPUTS
IN
VOUT
1-4A
1-4B
LATCH
tOFF
SX-CRTL
INPUT
VNB
C
VSS
75%
VOUT
Switch changes state on rising edge of CS-LATCH. VNA = VOUT at
all times.
CL
35pF
RL
300
GND
SWITCH
OUTPUT
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NB) ---------------------------R L + r  ON 
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VPLUS
SWITCH
OUTPUT
VOUT
VOUT
RG
3V
OFF
CONTROLLER
SEQUENCE
SW: ON/OFF/ON
0V
C
VLOGIC
C
VOUT
1-4B
LATCH
VG
IN
Q = VOUT x CL
C
Switch changes state on rising edge of CS-LATCH.
VDD
1-4A
ON
ON
C
GND
CL
VSS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
VPLUS
C
VDD
C
VLOGIC
C
VPLUS
C
VDD
C
VLOGIC
C
rON = V1/10mA
SIGNAL
GENERATOR
1-4A
1-4A
VXA
CS-LATCH/SX-CRTL
1-4B
ANALYZER
10mA
CS-LATCH/SX-CRTL
V1
1-4B
GND
GND
RL
VSS
C
Repeat test for all switches.
VSS
C
Repeat test for all switches.
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
FIGURE 4. rON TEST CIRCUIT
March 19, 2008
ISL54302
Test Circuits and Waveforms (Continued)
SX-CTRL SHOULD REMAIN IN DESIRED STATE, BEFORE DURING AND AFTER CS-LATCH.
CS-LATCH
INPUT
50%
50%
tSETUP
tHOLD
100%
DATA = 1
SX-CTRL
100%
DATA = 0
FIGURE 5. SETUP AND HOLD TIMES
ISL54302 Detailed Description
ISL54302 Parallel Communications
The ISL54302 quad analog switches offer switching capability
from a split-supply -3V and +9V or single 0V and 5V to 12V
supply. Please review “Power Supply Considerations” on
page 7 before powering up the device.
The ISL54302 operates based on parallel data. CTRL and
LATCH inputs are 3V level compatible. Setup and Hold times
relative to the rising the edge of the CS-LATCH input must
be maintained for proper operation. Switch control data is
clocked into internal registers on the rising edge of
CS-LATCH.
The user can employ multi-device control data in two ways.
The S1-S4-CTRL lines can be connected to several devices,
with each device having its own CS-LATCH connection to
the system controller. The other way is to have separate
S1-4-CTRL connections for each switch and a single
CS-LATCH connection to all ISL54302s.
Power Supply Considerations
The ISL54302 construction consists of CMOS analog
switches and four supply pins: VPLUS, VSS, VLOGIC, VDD
and GND. VPLUS and VSS determine the switch voltage
range of the four SPST CMOS switches and set their analog
voltage limits. There are no connections between the switch
contact signal path and GND.
VLOGIC and GND power the digital input/output logic level
shifters (thus setting the digital switching point). The level
shifters convert the external logic levels to VDD and VSS
signals to drive the internal digital circuitry.
VDD and VSS power the internal logic of the device. VDD
must always be held at a fixed 3V above VSS to avoid
device damage.
Whether operating split or single device, GND will
always be @ 0V and VLOGIC will always be @ 3V.
VDD should always remain 3V above VSS. VSS to
VPLUS should not exceed a maximum spread of more
than 12V. For examples, see the following:
SPLIT POSITIVE AND NEGATIVE SWITCH RANGE
OPERATION
• VSS = -3V, VDD = +0V, VPLUS = +9V, VLOGIC = 3V
• VSS = -1V, VDD = +2V, VPLUS = +11V, VLOGIC = 3V
POSITIVE SWITCH RANGE OPERATION
• VSS = 0V, VDD = +3V, VPLUS = +12V, VLOGIC = 3V
7
MULTIPLE DEVICE CONNECTION
The user can configure the four SX-CTRL inputs to connect
to several ISL54302’s. In this configuration each ISL54302
requires a separate/dedicated CS-LATCH input. Therefore,
each device will update at different times.
So in essence, the S1-S4-CTRL signals are multiplexed and
connected to all switch control inputs in parallel (see Figure 8).
For non-multiplexed connections, each SX-CTRL input must
have a dedicated logic input for each switch/each device. If
three ISL54302s are being used, the user must supply 12
dedicated SX-CTRL signals. All switches are then tied to the
same CS-LATCH pin and all devices would change state at
the same time.
ISL54302 CS-LATCH Pin Discussion
The ISL54302’s operational state does not change while
SX-CTRL inputs are changing. The user must insure that the
CS-LATCH pin remains low and does not change state while
SX-CTRL inputs are changing.
Once the user has set the SX-CTRL inputs, the CS-LATCH
pin is then utilized. Just as the CS-LATCH pin must remain
low during SX-CTRL setup, the SX-CTRL pins must remain
stable during and after the CS-LATCH operation.
The switch from present to next operation occurs on the
rising edge on the CS-LATCH pin. This rising edge transfers
data to the internal 4-bit switch control registers. This
transfer updates opening/closing of the four switches.
ISL54302 Power On Reset (POR)
Switch conditions are controlled during POR (Power On
Reset). During and after a POR condition, the switches are
opened until closed by the controller.
March 19, 2008
ISL54302
SW2-B
SW3-A
S3 CONTROL
SW2-A
S2 CONTROL
SW3-B
INTERNAL
CS-LATCH
REGISTERS
INTERNAL
CS-LATCH
REGISTERS
SW1-B
SW4-A
S4 CONTROL
S1 CONTROL
SW4-B
LEVEL
SHIFTER
LEVEL
SHIFTER
S4-CTRL
LEVEL
SHIFTER
S3-CTRL
LEVEL
SHIFTER
S2-CTRL
CS-LATCH
LEVEL
SHIFTER
S1-CTRL
SW1-A
FIGURE 6. ISL54302 FUNCTIONAL DIAGRAM
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All switch contact
I/O pins contain ESD protection diodes from the pin to
VPLUS and to VSS (see Figure 7). To prevent forward
biasing these diodes, VPLUS, GND and VSS must be
applied before any input signals, and switch signal voltages
must remain between VPLUS and VSS. Digital control
signals should be limited to VLOGIC and VSS.
The leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
ESD Protection
The device contains ESD protection on the device pins.
These devices are design to work based on dV/dt. During
power-up, the user should review the rise/fall times on the
power connections. The rise time of the power rails should
not be faster than 1µs.
SPECIFIC POWER SEQUENCE
1. GND
2. VSS Typical . . . . . . . . . . . 3V to 0V with respect to GND
VPLUS
VDD
VLOGIC
CLAMP
CLAMP
CLAMP
VSS
VSS
GND
VPLUS
3. VPLUS Typical . . . . . . . +5V to +9V with respect to GND
4. VDD . . . . . . . . . . . . . . . . . . . +3V to with respect to VSS
ONE FOR EACH PIN LISTED: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B,
VDD, VLOGIC
5. VLOGIC . . . . . . . . . . . . . . . . . . +3V with respect to GND
If these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input. The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 7). These additional diodes
limit the analog signal from 1V below VPLUS to 1V above VSS.
8
VLOGIC
ONE FOR EACH PIN LISTED: S1-CTRL, S2-CTRL,
S3-CTRL, S4-CTRL, CS-LATCH
GND
VSS
FIGURE 7. ESD/OVERVOLTAGE PROTECTION
March 19, 2008
ISL54302
Logic-Level Thresholds
ISL54302 Device Programming
VLOGIC and GND power the internal logic level shifter
stages, so VPLUS and VSS have no affect on logic
thresholds. Thus, SX-CTRL, CS-LATCH receive thresholds
which will remain constant, despite changes to VPLUS and
VSS.
Programming the device entails accessing the internal
switch control registers. To write data into the register, the
data must be transferred via the CS-LATCH pin.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both VPLUS and VSS.
One of these diodes conducts if any analog signal exceeds
VPLUS or VSS.
9
Via the CS-LATCH pin, the programmer has complete
control as to “when” data is transferred to the internal
latches. Until such time as the CS-LATCH pin is “toggled,”
the device will remain as previously programmed. Therefore,
data transitions on the SX-CTRL inputs will not effect the
switch’s operational condition.
March 19, 2008
ISL54302
VPLUS (VSUB+5 TO VSUB+12V)
VLOGIC (GND + 3V)
VDD (VSUB +3V)
VSUB (-3V TO 0V)
GND
C1
4.7µF
C2
4.7µF
C3
4.7µF
C4
4.7µF
SWITCH CONTACT
CONNECTIONS
5
4
3
2
1
CS-LATCH DEVICE 1
SW1-CTRL
CS-LATCH
1A
1B
2A
2B
DIGITAL INPUTS FROM
SYSTEM CONTROLLER
6
7
8
9
10
SW2-CTRL
SW3-CTRL
NC
VSS
VDD
VLOGIC
VPLUS
20
19
18
17
16
C5
0.1µF
11
12
13
14
15
NC
4B
4A
3B
3A
SW4-CTRL
SW1_CTRL
SW2_CTRL
GND
SW3_CTRL
SW4_CTRL
C8
0.1µF
C9
0.1µF
C10
0.1µF
ISL54302
SWITCH CONTACT
CONNECTIONS
5
4
3
2
1
CS-LATCH DEVICE 2
1A
1B
2A
2B
CS-LATCH
SW1_CTRL
SW2_CTRL
GND
SW3_CTRL
SW4_CTRL
NC
VSS
VDD
VLOGIC
VPLUS
20
19
18
17
16
11
12
13
14
15
NC
4B
4A
3B
3A
6
7
8
9
10
DEVICE DECOUPLING
C6
0.1µF
C11
0.1µF
C12
0.1µF
C13
0.1µF
C7
0.1µF
C14
0.1µF
C15
0.1µF
C16
0.1µF
ISL54302
SWITCH CONTACT
CONNECTIONS
5
4
3
2
1
CS-LATCH DEVICE 3
1A
1B
2A
2B
CS-LATCH
SW1_CTRL
SW2_CTRL
GND
SW3_CTRL
SW4_CTRL
NC
VSS
VDD
VLOGIC
VPLUS
20
19
18
17
16
11
12
13
14
15
NC
4B
4A
3B
3A
6
7
8
9
10
ISL54302
GND
SWITCH CONTACT
CONNECTIONS
FIGURE 8. ISL54302 SW-CONTROL LINES MULTIPLEXED
10
March 19, 2008
ISL54302
Typical Performance Curves
VLOGIC = 3V, TA = +25°C, VIH = 3V, VIL = 0V, Unless Otherwise Specified.
5.0
5.0
ICOM = 10mA
VSS = -3V, VPLUS = 3V, VDD = 0V
4.5
4.5
4.0
3.5
3.5
+85°C
+25°C
3.0
2.5
rON ()
rON ()
3.0
+25°C
2.0
-40°C
2.5
1.5
1.0
1.0
0.5
0.5
-3
-2
-1
0
1
2
0.0
3
-40°C
2.0
1.5
0.0
+85°C
4.0
1
2
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
5.0
ICOM = 10mA
VSS = -3V, VPLUS = 7V, VDD = 0V
4.5
4.0
+85°C
3.5
3.0
3.5
2.5
-40°C
2.0
2.0
1.5
1.0
1.0
0.5
0.5
0.0
-2
-1
0
1
2
3
4
5
6
+25°C
2.5
1.5
-3
+85°C
3.0
+25°C
rON ()
rON ()
ICOM = 10mA
VSS = 0V, VPLUS = 7V, VDD = 3V
4.5
4.0
7
-40°C
0
1
2
3
VCOM (V)
4
5
6
7
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
5.0
4.5
ICOM = 10mA
VSS = -3V, VPLUS = 9V, VDD = 0V
4.0
4.0
3.5
3.5
3.0
3.0
2.5
+85°C
2.0
1.5
2.5
+85°C
2.0
1.5
-40°C
1.0
+25°C
-2
-1
0
1
2
3
4
5
6
7
8
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
11
+25°C
0.5
0.0
-3
-40°C
1.0
0.5
ICOM = 10mA
VSS = 0V, VPLUS = 12V, VDD = 3V
4.5
rON ()
rON ()
3
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
0.0
ICOM = 10mA
4
5
VSS = 0V, VPLUS = 5V, VDD = 3V
0
9
0.0
0
1
2
3
4
5
6
7
VCOM (V)
8
9
10
11
12
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
March 19, 2008
ISL54302
Typical Performance Curves
VLOGIC = 3V, TA = +25°C, VIH = 3V, VIL = 0V, Unless Otherwise Specified. (Continued)
5.0
5.0
VSS = -3V, VPLUS = 3V, VDD = 0V
4.5
4.0
4.0
3.5
3.5
3.0
3.0
VCOM (nA)
VCOM (nA)
4.5
2.5
2.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
-3
-2
-1
0
1
2
0.0
3
VSS = 0V, VPLUS = 5V, VDD = 3V
0
1
2
VCOM (V)
FIGURE 15. ON-LEAKAGE vs SWITCH VOLTAGE
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
-3
-2
-1
0
1
VSS = 0V, VPLUS = 7V, VDD = 3V
4.5
VCOM (nA)
VCOM (nA)
5
5.0
VSS = -3V, VPLUS = 7V, VDD = 0V
4.5
2
3
4
5
6
0.0
7
0
1
2
3
4
5
6
7
VCOM (V)
VCOM (V)
FIGURE 17. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 18. ON-LEAKAGE vs SWITCH VOLTAGE
5.0
VSS = -3V, VPLUS = 9V, VDD = 0V
4.0
4.0
3.5
VCOM (nA)
3.5
3.0
2.5
2.0
3.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0 -3
VSS = 0V, VPLUS = 12V, VDD = 3V
4.5
4.5
VCOM (nA)
4
FIGURE 16. ON-LEAKAGE vs SWITCH VOLTAGE
5.0
5.0
3
VCOM (V)
0.0
-2
-1
0
1
2
3
4
5
6
7
VCOM (V)
FIGURE 19. ON-LEAKAGE vs SWITCH VOLTAGE
12
8
9
0
1
2
3
4
5
6
7
8
9
10
11
12
VCOM (V)
FIGURE 20. ON-LEAKAGE vs SWITCH VOLTAGE
March 19, 2008
ISL54302
Typical Performance Curves
VLOGIC = 3V, TA = +25°C, VIH = 3V, VIL = 0V, Unless Otherwise Specified. (Continued)
5.0
5.0
VSS = -3V, VPLUS = 3V, VDD = 0V
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
-3
-2
-1
VSS = 0V, VPLUS = 5V, VDD = 3V
4.5
VCOM (nA)
VCOM (nA)
4.5
0
1
2
0.0
3
0
1
2
3
VCOM (V)
FIGURE 21. OFF-LEAKAGE vs SWITCH VOLTAGE
10
VSS = -3V, VPLUS = 7V, VDD = 0V
8
7
7
6
6
VCOM (nA)
VCOM (nA)
VSS = 0V, VPLUS = 7V, VDD = 3V
9
8
5
4
5
4
3
3
2
2
1
1
0
0
-3
-2
-1
0
1
2
3
4
5
6
7
0
1
2
3
4
VCOM (V)
VCOM (V)
FIGURE 23. OFF-LEAKAGE vs SWITCH VOLTAGE
7
VSS = 0V, VPLUS = 12V, VDD = 3V
9
8
7
7
6
6
VCOM (nA)
VCOM (nA)
6
10
VSS = -3V, VPLUS = 9V, VDD = 0V
8
5
4
5
4
3
3
2
2
1
1
0
5
FIGURE 24. OFF-LEAKAGE vs SWITCH VOLTAGE
10
9
5
FIGURE 22. OFF-LEAKAGE vs SWITCH VOLTAGE
10
9
4
VCOM (V)
0
-3
-2
-1
0
1
2
3
4
5
6
7
VCOM (V)
FIGURE 25. OFF-LEAKAGE vs SWITCH VOLTAGE
13
8
9
0
1
2
3
4
5
6
7
8
9
10
11
12
VCOM (V)
FIGURE 26. OFF-LEAKAGE vs SWITCH VOLTAGE
March 19, 2008
ISL54302
Typical Performance Curves
VLOGIC = 3V, TA = +25°C, VIH = 3V, VIL = 0V, Unless Otherwise Specified. (Continued)
6.0
6.0
VSS = -3V, VCOM = VPLUS - 1V, VDD = 0V
5.5
ICOM = 10mA
4.5
4.5
4.0
4.0
3.5
ICOM = 10mA
5.0
rON ()
rON ()
5.0
3.0
VSS = 0V, VCOM = VPLUS - 1V, VDD = 3V
5.5
+25°C
3.5
+25°C
3.0
2.5
2.5
+85°C
2.0
+85°C
2.0
-40°C
1.5
1.5
-40°C
1.0
3
1.0
4
5
6
7
8
9
3.0
4.5
6.0
7.5
10.5
12.0
FIGURE 28. ON-RESISTANCE vs SUPPLY VOLTAGE
FIGURE 27. ON-RESISTANCE vs SUPPLY VOLTAGE
17.0
2.00
VSS = -3V, VDD = 0V
1.94
VSS = -3V, VDD = 0V
16.5
+25°C
1.88
16.0
15.5
1.82
VPLUS (A)
+85°C
1.76
VIN (V)
9.0
VPLUS (V)
VPLUS (V)
1.70
1.64
-40°C
1.58
14.0
-40°C
13.5
13.0
1.46
12.5
12.0
1.40
2.7
+25°C
14.5
1.52
2.5
+85°C
15.0
2.9
3.1
3.3
3.5
3
4
5
6
7
8
9
VPLUS (V)
VPLUS (V)
FIGURE 29. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 30. DEVICE QUIESCENT CURRENT (VPLUS)
450
60
VPLUS = 9V, VSS = -3V, VDD = 0V
400
50
350
VPLUS = 9V, VSS = -3V, VDD = 0V
40
VPLUS = 12V, VSS = 0V,
VDD = 3V
250
200
VPLUS = 7V, VSS = 0V,
VDD = 3V
150
TIME (ns)
Q (pC)
300
30
20
VPLUS = 9V, VSS = 0V, VDD = 3V
100
10
50
0
-3 -2 -1
0
1
2
3
4
5 6
VCOM (V)
7
8
9
10 11 12
FIGURE 31. CHARGE INJECTION vs SWITCH VOLTAGE
14
0
-3
-2
-1
0
1
2
3
4
VCOM (V)
5
6
7
8
9
FIGURE 32. tON vs VCOM
March 19, 2008
ISL54302
Typical Performance Curves
VLOGIC = 3V, TA = +25°C, VIH = 3V, VIL = 0V, Unless Otherwise Specified. (Continued)
0
VPLUS = 9V, VSS = 0V, VDD = 3V
-10 VPLUS = 9V, VSS = -3V, VDD = 0V
RL = 50
-20
VPLUS = 9V, VSS = 0V, VDD = 3V
10 VPLUS = 9V, VSS = -3V, VDD = 0V
RL = 50
20
-30
30
OFF ISOLATION (dB)
CROSSTALK
0
-40
-50
-60
-70
-80
40
50
60
70
80
-90
90
-100
100
-110
1k
10k
100k
1M
10M
100M 500M
110
1k
10k
FREQUENCY (Hz)
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 33. CROSSTALK
NORMALIZED GAIN (dB)
100k
FIGURE 34. OFF-ISOLATION
VPLUS = 9V
0
VPLUS = 5V TO 9V, VSS = 0V, VDD = 3V
GAIN
-1
4
CS-LATCH
-2
VSS = 0V, VDD = 3V
-3
0
4
DATA = 1
-4
DATA = 0
0
SX-CRTL
-5
VSS = -3V, VDD = 0V
-6
4
-7
-8
0
RL = 50
VIN = 0.2VP-P to 2VP-P
1
SWITCH ON
SWITCH OFF
VOUT WITH VCOM = 3V
10
100
FREQUENCY (MHz)
FIGURE 35. FREQUENCY RESPONSE
15
600
40ms/DIV
FIGURE 36. TIMING
March 19, 2008
ISL54302
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
4.00
2.0
16X 0.50
A
B
16
6
PIN #1 INDEX AREA
20
6
PIN 1
INDEX AREA
1
4.00
15
2 .70 ± 0 . 15
11
(4X)
5
0.15
6
10
0.10 M C A B
4 20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
C
0 . 2 REF
5
( 20X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 20X 0 . 6)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
March 19, 2008
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