DATASHEET

ISL84684II
®
Data Sheet
November 3, 2005
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Dual SPDT Analog Switch
in Chipscale Package
The Intersil ISL84684II device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.8V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low RON (0.21Ω) and fast
switching speeds (tON = 43ns, tOFF = 27ns). The digital logic
input is 1.8V logic-compatible when using a single +1.8V to
4.5V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84684II is offered in a 2.00mm x 1.50mm chipscale
package, alleviating board space limitations. The 4x3 array of
solder balls are spaced with a 0.5mm ball pitch.
The ISL84684II is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multiplexer. The ISL84684II is pin
compatible with the MAX4684 and MAX4685.
TABLE 1. FEATURES AT A GLANCE
FN6190.0
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Pin Compatible Replacement for the MAX4684 and
MAX4685
• ON Resistance (RON)
- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.21Ω
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.14Ω
• RON Matching Between Channels, maximum . . . . . . 0.05Ω
• RON Flatness Across Signal Range, maximum . . . . . 0.03Ω
• Single Supply Operation . . . . . . . . . . . . . . . . +1.8V to +4.5V
• Low Power Consumption PD . . . . . . . . . . . . . . . . . <0.32µW
• Fast Switching Action (V+ = +2.7V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ns
• Guaranteed Break-before-Make
• 1.8V Logic Compatible
• Low I+ Current when VinH is not at the V+ Rail
• Available in 10 ball 4x3 Array Chipscale Package (2mm x
1.5mm)
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
ISL84684II
Number of Switches
2
SW
SPDT or 2-1 MUX
2.7V RON
0.21Ω
2.7V tON/tOFF
43ns/27ns
4.3V RON
0.14Ω
4.3V tON/tOFF
30ns/25ns
Package
10 ball, 2.0mm x 1.5mm
depopulated 4x3 array
Chipscale
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB451 “PCB Assembly Guidelines for
Intersil Wafer Level Chip Scale Package Devices”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84684II
Pinout
Ordering Information
(Note 1)
ISL84684II (CHIPSCALE)
TOP VIEW
PART NO.
GND
A1
NC2
C2
A2
IN2
COM1
C3
A3
COM2
NO1
C4
A4
NO2
NC1
C1
IN1
B1
B4
TEMP.
RANGE
PART
(°C)
MARKING
ISL84684IIZ-T 684Z
(Note)
PACKAGE
PKG.
DWG. #
W4x3.10A
-40 to 85 10 ball,
2.0mm x 1.5mm,
depopulated 4x3
array, Chipscale
Pb-free, Tape
and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
V+
NOTE:
1. B2 and B3 of the 4x3 array are not populated.
Truth Table
LOGIC
PIN NC1 and NC2
PIN NO1 and NO2
0
ON
OFF
1
OFF
ON
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V
Pin Descriptions
PIN
FUNCTION
V+
System Power Supply Input (+1.8V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
2
FN6190.0
November 3, 2005
ISL84684II
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD HBM rating (Per Mil-Std-883, Method 3015) . . . . . . . . . . ±2kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
10 Ball Chipscale Package . . . . . . . . . . . . . . . . . . .
91
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Soldering conditions (Note 4) . . . . . . . . . . . . . . . . . . per J-STD-020
Operating Conditions
Temperature Range
ISL84684II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. Permitted soldier profiles are limited to only those recommended in the industry standard specification, JEDEC J-STD-020. Preheating is
required. Hand or wave soldering is not allowed. See Technical Brief TB451.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 5, 7)
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 6)
MIN
TYP
(NOTE 6)
MAX
UNITS
Full
0
-
V+
V
25
-
0.21
0.5
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5, Note 9)
RON Matching Between Channels,
∆RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max RON (Note 9, Note 10)
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 8, Note 9)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
Full
-
-
0.5
Ω
25
-
0.05
0.06
Ω
Full
-
-
0.09
Ω
25
-
0.03
0.2
Ω
Full
-
-
0.2
Ω
25
-40
-
40
nA
Full
-150
-
150
nA
25
-40
-
40
nA
Full
-150
-
150
nA
25
-
43
50
ns
Full
-
-
60
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 9)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 9)
25
-
27
30
ns
Full
-
-
40
ns
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 3, Note 9)
Full
2
12
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
200
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
56
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-105
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω
25
-
0.012
-
%
f = 1kHz, VCOM = 2VP-P, RL = 32Ω
25
-
0.009
-
%
25
-
0.006
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
f = 1kHz, VCOM = 2VP-P, RL = 600Ω
25
-
140
-
pF
COM ON Capacitance, CCOM(ON)
25
-
355
-
pF
3
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
FN6190.0
November 3, 2005
ISL84684II
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 5, 7)
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 6)
MIN
TYP
(NOTE 6)
MAX
UNITS
Full
1.8
-
4.5
V
25
-
5
20
nA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
Full
-
-
70
nA
25
-
1.6
4
µA
Full
-
-
8
µA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
VIN = 0V or V+ (Note 9)
NOTES:
5. VIN = input voltage to perform proper function.
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
9. Guaranteed but not tested.
10. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max
RON value.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 5, 7),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 6)
MIN
TYP
(NOTE 6)
MAX
UNITS
Full
0
-
V+
V
25
-
0.14
-
Ω
Full
-
0.17
-
Ω
25
-
0.05
-
Ω
Full
-
0.06
-
Ω
25
-
0.03
-
Ω
Full
-
0.04
-
Ω
25
-
0.9
-
µA
Full
-
4
-
µA
25
-
0.9
-
µA
Full
-
4
-
µA
25
-
30
40
ns
Full
-
-
45
ns
25
-
25
35
ns
Full
-
-
40
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
RON Matching Between Channels,
∆RON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max RON (Note 10)
RON Flatness, RFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 8)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 9)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 9)
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 3, Note 9)
Full
2
4
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
260
-
pC
4
FN6190.0
November 3, 2005
ISL84684II
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 5, 7),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 6)
MIN
TYP
(NOTE 6)
MAX
UNITS
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
56
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-105
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
140
-
pF
COM ON Capacitance, CCOM(ON)
25
-
355
-
pF
Full
1.8
-
4.5
V
25
-
5
20
nA
Full
-
-
70
nA
25
-
1.6
4
µA
Full
-
-
8
µA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+ (Note 9)
Test Circuits and Waveforms
V+
LOGIC
INPUT
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
NO or NC
COM
IN
VOUT
90%
SWITCH
OUTPUT
V+
tr < 12ns
tf < 12ns
90%
LOGIC
INPUT
GND
RL
50Ω
CL
35pF
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(NO or NC) R + R
L
( ON )
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
5
FN6190.0
November 3, 2005
ISL84684II
Test Circuits and Waveforms (Continued)
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO or NC
∆VOUT
VG
GND
IN
CL
V+
ON
ON
LOGIC
INPUT
OFF
LOGIC
INPUT
0V
Q = ∆VOUT x CL
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V+
NO
VNX
LOGIC
INPUT
C
VOUT
COM
NC
RL
50Ω
0V
IN
SWITCH
OUTPUT
VOUT
90%
0V
CL
35pF
GND
LOGIC
INPUT
tD
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
V+
C
SIGNAL
GENERATOR
C
RON = V1/100mA
NO or NC
NO or NC
VNX
IN
0V or V+
100mA
COM
ANALYZER
FIGURE 4. OFF ISOLATION TEST CIRCUIT
6
0V or V+
COM
GND
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
IN
V1
Repeat test for all switches.
FIGURE 5. RON TEST CIRCUIT
FN6190.0
November 3, 2005
ISL84684II
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
0V or V+
IN
0V or V+
IMPEDANCE
ANALYZER
NC or NO
COM
ANALYZER
N.C.
COM
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL84684II is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.8V to 4.5V supply with low onresistance (0.21Ω) and high speed operation (tON = 43ns,
tOFF = 27ns). The device is especially well suited for
portable battery powered equipment due to its low operating
supply voltage (1.8V), low power consumption (0.32µW max),
low leakage currents (150nA max), and the tiny chipscale
package. The ultra low on-resistance and RON flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provide additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
7
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch. Connecting schottky
diodes to the signal pins as shown in Figure 8 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNX
OPTIONAL
SCHOTTKY
DIODE
VCOM
GND
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL84684II construction is typical of most single supply
CMOS analog switches, in that they have two supply pins;
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84684II 5V
maximum supply voltage provides plenty of room for the
10% tolerance of a 4.3V supply, as well as room for
overshoot and noise spikes.
FN6190.0
November 3, 2005
ISL84684II
The minimum recommended supply voltage is 1.8V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 1.8V to 4.5V (see Figure 16). At 4.5V
the VIH level is about 1.3V. This is still below the 1.8V CMOS
guaranteed high output minimum level of 1.4V, but noise
margin is reduced.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation. The ISL84684II has been
designed to minimize the supply current whenever the digital
input voltage is not driven to the supply rails (0V to V+). For
example driving the device with 2.85V logic (0V to 2.85V)
while operating with a 4.2V supply the device draws only
1.6µA of current.
High-Frequency Performance
In 50Ω systems, the signal response is reasonably flat even
past 10MHz with a -3dB bandwidth of 80MHz (see
Figure 17). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 18 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 56dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
8
FN6190.0
November 3, 2005
ISL84684II
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
0.21
0.24
ICOM = 100mA
0.23
V+ = 2.7V
0.22
0.19
0.21
0.18
RON (Ω)
0.2
RON (Ω)
V+ = 4.3V
ICOM = 100mA
0.2
V+ = 3V
0.19
0.18
0.17
85°C
0.16
0.15
25°C
0.14
V+ = 3.6V
0.16
0.17
0.13
0.15
V+ = 4.3V
0.14
V+ = 4.5V
-40°C
0.12
0.11
0.13
0
1
2
3
4
0
5
1
2
4
5
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.25
2
V+ = 2.7V
ICOM = 100mA
0.24
0.23
3
VCOM (V)
VCOM (V)
V+ = 1.8V
ICOM = 100mA
85°C
1.5
0.22
-40°C
25°C
0.2
RON (Ω)
RON (Ω)
0.21
0.19
1
25°C
-40°C
0.18
0.17
0.5
85°C
0.16
0.15
0
0.14
0
0.5
1
1.5
VCOM (V)
2
2.5
0
3
0.5
1
1.5
2
VCOM (V)
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
120
250
110
100
200
90
80
tOFF (ns)
tON (ns)
150
100
70
60
50
40
50
20
85°C, 25°C, -40°C
0
1.5
85°C, 25°C
30
2
2.5
3
V+ (V)
3.5
4
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE
9
4.5
10
1.5
-40°C
2
2.5
3
3.5
4
4.5
V+ (V)
FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6190.0
November 3, 2005
ISL84684II
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
400
1.4
300
1.3
200
100
VINH AND VINL (V)
V+ = 3V
0
-100
-200
-300
1.1
0.9
0.7
-500
0.6
0
1
2
3
4
VINL
0.8
-400
-600
VINH
1
0.5
5
1.5
2
2.5
VCOM (V)
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
3
V+ (V)
3.5
4
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
GAIN
0
-3
PHASE
20
40
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1
10
100
FREQUENCY (MHz)
FIGURE 17. FREQUENCY RESPONSE
500
PHASE (DEGREES)
0
0.1
10
V+ = 3V
CROSSTALK (dB)
NORMALIZED GAIN (dB)
-10
V+ = 3V
-6
4.5
-20
20
-30
30
-40
40
-50
50
ISOLATION
-60
60
-70
70
-80
80
CROSSTALK
-90
90
-100
-110
1k
OFF ISOLATION (dB)
Q (pC)
1.2
V+ = 4.3V
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 18. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
10
FN6190.0
November 3, 2005
ISL84684II
Wafer Level Chip Scale Package (WLCSP)
W4x3.10A
4X3 ARRAY 10 BALL WAFER LEVEL CHIP SCALE PACKAGE
E
PIN 1 ID
SYMBOL
MILLIMETERS
NOTES
A
0.64 +0.05 -0.10
-
A1
0.29 ±0.02
-
D
TOP VIEW
bb
A2
A
A1
b
A2
0.35 REF.
-
b
θ 0.37 ±0.03
-
bb
θ 0.30 REF.
-
D
1.50 ±0.05
-
D1
1.00 BASIC
-
E
2.00 ±0.05
-
E1
1.50 BASIC
-
e
0.50 BASIC
-
SD
0.00 BASIC
-
SE
0.25 BASIC
-
N
10
3
Rev. 1 10/05
SIDE VIEW
NOTES:
1. Dimensions are in Millimeters.
2. Dimensioning and tolerancing conform to ASME 14.5M-1994.
E1
3. Symbol “N” is the actual number of solder balls.
e
SE
C
B
SD
D1
A
1
2
3
4
b
BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6190.0
November 3, 2005
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