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TERSIL
1-888-IN
Numerically Controlled Oscillator/
Modulator
HSP45116A
May 7, 2007
FN4156.4
Features
• NCO and CMAC on One Chip
The Intersil HSP45116A combines a high performance
quadrature numerically controlled oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
HSP45116A is divided into three main sections. The Phase/
Frequency Control Section (PFCS) and the Sine/Cosine
Section together form a complex NCO. The CMAC multiplies
the output of the Sine/ Cosine Section with an external
complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.013Hz at 52MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.
• 52MHz Version
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.013Hz Tuning Resolution at 52MHz
• Programmable Rounding Option
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal. The bit
position and widths for the outputs of CMAC and Complex
Accumulator (ACC) are programmable.
Ordering Information
PART NUMBER
HSP45116AVC-52
PART MARKING
HSP45116AVC-52
HSP45116AVC-52Z (Note) HSP45116AVC-52Z
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
0 to +70
160 Ld MQFP (28mmx28mm)
Q160.28x28
0 to +70
160 Ld MQFP (28mmx28mm) (Pb-free)
Q160.28x28
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas LLC 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HSP45116A
Block Diagram
VECTOR INPUT
R
I
MICROPROCESSOR
INTERFACE
INDIVIDUAL
CONTROL SIGNALS
PHASE/
FREQUENCY
CONTROL
SECTION
SINE/
COSINE
ARGUMENT
SIN
SINE/
COSINE
SECTION
COS
CMAC
R
I
VECTOR OUTPUT
2
FN4156.4
May 7, 2007
HSP45116A
Pinout
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
NC
VCC
IMIN1
GND
IMIN2
IMIN3
IMIN4
IMIN5
IMIN6
IMIN7
IMIN8
IMIN9
IMIN10
IMIN11
IMIN12
VCC
IMIN13
GND
IMIN14
IMIN15
IMIN16
IMIN17
IMIN18
IO19
IO18
IO17
IO16
IO15
VCC
GND
IO14
IO13
IO12
IO11
IO10
GND
VCC
IO9
IO8
IO7
HSP45116A
(160 LD MQFP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
GND
IO6
IO5
IO4
IO3
GND
IO2
IO1
VCC
IO0
RO19
GND
RO18
RO17
RO16
RO15
RO14
VCC
RO13
RO12
RO11
GND
RO10
RO9
VCC
RO8
RO7
GND
RO6
RO5
RO4
RO3
VCC
RO2
RO1
RO0
GND
DET1
DET0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CLROFR
ENCFREG
ENPHAC
ENTIREG
ENI
MODPI/2PI
CS
GND
CLK
VCC
AD1
AD0
WR
C15
C14
C13
C12
C11
C10
C9
C8
GND
C7
C6
C5
C4
C3
C2
C1
C0
OUTMUX1
OUTMUX0
GND
OER
RND
OEREXT
OEIEXT
OEI
PACO
NC
IMIN0
RIN18
RIN17
RIN16
RIN15
RIN14
GND
RIN13
RIN12
RIN11
RIN10
RIN9
RIN8
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2
GND
RIN1
VCC
RIN0
SH1
SH0
ACC
ENPHREG
ENOFREG
PEAK
RBYTILD
BINFMT
GND
TICO
VCC
MOD1
MOD0
PACI
LOAD
PMSEL
NC
3
FN4156.4
May 7, 2007
HSP45116A
Pin Descriptions
NAME
NUMBER
TYPE
DESCRIPTION
VCC
22, 34, 50, 87, 95,
102, 111, 124, 132,
145, 159
-
+5V Power supply input.
GND
7, 20, 32, 48, 62, 73,
83, 92, 98, 108,
114, 119, 125, 131,
143, 157
-
Power supply ground input.
C0-15
54-61, 63-70
I
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
AD0-1
51, 52
I
Address pins for selecting destination of C0-15 data. AD1 is the MSB.
CS
47
I
Chip select (active low).
WR
53
I
Write Enable. Data is clocked into the input register selected by AD0-1 on the rising edge of WR
when the CS line is low.
CLK
49
I
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
ENPHREG
27
I
Phase Register Enable (active low). Registered on chip by CLK. When active low, after being
clocked onto chip, ENPHREG enables the clocking of data into the Phase Register.
ENOFREG
28
I
Frequency Offset Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of frequency offset data into the frequency
offset register.
ENCFREG
42
I
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the Center Frequency Register.
ENPHAC
43
I
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the Phase Accumulator Register.
ENTIREG
44
I
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENTIREG enables clocking of data into the Time Accumulator Register.
ENI
45
I
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
MODPI/2PI
46
I
Modulo /2 Select. When low, the Sine and Cosine ROMs are addressed modulo 2 (360
degrees). When high, the most significant address bit is held low so that the ROMs are addressed
modulo  (180 degrees). This input is registered on chip by clock. This control pin was included
for FFT processing.
CLROFR
41
I
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the Frequency Offset Register
to the frequency adder. New data can still be clocked into the Frequency Offset Register;
CLROFR does not affect the contents of the register.
LOAD
38
I
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path
in the phase accumulator without clearing the Phase Accumulator Register.
MOD0-1
35, 36
I
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90, 180,
or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of the phase
control path are set to zero.
These bits are loaded into the Phase Register when ENPHREG is low.
4
MOD1
MOD0
0
0
PHASE SHIFT (DEGREES)
0
0
1
90
1
0
270
1
1
180
FN4156.4
May 7, 2007
HSP45116A
Pin Descriptions
(Continued)
NAME
NUMBER
TYPE
DESCRIPTION
PMSEL
39
I
Phase Modulation Select Line. This line determines the source of the data clocked into the Phase
Register. When high, the Phase Control Register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the least
significant 14 bits are set to zero. This control is registered by CLK.
RBYTILD
30
I
ROM Bypass, Timer Load (active low). Registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16 bit phase adder output and lower 16 bits of the phase accumulator go directly
to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the Timer
Accumulator Register by zeroing the feedback in the accumulator.
PACI
37
I
Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one in addition to the values in the Phase Accumulator Register and frequency
adder.
PACO
79
O
Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has
been reached.
TICO
33
O
Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time out
control events such as synchronizing register clocking to data timing.
RIN0-18
2-6, 8-19, 21, 23
I
Real Input Data Bus. RIN18 is the MSB. This is the external real component into the complex
multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is asserted. Two’s
complement.
IMIN0-18
1, 138-142, 144,
146-156, 158
I
Imaginary Input Data Bus. IMIN18 is the MSB. This is the external imaginary component into the
complex multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is
asserted. Two’s complement.
SH0-1
24, 25
I
Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex
multiplier. The shift controls are common to the shifters on both of the busses.
ACC
26
I
SH1
SH0
SELECTED BITS
0
0
RIN0-15, IMIN0-15
0
1
RIN1-16, IMIN1-16
1
0
RIN2-17, IMIN2-17
1
1
RIN3-18, IMIN3-18
Accumulate/Dump Control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled. When
low, the feedback in the accumulators is zeroed to cause the accumulators to load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.
BINFMT
31
I
This input is used to convert the two’s complement output to offset binary (unsigned) for
applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two’s complement representation. This input is registered by CLK.
PEAK
29
I
This input enables the peak detect feature of the block floating point detector. When high, the
maximum bit growth in the Output Holding Registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted, the block floating point detector output will track the maximum
growth in the holding registers, including the data in the Holding Registers at the time that PEAK
is activated.
5
FN4156.4
May 7, 2007
HSP45116A
Pin Descriptions
(Continued)
NAME
NUMBER
TYPE
OUTMUX0-1
71, 72
I
DESCRIPTION
These inputs select the data to be output on RO0-19 and IO0-19.
OUT OUT
MUX MUX
0
1
RO16-19
RO0-15
IO16-19
IO0-15
0
0
Real CMAC Real CMAC Imag CMAC Imag CMAC
31-34
15-30
31-34
15-30
0
1
Real CMAC 0, Real
Imag CMAC 0, Imag
31-34
CMAC 0-14 31-34
CMAC 0-14
1
0
Real ACC
16-19
Real ACC
0-15
Imag ACC
16-19
Imag ACC
0-15
1
1
Reserved
Reserved
Reserved
Reserved
RO0-19
84-86, 88-91, 93,
94, 96, 97, 99-101,
103-107, 109
O
Real Output Data Bus. R19 is the MSB. These three-state outputs are controlled by OER and
OEREXT. OUTMUX0-1 select the data output on the bus.
IO0-19
110, 112, 113,
115-118, 121-123,
126-130, 133-137
O
Imaginary Output Data Bus. I19 is the MSB. These three-state outputs are controlled by OEI and
OEIEXT. OUTMUX0-1 select the data output on the bus.
DET0-1
81, 82
O
These output pins indicate the number of bits of growth in the accumulators. While PEAK is low,
these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary
accumulator holding registers and bits 30-33 of the real and imaginary CMAC Holding Registers.
The bits indicate the largest growth of the four registers.
DET 1
DET 0
NUMBER OF BITS
OF GROWTH ABOVE 2o
0
0
0
0
1
1
1
0
2
1
1
3
OER
74
I
Three-state control for bits RO0-15. Outputs are enabled when the line is low.
OEREXT
76
I
Three-state control for bits RO16-19. Outputs are enabled when the line is low.
OEI
78
I
Three-state control for bits IO0-15. Outputs are enabled when the line is low.
OEIEXT
77
I
Three-state control for bits IO16-19. Outputs are enabled when the line is low.
RND
75
I
Round Enable. This input enables rounding of the output data precision from 9 to 20 bits. This
input is active “low”. This input must be tied either high or low.
6
FN4156.4
May 7, 2007
HSP45116A
Functional Description
The Numerically Controlled Oscillator/Modulator (NCOM)
produces a digital complex sinusoid waveform whose
amplitude, phase and frequency are controlled by a set of
input command words. When used as a Numerically
Controlled Oscillator (NCO), it generates 16-bit sine and
cosine vectors at a maximum sample rate of 40MHz. The
NCOM can be preprogrammed to produce a constant (CW)
sine and cosine output for Direct Digital Synthesis (DDS)
applications. Alternatively, the phase and frequency inputs
can be updated in real time to produce a FM, PSK, FSK, or
MSK modulated waveform. The Complex Multiplier/
Accumulator (CMAC) can be used to multiply this waveform
by an input signal for AM and QAM signals. By stepping the
phase input, the output of the ROM becomes an FFT twiddle
factor; when data is input to the Vector Inputs (see Block
Diagram), the NCOM calculates an FFT butterfly.
As shown in the Block Diagram, the NCOM consists of
three parts: Phase and Frequency Control Section (PFCS),
Sine/Cosine Generator, and CMAC. The PFCS stores the
phase and frequency inputs and uses them to calculate the
phase angle of a rotating complex vector. The Sine/Cosine
Generator performs a lookup on this phase and outputs the
appropriate values for the sine and cosine. The sine and
cosine form one set of inputs to the CMAC, which multiplies
them by the input vector to form the modulated output.
The outputs of the CMAC and ACC can be rounded to
different bit widths.
Phase and Frequency Control Section
The phase and frequency of the internally generated sine
and cosine are controlled by the PFCS (Figure 1). The PFCS
generates a 32-bit word that represents the current phase of
the sine and cosine waves being generated: The Sine/
Cosine Argument. Stepping this phase angle from 0 through
full scale (232 - 1) corresponds to the phase angle of a
sinusoid starting at 0o and advancing around the unit circle
counterclockwise. The PFCS automatically increments the
phase by a preprogrammed amount on every rising edge of
the external clock. The value of the phase step (which is the
sum of the Center and Offset Frequency Registers) is:
32
Signal Frequency
Phase Step = ----------------------------------------------  2
Clock Frequency
where Signal Frequency is a 2’s complement number. The
sign bit will set the output vector notation for Upper Sideband
(USB) or lower Sideband (LSB) applications.
The PFCS is divided into two sections: The Phase
Accumulator uses the data on C0-15 to compute the phase
angle, that is the input to the Sine/Cosine Section (Sine/
Cosine Argument); the Time Accumulator supplies a pulse to
mark the passage of a preprogrammed period of time.
7
The Phase Accumulator and Time Accumulator work on the
same principle: a 32-bit word is added to the contents of a
32-bit accumulator register every clock cycle; when the sum
causes the adder to overflow, the accumulation continues
with the 32 bits of the adder going into the Accumulator
Register. The overflow bit is used as an output to indicate
the timing of the accumulation overflows. In the Time
Accumulator, the overflow bit generates TICO, the Time
Accumulator carry out (which is the only output of the Time
Accumulator). In the Phase Accumulator, the overflow is
inverted to generate the Phase Accumulator Carry Out,
PACO.
The output of the Phase Accumulator goes to the Phase
Adder, which adds an offset to the top 16 bits of the phase.
This 32-bit number forms the argument of the sine and
cosine, which is passed to the Sine/Cosine Generator.
Both accumulators are loaded 16 bits at a time over the
C0-15 bus. Data on C0-15 is loaded into one of the three
input registers when CS and WR are low. The data in the
Most Significant Input Register and Least Significant Input
Register forms a 32-bit word that is the input to the Center
Frequency Register, Offset Frequency Register and Time
Accumulator. These registers are loaded by enabling the
proper register enable signal; for example, to load the
Center Frequency Register, the data is loaded into the LS
and MS Input Registers, and ENCFREG is set to zero; the
next rising edge of CLK will pass the registered version of
ENCFREG, R.ENCFREG, to the clock enable of the Center
Frequency Register; this register then gets loaded on the
following rising edge of CLK. The contents of the Input
Registers will be continuously loaded into the Center
Frequency Register as long as R.ENCFREG is low.
The Phase Register is loaded in a similar manner. Assuming
PMSEL is high, the contents of the Phase Input Register is
loaded into the Phase Register on every rising clock edge
that R.ENPHREG is low. If PMSEL is low, MOD0-1 supply
the two most significant bits into the Phase Register (MOD1
is the MSB) and the least significant 14 bits are loaded with
0. MOD0-1 and are used to generate a Quad Phase Shift
Keying (QPSK) signal (Table 2).
TABLE 1. AD0-1 DECODING
AD1
AD0
CS
WR
FUNCTION
0
0
0

Load least significant bits
of frequency input.
0
1
0

Load most significant bits
of frequency input.
1
0
0

Load phase register.
1
1
X
X
Reserved.
X
X
1
X
No Operation.
FN4156.4
May 7, 2007
HSP45116A
RIN(18:0)
2
MSEN
>
R
E
G
AD(1:0)
>
DECODER
2
CS
WR
FREQUENCY
ADDER
CENTER FREQUENCY
REGISTER
16
32
LS INPUT
REGISTER
R
E
G
16
R.PMSEL
MS INPUT
REGISTER
16
>
R
E
G
32
CLK
>
SIN/COS
ARGUMENT
R
E
G
A
D
D
E
R
OFFSET
FREQUENCY
REGISTER
16
R.ENCFREG
32
LSEN
CLK
>
R
E
G
32
20
32
1
>
R.ENPHREG
CLK
MUX
PHEN
16
R
E
G
16
PHASE
32
16
SINE/COSINE
GENERATOR
16
CLK
>
SIN 16
R
E
G
16
COS
0
C(15:0)
PHASE
REGISTER
14
0
0
MUX
ENCODE
PHASE
INPUT
REGISTER
1
MOD(1:0)
0
32
R.ENOFREG
32
R.CLROFR
R.PMSEL
PMSEL
ENPHREG
ENCFREG
ENOFREG
CLROFR
PHASE
ACCUMULATOR
R.ENPHREG
>
PHASE
ADDER
PHASE
ACCUMULATOR
ADDER
>
32
0
32
MSB
16
CLK
>
R
E
G
32
CLK
1
MUX
PHASE
ACCUMULATOR
REGISTER
A
D
D
E
R
CLK
0
A
D
D
E
R
0
32
1
RBYTILD
ENTIREG
CLK
CLK
PACO
R
E
G
MUX
LOAD
ENPHAC
MODPI/2PI
R.ENCFREG
R.ENOFREG
R.CLROFR
R.LOAD
R.ENPHAC
R.MODPI/2PI
R.RBYTILD
R.ENTIREG
0
R
E
G
>
R
E
G
15
16 MSBs
R.ENPHAC
16 LSBs
R.LOAD
32
PACI
PACI
R.MODPI/2PI
R
E
G
>
CLK
R.ENTIREG
>
R
E
G
32
32
CLK
32
>
CLK
>
R
E
G
TIME ACCUMULATOR
TICO
32
1
TIME
INCREMENT
R
E
G
MUX
32
CARRY OUT
TIME
ACCUMULATOR
REGISTER
0
0
CLK
OEI
OEIEXT
OER
OEREXT
RND
OUTMUX(1:0)
ADDER
SH(1:0)
ENI
ACC
PEAK
BINFMT
R.RBYTILD
R.SH(1:0)
R.ENI
R.ACC
R.PEAK
R.BINFMT
R.SH(1:0)
R.ENI
R.ACC
R.PEAK
R.BINFMT
TICO
PACO
FIGURE 1. HSP45116A BLOCK DIAGRAM
8
FN4156.4
May 7, 2007
HSP45116A
>
CLK
R
E
R
E
G
>G
CLK
19
19
R.ENI
RIN0-18
R.SH(1:0)
IMIN0-18
SHIFTER
SHIFTER
16
16
CLK
>
CLK
16
MUX
COS
0
MUX
0
ROUND
>
<
1
>
CLK
MUX
>
CLK
REG
ADDER
R1.ACC
1
CLK
0
>
REG
>
REG
MUX
1
0
REG
<
CLK
0
0
ROUND
REG
CMAC
ACCUMULATOR
CLK
>
REG
REG
<
CLK
CLK
REG
<
CLK
20
35
35
<
REG
ADDER
CLK
MUX
0
COMPLEX
ACCUMULATOR
33
CLK
REG
ADDER
1
CLK
REG
REG
ADDER
0
>
CLK
REG
R1.ACC
<
>
CLK
REG
COMPLEX
MULTIPLIER
R
E
G
33
RND
R2.ACC
>
CLK
R.RBYTILD
REG
>G
CLK
COS 16
0
SIN
>
R
E
1
SIN
CLK
0
R.PEAK
20
R.PEAK
R.ACC
1
OUTMUX(1:0)
SEE TABLE 4
MUX
R.BINFMT
R.SH(1:0)
R.ENI
OEI
OEIEXT
OER
3
FMT
0
GROWTH
DETECT
16
OUTMUX(1:0)
SEE TABLE 4
R.BINFMT
MUX
3
FMT
16
R.ENI
OEREXT
OUTMUX(1:0)
MUX
R.SH(1:0)
PHASE
REG
CLK
4
>
REG
16
4
16
RND
RO(19-16)
RO(15:0)
DET(1:0)
IO(19-16)
IO(15:0)
FIGURE 1. HSP45116A BLOCK DIAGRAM (Continued)
9
FN4156.4
May 7, 2007
HSP45116A
The sum of the values in Center and Offset Frequency
Registers corresponds to the desired phase increment
(modulo 232) from one clock to the next. For example,
loading both registers with zero will cause the Phase
Accumulator to add zero to its current output; the output of
the PFCS will remain at its current value; i.e., the output of
the NCOM will be a DC signal. If a hexadecimal 00000001 is
loaded into the Center Frequency Control Register, the
output of the PFCS will increment by one after every clock.
This will step through every location in the Sine/Cosine
Generator, so that the output will be the lowest frequency
above DC that can be generated by the NCOM, i.e., the
clock frequency divided by 232. If the input to the Center
Frequency Control Register is hex 80000000, the PFCS will
step through the Generator with half of the maximum step
size, so that frequency of the output waveform will be half of
the sample rate.
The operation of the Offset Frequency Control Register is
identical to that of the Center Frequency Control Register;
having two separate registers allows the user to generate an
FM signal by loading the carrier frequency in the Center
Frequency Control Register and updating the Offset
Frequency Control Register with the value of the frequency
offset - the difference between the carrier frequency and the
frequency of the output signal. A logic low on CLROFR
disables the output of the Offset Frequency Register without
clearing the contents of the register.
TABLE 2. MOD0-1 DECODE
MOD1
MOD0
PHASE SHIFT (DEGREES)
0
0
0
0
1
90
1
0
270
1
1
180
Initializing the Phase Accumulator Register is done by putting
a low on the LOAD line. This zeroes the feedback path to the
accumulator, so that the register is loaded with the current
value of the phase increment summer on the next clock.
The final phase value going to the Generator can be
adjusted using MODPI/2PI to force the range of the phase to
be 0o to 180o (modulo ) or 0o to 360o (modulo 2). Modulo
2 is the mode used for modulation, demodulation, direct
digital synthesis, etc. Modulo  is used to calculate FFTs.
This is explained in greater detail in the Applications Section.
10
The Phase Register adds an offset to the output of the
Phase Accumulator. Since the Phase Register is only 16
bits, it is added to the top 16 bits of the Phase Accumulator.
The Time Accumulator consists of a register which is
incremented on every clock. The amount by which it
increments is loaded into the Input Registers and is latched
into the Time Accumulator Register on rising edges of CLK
while ENTIREG is low. The output of the Time Accumulator
is the accumulator carry out, TICO. TICO can be used as a
timer to enable the periodic sampling of the output of the
NCOM. The number programmed into this register equals
232 x CLK period/desired time interval. TICO is disabled and
its phase is initialized by zeroing the feedback path of the
accumulator with RBYTILD.
Sine/Cosine Section
The Sine/Cosine Section (Figure 2) converts the output of
the PFCS into the appropriate values for the sine and
cosine. It takes the most significant 20 bits of the PFCS
output and passes them through a look up table to form the
16-bit sine and cosine inputs to the CMAC.
32
16
SIN/COS
ARGUMENT
The Phase Accumulator consists of registers and adders
that compute the value of the current phase at every clock. It
has three inputs: Center Frequency, which corresponds to
the carrier frequency of a signal; Offset Frequency, which is
the deviation from the Center Frequency; and Phase, which
is a 16-bit number that is added to the current phase for PSK
modulation schemes. These three values are used by the
Phase Accumulator and Phase Adder to form the phase of
the internally generated sine and cosine.
MUX
32
20
16
SINE/COSINE
GENERATOR 16
REG 16
16
SIN
COS
16
CLK
CLK
R.RBYTILD
FIGURE 2. SINE/COSINE SECTION
The 20-bit word maps into 2 radians so that the angular
resolution is 2/220. An address of zero corresponds to
0 radians and an address of hex FFFFF corresponds to
2- (2/220) radians. The outputs of the Generator Section
are 2’s complement sine and cosine values. The sine and
cosine outputs range from hexadecimal 8001, which
represents negative full scale to 7FFF, which represents
positive full scale. Note that the normal range for two’s
complement numbers is 8000 to 7FFF; the output range of
the SIN/COS generator is scaled by one so that it is
symmetric about 0.
The sine and cosine values are computed to reduce the
amount of ROM needed. The magnitude of the error in the
computed value of the complex vector is less than -90.2dB.
The error in the sine or cosine alone is approximately
2dB better.
If RBYTILD is low, the output of the PFCS goes directly to
the inputs of the CMAC. If the real and imaginary inputs of
the CMAC are programmed to hex 7FFF and 0 respectively,
then the output of the PFCS will appear on output bits 0
FN4156.4
May 7, 2007
HSP45116A
through 15 of the NCOM, with the output multiplexers set to
bring out the most significant bits of the CMAC output
(OUTMUX = 00). The most significant 16 bits out of the
PFCS appears on IOUT0-15 and the least significant bits
come out on ROUT0-15.
Complex Multiplier/Accumulator
The CMAC (Figure 1) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations
necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier
and its associated accumulator; the rest of the circuitry
in this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and imaginary inputs RIN and IIN. The two vectors are
combined in the following manner:
ROUT = COS x RIN - SIN x IIN
IOUT = COS x IIN + SIN x RIN
RIN and IIN are latched into the Input Registers and passed
through the shift stages. Clocking of the Input Registers is
enabled with a low on ENI. The amount of shift on the
latched data is programmed with SH0-1 (Table 3). The
output of the shifters is sent to the CMAC and the auxiliary
accumulators.
TABLE 3. INPUT SHIFT SELECTION
SH1
SH0
SELECTED BITS
0
0
RIN0-15, IMIN0-15
0
1
RIN1-16, IMIN1-16
1
0
RIN2-17, IMIN2-17
1
1
RIN3-18, IMIN3-18
The 33-bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the Accumulator Section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set of
real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.
TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT OUT
MUX MUX
0
1
RO16-19
RO0-15
IO16-19
IO0-15
0
0
Real CMAC Real CMAC Imag CMAC Imag CMAC
31-34
15-30
31-34
15-30
0
1
Real CMAC 0, Real
Imag CMAC 0, Imag
31-34
CMAC 0-14 31-34
CMAC 0-14
1
0
Real ACC
16-19
Real ACC
0-15
Imag ACC
16-19
Imag ACC
0-15
1
1
Reserved
Reserved
Reserved
Reserved
The Complex Accumulator duplicates the accumulator in the
CMAC. The input comes from the data shifters, and its 20-bit
complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUX0-1
determines whether the accumulator output appears on
ROUT and IOUT.
The Growth Detect circuitry outputs a two bit value that
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DET0-1, is encoded as
shown in Table 5. If PEAK is low, the highest value of
DET0-1 is latched in the Growth Detect Output Register.
The relative weighting of the bits at the inputs and outputs of
the CMAC is shown in Figure 3. Note that the binary point of
the sine, cosine, RIN and IIN is to the right of the most
significant bit, while the binary point of RO and IO is to the
right of the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOMs for FFT applications.
TABLE 5. GROWTH ENCODING
DET 1
DET 0
NUMBER OF BITS
OF GROWTH ABOVE 2o
0
0
0
0
1
1
1
0
2
1
1
3
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUX0- 1 lines (Table 4). BINFMT controls whether the
output of the Multiplexer is presented in two’s complement or
unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19
for unsigned output, while BINFMT = 1 selects two’s
complement.
11
FN4156.4
May 7, 2007
HSP45116A
SIN/COS INPUT
S
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-20 . 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15

Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, IIN)
SH = 00
S
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-20 . 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15

Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 00
MSB
S
19
18
17
16
-24
23
22
21
LSB
15
14
20 . 2-1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15

Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 01
MSB
LSB
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-24
23
22
21
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
0
COMPLEX ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 10
MSB
S
19
18
17
16
-24
23
22
21
LSB
15
14
20 . 2-1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15

Radix Point
FIGURE 3. BIT WEIGHTING
12
FN4156.4
May 7, 2007
HSP45116A
Rounding
The operation of the HSP45116A is identical to the
HSP45116 with the exception of a programmable rounding
option added for the data outputs. The added functionality
was achieved by using one of the HSP45116’s reserved
Configuration Registers to specify rounding precision and
replacing a VCC pin with a round enable (RND) input. When
RND is “high”, rounding is disabled, and the HSP45116A
functions as a pin-for-pin equivalent of the HSP45116. When
RND is active “low” rounding is enabled. The RND input
replaces VCC on PIN 75 of the 160 Lead MQFP package as
seen in the Pinout Diagram.
The Round Control Register is loaded by placing the round
control value on C15-0, setting AD1-0 = 11, setting CS = 0,
and forcing a low to high transition on the WR input. The
rounding operation is determined by the least significant 8
bits loaded into the Control Register as shown in Table 6.
The least significant four bits (C3-0) loaded into the register
govern rounding of the real and imaginary outputs of the
Complex Accumulator (ACC). The next more significant four
bits (C7-4) govern the rounding of the complex outputs of the
complex multiply accumulator (CMAC). The real and
imaginary outputs from the CMAC or ACC are rounded to
the same precision. The rounding is perform by adding a
“one” to the bit position below the least significant bit desired
in the output. For example, for a configuration that rounds to
the most significant 20 bits of the CMAC output, a “one”
would be added to bit position 2-14 (See Figure 3 for output
bit weightings).
TABLE 6. ROUNDING CONTROL
ROUND CONTROL REGISTER
C15-8
C7-4
C3-0
UNUSED
CMAC
ROUNDING
ACC
ROUNDING
XXXXXXXX
0000
0000
No Rounding
XXXXXXXX
0001
0001
CMAC outputs rounded to most significant 20 bits, bit positions -24 to 2-15
ACC outputs rounded to most significant 20 bits, bit positions -24 to 2-15
XXXXXXXX
0010
0010
CMAC outputs rounded to most significant 19 bits, bit positions -24 to 2-14
ACC outputs rounded to most significant 19 bits, bit positions -24 to 2-14
XXXXXXXX
0011
0011
CMAC outputs rounded to most significant 18 bits, bit positions -24 to 2-13
ACC outputs rounded to most significant 18 bits, bit positions -24 to 2-13
XXXXXXXX
0100
0100
CMAC outputs rounded to most significant 17 bits, bit positions -24 to 2-12
ACC outputs rounded to most significant 17 bits, bit positions -24 to 2-12
XXXXXXXX
0101
0101
CMAC outputs rounded to most significant 16 bits, bit positions -24 to 2-11
ACC outputs rounded to most significant 16 bits, bit positions -24 to 2-11
XXXXXXXX
0110
0110
CMAC outputs rounded to most significant 15 bits, bit positions -24 to 2-10
ACC outputs rounded to most significant 15 bits, bit positions -24 to 2-10
XXXXXXXX
0111
0111
CMAC outputs rounded to most significant 14 bits, bit positions -24 to 2-9
ACC outputs rounded to most significant 14 bits, bit positions -24 to 2-9
XXXXXXXX
1000
1000
CMAC outputs rounded to most significant 13 bits, bit positions -24 to 2-8
ACC outputs rounded to most significant 13 bits, bit positions -24 to 2-8
XXXXXXXX
1001
1001
CMAC outputs rounded to most significant 12 bits, bit positions -24 to 2-7
ACC outputs rounded to most significant 12 bits, bit positions -24 to 2-7
XXXXXXXX
1010
1010
CMAC outputs rounded to most significant 11 bits, bit positions -24 to 2-6
ACC outputs rounded to most significant 11 bits, bit positions -24 to 2-6
XXXXXXXX
1011
1011
CMAC outputs rounded to most significant 10 bits, bit positions -24 to 2-5
ACC outputs rounded to most significant 10 bits, bit positions -24 to 2-5
XXXXXXXX
1100
1100
CMAC outputs rounded to most significant 9 bits, bit positions -24 to 2-4
ACC outputs rounded to most significant 9 bits, bit positions -24 to 2-4
XXXXXXXX
1101-1111
1101-1111
13
ROUNDING OPERATION
Undefined
FN4156.4
May 7, 2007
HSP45116A
RIN IMIN
16
16
NCOM
32
SINE/COSINE
GENERATOR
The NCOM can be used for Amplitude, Phase and
Frequency modulation, as well as in variations and
combinations of these techniques, such as QAM. It is most
effective in applications requiring multiplication of a rotating
complex sinusoid by an external vector. These include AM
and QAM modulators and digital receivers. The NCOM
implements AM and QAM modulation on a single chip, and
is a element in demodulation, where it performs complex
down conversion. It can be combined with the Intersil
HSP43220 Decimating Digital Filter to form the front end of a
digital receiver.
Phase/Frequency Control Section, the frequency tuning
resolution equals the clock frequency divided by 232. For
example, a 25MHz clock gives a tuning resolution of
0.006Hz.
CENTER
FREQUENCY
Applications
PFCS
CLK
16
CMAC
16
Modulation/Demodulation
PFCS
SINE/COSINE
GENERATOR
CENTER
FREQUENCY
CLK
32
RIN
SIN
CMAC
16
RO
D/A
HSP45116A
NCOM
FIGURE 4. AMPLITUDE MODULATION
By replacing the real input with a complex vector, a similar
setup can generate QAM signals (Figure 5). In this case, the
carrier frequency is loaded into the Center Frequency
Register as before, but the modulating vector now carries
both amplitude and phase information. Since the input vector
and the internally generated sine and cosine waves are both
16 bits, the number of states is only limited by the
characteristics of the transmission medium and by the
analog electronics in the transmitter and receiver.
The phase and amplitude resolution for the Sine/Cosine
Section (16-bit output), delivers a spectral purity of greater
than 90dBc. This means that the unwanted spectral
components due to phase uncertainty (phase noise) will be
greater than 90dB below the desired output (dBc, decibels
below the carrier). With a 32-bit phase accumulator in the
HSP43220
DDF
COS (wt)
LO
14
LO
FIGURE 5. QUADRATURE AMPLITUDE MODULATION (QAM)
XMTR
16
D/A
NCOM
MODULATED OUTPUT
RO
The NCOM also works with the HSP43220 Decimating
Digital Filter to implement down conversion and low pass
filtering in a digital receiver (Figure 6). The NCOM performs
complex down conversion on the wideband input signal by
multiplying the input vector and the internally generated
complex sinusoid. The resulting signal has components at
twice the center frequency and at DC. Two HSP43220s, one
each on the real and imaginary outputs of the HSP45116A,
perform low pass filtering and decimation on the down
converted data, resulting in a complex baseband signal.
SIGNAL INPUT
16
16
XMTR
Figure 4 shows a block diagram of an AM modulator. In this
example, the phase increment for the carrier frequency is
loaded into the Center Frequency Register, and the
modulating input is clocked into the real input of the CMAC,
with the imaginary input set to 0. The modulated output is
obtained at the real output of the CMAC. With a sixteen bit,
two’s complement signal input, the output will be a 16-bit real
number, on ROUT0-15 (with OUTMUX = 00).
SAMPLED
INPUT
DATA
SIN (wt)
INPUT
0
10MHz
NCOM
OUTPUT
0
20MHz
DDF
OUTPUT
0
FIGURE 6. CHANNELIZED RECEIVER CHIP SET
FN4156.4
May 7, 2007
HSP45116A
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
JA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38.0
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26,000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
VCC = 5.0V 5%, TA = 0°C to +70°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Power Supply Current
ICCOP
VCC = Max, CLK Frequency 52.6MHz
Notes 2, 3
-
184
mA
Standby Power Supply Current
ICCSB
VCC = Max, Outputs Not Loaded
-
500
A
Input Leakage Current
II
VCC = Max, Input = 0V or VCC
-10
10
A
Output Leakage Current
IO
VCC = Max, Input = 0V or VCC
-10
10
A
Logical One Input Voltage
VIH
VCC = Max
2.0
-
V
Logical Zero Input Voltage
VIL
VCC = Min
-
0.8
V
Logical One Input Voltage: CLK
VIHC
VCC = Max
3.0
-
V
Logical One Output Voltage
VOH
IOH = -5mA, VCC = Min
2.6
-
V
Logical Zero Output Voltage
VOL
IOL = 5mA, VCC = Min
-
0.4
V
Input Capacitance
CIN
CLK Frequency 1MHz
All measurements referenced to GND. 
TA = +25°C, Note 4
-
10
pF
-
10
pF
Output Capacitance
COUT
NOTES:
2. Power supply current is proportional to frequency. Typical rating is 3.5mA/MHz.
3. Output load per test circuit and CL = 40pF.
4. Not tested, but characterized at initial design and at major process/design changes.
AC Electrical Specifications
VCC = 5.0V 5%, TA = 0°C to +70°C (Note 5)
52.6MHz (-52)
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
CLK Period
tCP
19
-
ns
CLK High
tCH
7
-
ns
CLK Low
tCL
7
-
ns
WR Low
tWL
7
-
ns
WR High
tWH
7
-
ns
Setup Time AD0-1, CS to WR
tAWS
10
-
ns
Hold Time AD0-1, CS from WR
tAWH
0
-
ns
Setup Time C0-15 to WR
tCWS
10
-
ns
Hold Time C0-15 from WR
tCWH
0
-
ns
15
FN4156.4
May 7, 2007
HSP45116A
AC Electrical Specifications
VCC = 5.0V 5%, TA = 0°C to +70°C (Note 5) (Continued)
52.6MHz (-52)
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
Setup Time WR to CLK
tWC
7
10
-
ns
Setup Time MOD0-1 to CLK
tMCS
10
-
ns
Hold Time MOD0-1 from CLK
tMCH
0
-
ns
Setup Time PACI to CLK
tPCS
10
-
ns
Hold Time PACI from CLK
tPCH
0
-
ns
Setup Time ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD to
CLK
tECS
10
-
ns
Hold Time ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK
tECH
0
-
ns
Setup Time RIN0-18, IMIN0-18 to CLK
tDS
10
-
ns
Hold Time RIN0-18, IMIN0-18 from CLK
tDH
0
-
ns
CLK to Output Delay RO0-19, IO0-19
tDO
-
12
ns
tDEO
-
12
ns
CLK to Output Delay PACO
tPO
-
12
ns
CLK to Output Delay TICO
tTO
-
12
ns
Output Enable Time OER, OEI, OEREXT, OEIEXT
tOE
-
8
ns
Output Enable Time OUTMUX0-1
tMD
-
14
ns
Output Disable Time
tOD
6
-
8
ns
Output Rise, Fall Time
tRF
6
-
4
ns
CLK to Output Delay DET0-1
NOTES:
5. AC tests performed with CL = 40pF, IOL = 2.0mA, and IOH = -0.4mA. Input reference level for CLK = 2.0V, all other inputs 1.5V. Test
VIH = 3.0V, VIHC = 4.0V, VIL = 0V; VOH 1.5V, VOL 1.5V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG or ENTIREG is active. WR is always asynchronous when RND
is active.
AC Test Load Circuit
DUT
S1
CL (NOTE)
SWITCH S1 OPEN FOR ICCSB AND ICCOP
IOH

1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
16
FN4156.4
May 7, 2007
HSP45116A
Waveforms
tCP
tCH
tCL
CLK
tMCH
tMCS
MOD0-1
tPCH
tPCS
PACI
tECH
tECS
CONTROL
INPUTS
tDH
tDS
RIN0-19
IIN0-19
tDO
ROUT0-19
IOUT0-19
tDEO
DET0-1
tPO
PACO
tTO
TICO
FIGURE 7. INPUT AND OUTPUT TIMING
tWC
CLK
tWL
WR
tWH
tAWS
tAWH
tAWS
tAWH
CS
AD0-1
tCWS
tCWH
C0-15
FIGURE 8. CONTROL BUS TIMING
17
FN4156.4
May 7, 2007
HSP45116A
Waveforms
OER
OEI
OEREXT
OEIEXT
RO0-19
IO0-19
(Continued)
1.5V
tOE
HIGH
IMPEDANCE
OUTMUX0-1
1.5V
tOD
tMD
1.7V
1.3V
RO0-19
HIGH
IMPEDANCE
IO0-19
FIGURE 9. OUTPUT ENABLE, DISABLE TIMING
FIGURE 10. MULTIPLEXER TIMING
2.0V
0.8V
tRF
tRF
FIGURE 11. OUTPUT RISE AND FALL TIMES
18
FN4156.4
May 7, 2007
HSP45116A
Metric Plastic Quad Flatpack Packages (MQFP)
Q160.28x28 (JEDEC MS-022DD-1 ISSUE B)
D
160 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.076
0.003
-C-
12o-16o
0.40
0.016 MIN
0.20
M
0.008
C A-B S
0o MIN
A2 A1
0o-7o
L
MIN
MAX
MIN
MAX
NOTES
A
-
0.161
-
4.10
-
A1
0.010
-
0.25
-
-
A2
0.126
0.142
3.20
3.60
-
B
0.009
0.015
0.22
0.38
6
B1
0.009
0.013
0.22
0.33
-
D
1.223
1.233
31.08
31.32
3
D1
1.097
1.107
27.88
28.12
4, 5
E
1.224
1.232
31.10
31.30
3
E1
1.098
1.106
27.90
28.10
4, 5
L
0.029
0.040
0.73
1.03
N
160
160
e
0.026 BSC
0.65 BSC
7
Rev. 1 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
b
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
b1
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
BASE METAL
WITH PLATING
SYMBOL
D S
0.13/0.17
0.005/0.007
12o-16o
MILLIMETERS
0.13/0.23
0.005/0.009
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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19
FN4156.4
May 7, 2007
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