DATASHEET

TM
HSP45314
File Number
4820.3
CommLinkTM Direct Digital Synthesizer
Features
The 14-bit HSP45314 provides a complete Direct Digital
Synthesizer (DDS) system in a single 48-pin LQFP package.
A 48-bit Programmable Carrier NCO (numerically controlled
oscillator) and a high speed 14-bit DAC (digital to analog
converter) are integrated into a stand alone DDS.
• 125MSPS Output Sample Rate with 5V Digital Supply
The DDS accepts 48-bit center and offset frequency control
information via a parallel processor interface. Modulation
control is provided by 3 external pins. The PH0 and PH1 pins
select phase offsets of 0, 90, 180 and 270 degrees, while the
ENOFR pin enables or zeros the offset frequency word to
the phase accumulator.
The parallel processor interface has an 8-bit write-only data
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe
(WR), and a Write Enable (WE). The processor can update
all registers simultaneously by loading a set of master
registers, then transfer all master registers to the slave
registers by asserting the UPDATE pin.
Block Diagram
• 100MSPS Output Sample Rate with 3.3V Digital Supply
• 14-bit DAC with Internal Reference
• Parallel Control Interface for Fast Tuning (50MSPS Control
Register Write Rate)
• 48-bit Programmable Frequency Control
• Small 48-pin LQFP package
Applications
• Programmable Local Oscillator
• FSK Modulation
• Direct Digital Synthesis
• Clock Generation
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PHASE
ACCUM.
48 LQFP
PKG. NO.
Q48.7X7A
Pinout
+
48-PIN LQFP (Q48.7X7A
TOP VIEW
ININ+
∑
UPDATE
MODULATION
CONTROL
ENOFR
PH(1:0)
-40 to 85
PACKAGE
C3
C4
C5
C6
C7
DVDD
WR
DGND
WE
NC
A0
A1
WR
WE
SLAVE
C(7:0)
A(3:0)
COMPOUT
HSP45314VI
MASTER
COMP1
COMP2
SINE
WAVE
ROM
RESET
CLK
14 BIT
DAC
IOUTA
IOUTB
INT
REF
REFIO
REFLO
C2
C1
C0
ENOFR
DGND
CLK
DVDD
RESET
UPDATE
COMPOUT
REFLO
REFIO
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
HSP45314
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
A2
A3
PH0
PH1
DGND
DVDD
DGND
DGND
DGND
DGND
DVDD
DGND
FSADJ
COMP1
AGND
AGND
IOUTB
IOUTA
COMP2
AVDD
AGND
IN+
INAGND
[ /Title
(HSP4
5314)
/Subject
(CommLink
Direct
Digital
Synthesizer)
/Autho
r ()
/Keywords
(Intersil
Corporation,
semiconductor,
DDS,
Direct
Digital
Synthesis,
Direct
Digital
NS
ESIG
D
W
R NE
UCT
D FO E PROD
E
D
MEN
ITUT
COM SUBST 5314
E
R
January 2001
NOTData
IBLE See ISL
SSheet
POS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
CommLink™ is a trademark of Intersil Corporation.
HSP45314
Typical Application Circuit (Sinewave Generation)
WRITE CLOCK
WRITE ENABLE
PH1:PH0 BUS
µPROCESSOR/
A3:A0 BUS
C7:C0 BUS
C3
C4
C5
C6
C7
DVDD
WR
DGND
WE
NC
A0
A1
FPGA/CPLD
DVPP
0.1µF
DVPP
0.1µF
DVPP
0.1µF
FSADJ
COMP1
AGND
AGND
IOUTB
IOUTA
COMP2
AVDD
AGND
IN+
INAGND
0.1µF
AVPP
0.1µF
0.1µF
RSET
AVPP
2kΩ
0.1µF
50Ω 50Ω
(IOUTA) ANALOG OUTPUT
FERRITE
BEAD
DVPP (DIGITAL POWER PLANE)
+
10µH
10µF
0.1µF
1µF
+5V POWER SOURCE
FERRITE
BEAD
AVPP (ANALOG POWER PLANE)
+
10µF
2
10µH
0.1µF
1µF
3
CLOCK
SOURCE
A2
A3
PH0
PH1
DGND
DVDD
DGND
DGND
DGND
DGND
DVDD
DGND
SIGNAL
PROCESSING
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
HSP45314
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
C2
C1
C0
ENOFR
DGND
CLK
DVDD
RESET
UPDATE
COMPOUT
REFLO
REFIO
HSP45314
Functional Description
Parallel Interface
The HSP45314 is an NCO with an integrated 14-bit DAC
designed to run in excess of 125MSPS. The NCO is a 16-bit
output design, which is rounded to 14 bits for input to the
DAC. The frequency control is the sum of a 48-bit center
frequency word and a 48-bit offset frequency word. The two
components are added modulo 48 bits with the alignment
shown in Table 1. Each of the two terms can be zeroed
independently (via the microprocessor interface for the
center frequency and via the ENOFR pin for the offset
frequency term).
The processor interface is an 8-bit parallel write only
interface. The interface consists of 8 data bits (C7:C0), four
address pins (A3:A0), a Write Strobe (WR), and a Write
Enable (WE). The interface is a master/slave type. The
processor interface loads a set of master registers. The
contents of the master set of registers is then transferred to
a slave set of registers by asserting a pin (UPDATE). This
allows all of the bits of the frequency control to be updated
simultaneously.
Frequency Generation
The output frequency of the part is determined by the
summation of two registers:
fOUT = fCLK x ( (CF + OF) mod (248))/ (248),
where CF is the Center Frequency register and OF is the
Offset Frequency register.
With a 125MSPS clock rate, the center frequency can be
programmed to
(125 x 106)/(248) = 0.4 µHz resolution.
The addition of the frequency control words can be
interpreted as two’s complement if convenient. For example,
if the center frequency is set to 4000...00h and the offset
frequency set to C000..00h, the programmed center
frequency would be fCLK/4 and the programmed offset
frequency -fCLK/4. The sum would be 10000..00h, but
because only the lower 48 bits are retained, the effective
frequency would be 0. In reality, frequencies above
8000...00h alias below fCLK/2 (the output of the part is real),
so the MSB is only provided as a convenience for two’s
complement calculations.
The frequency control of the NCO is the change in phase per
clock period or dφ/dt. This is integrated by the phase
accumulator to obtain frequency. The most significant 24
bits of phase are then mapped to 16 bits of amplitude in a
sine look-up table function. The range of dφ/dt is 0 to 1 with
1 equaling 360 degrees or (2 x pi) per clock period. The
phase accumulator output is also 0 to 1 with 1 equaling 360
degrees. The operations are modulo 48 bits because the
MSB (bit 47) aligns with the most significant address bit of
the sine ROM and the ROM contains one cycle of a sinusoid.
The MSB is weighted at 180 degrees. Full scale is 360
degrees minus 1 LSB and the phase then rolls over to 0
degrees for the next cycle of the sinusoid.
The rate which the user writes (WR) to these registers does
not have to be the same rate as the DDS clock rate (the rate
of the NCO and DAC; pin CLK). It is expected that most
applications will have a slower register write rate than the
DDS clock rate. It takes 6 WR cycles at the write rate plus
another 11 CLK cycles at the DDS rate to write and obtain a
new frequency, assuming that all registers are rewritten and
the UPDATE pin is always active. If the UPDATE pin is not
active until after the new word has been written, it takes 14
CLK cycles, rather than 11. For cases which require the
output to be updated with all of the new frequency
information present, it is necessary that the UPDATE be
inactive until after all of the new frequency word has been
written to the device. See the Timing Diagrams for more
information. The parallel registers can be written to again
immediately after the 11th or 14th CLK cycle, again
depending the state of UPDATE. If the application does not
need 48 bits (all 6 registers) of frequency information, then
the output frequency can be changed more quickly. For
example, if only 32 bits of frequency information are needed
and it is desired that the output be updated all at once, then
it takes 4 WR cycles, then the assertion low of the UPDATE
pin, plus another 14 CLK cycles at the DDS rate to write and
update a new frequency.
The timing is the same whether writing to the center or offset
frequency registers. For faster frequency update, consider
the ENOFR (Enable Offset Frequency Register) option.
Once the values have been written to the center and offset
frequency registers, the user can enable and disable the
offset frequency register, which is added to the center
frequency value when enabled. The ENOFR pin has a
latency of 14 CLK cycles, but simplifies the interface
because the only pin that has to be toggled is the ENOFR
pin.
TABLE 1. FREQUENCY CONTROL BIT ALIGNMENTS
Bits
4444 4444
3333 3333
3322 2222
2222 1111
1111 1100
0000 0000
Individual Bit Alignment
7654 3210
9876 5432
1098 7654
3210 9876
5432 1098
7654 3210
Phase Accumulator
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Center Frequency
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Offset Frequency
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
3
HSP45314
There are three control pins provided for phase and
frequency control. The PH0 and PH1 pins select phase
offsets of 0, 90, 180, and 270 degrees and can be used for
low speed, unfiltered BPSK or QPSK modulation. These
pins can also be used for providing sine/cosine when using
two HSP45314s together as quadrature local oscillators.
The ENOFR pin enables or zeros the offset frequency word
to the phase accumulator and can be used for FSK or MSK
modulation. These control pins and the UPDATE pin are
passed through special cells to minimize the probability of
meta-stability.
If the internal reference is used, VFSADJ will equal
approximately 1.2V (pin 13). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT (Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
Analog Output
Comparator
VOUT = IOUT X RLOAD.
Reset
A comparator is provided for square wave output generation.
The user can take the DDS analog output, filter it, and then
send it back into the comparator. A square wave will be
generated at the comparator output (COMPOUT pin) at an
amplitude level that is dependent on the digital power supply
used (DVDD). The comparator was designed to operate at
speeds comparable to the DDS output frequency range
(approximately 0-50MHz). It is not intended for low jitter
applications. The comparator has a sleep mode that is
activated by connecting both inputs (IN- and IN+) to the
analog power supply plane. This will save approximately
4mA of current (as shown in the Typical Application Circuit).
If the comparator is not used, leave the COMPOUT pin
floating.
DAC Voltage Reference
The internal voltage reference for the DAC has a nominal
value of +1.2V with a ±60ppm/ oC drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(11) selects the reference. The internal reference can be
selected if pin 11 is tied low (ground). If an external
reference is desired, then pin 11 should be tied high (the
analog supply voltage) and the external reference driven into
REFIO, pin 12. The full scale output current of the converter
is a function of the voltage reference used and the value of
RSET. IOUT should be within the 2mA to 20mA range,
though operation below 2mA is possible, with performance
degradation.
4
3
A RESET pin is available which resets all registers to their
defaults. In order to reset the part, the user must take the
RESET pin low, allow at least one CLK rising edge, and then
take the RESET pin high again. The latency from the RESET
pin going high until the output reflects the reset is 11 CLK
cycles. See the register description table in the back of the
datasheet for the default states of all bits in all addresses.
After RESET goes high, one rising edge of CLK is required
before the control registers can be written to again.
IOUTA and IOUTB are complementary current outputs. They
are generated by a 14-bit digital-to-analog converter (DAC)
that is capable of running at the full 125MSPS rate. The DDS
clock also clocks the DAC. The sum of the two output
currents is always equal to the full scale output current
minus one LSB. If single ended use is desired, a load
resistor can be used to convert the output current to a
voltage. It is recommended that the unused output be either
grounded or equally terminated. The voltage developed at
the output must not violate the output voltage compliance
range of -1.0V to 1.25V. RLOAD (the impedance loading
each current output) should be chosen so that the desired
output voltage is produced in conjunction with the output full
scale current. If a known line impedance is to be driven, then
the output load resistor should be chosen to match this
impedance. The output voltage equation is:
These outputs can be used in a differential-to-single-ended
arrangement. This is typically done to achieve better
harmonic rejection. Because of a mismatch in IOUTA and
IOUTB, the transformer does not improve the harmonic
rejection. However, it can provide voltage gain without
adding distortion. The SFDR measurements in this data
sheet were performed with a 1:1 transformer on the output of
the DDS (see Figure 1). With the center tap grounded, the
output swing of pins 17 and 18 will be biased at zero volts.
The loading as shown in Figure 1 will result in a 500mVP-P
signal at the output of the transformer if the full scale output
current of the DAC is set to 20mA.
R EQ IS THE IMPEDANCE
LOADING EACH OUTPUT
50Ω
PIN 17
IOUTB
100Ω
PIN 18
HSP45314
VOUT = (2 x IOUT x REQ)VPP
50Ω
IOUTA
50Ω
50Ω REPRESENTS THE
SPECTRUM ANALYZER
FIGURE 1.
VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. Allowing the
center tap to float will result in identical transformer output,
however the output pins of the DAC will have positive DC
offset, which could limit the voltage swing available due to
the output voltage compliance range. The 50Ω load on the
output of the transformer represents the load at the end of a
SIGNAL
PROCESSING
Control Pins
HSP45314
‘transmission line’, typically a spectrum analyzer,
oscilloscope, or the next function in the signal chain. The
necessity to have a 50Ω impedance looking back into the
transformer is negated if the DDS is only driving a short
trace. The output voltage compliance range does limit the
impedance that is loading the DDS output.
Ground Plane Considerations
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Pins 11 through 24 are analog pins,
while all of the others are digital.
Noise Reduction Considerations
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the power supply pins, AVDD
and DVDD. Also, the layout should be designed using
separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Power Supplies
The DDS will provide the best SFDR (Spurious Free
Dynamic Range) when using +5V analog and +5V digital
power supply. The analog supply must be +5V (±10%). The
digital supply can be either a +3.3V (±10%) or a +5V (±10%)
supply, or anything in between. The DDS is rated to
125MSPS when using a +5V digital supply. The maximum
clock is 100MSPS when using a +3.3V digital supply.
5
Improving SFDR
As was previously noted, using +5V power supplies provides
the best SFDR. Under some clock and output frequency
combinations, particularly when the fCLK/fOUT ratio is less
than 4, the user can improve SFDR even further by
connecting the COMP2 pin (19) of the DDS to the analog
power supply. The digital supply must be +5V if this option is
explored. Improvements as much as 6dBc in the SFDR-toNyquist measurement were seen in the lab.
FSK Modulation
BFSK (Binary Frequency Shift Keying) can be done by
enabling and disabling the offset frequency (ENOFR pin).
Once the offset frequency has been written once, it can be
toggled with a latency of 14 CLK cycles.
M-ary FSK or GFSK can be done by continuously loading in
new frequency words.
Quadrature Local Oscillators
Two HSP45314s can be used as sine/cosine generators for
quadrature local oscillator applications. It is important to note
that the Phase Accumulator feedback needs to be zeroed in
both devices if it is desired that both DDSs restart with a
known phase, which is determined by the use of the phase
control pins, PH1 and PH0. To zero the phase accumulator,
pull bit 5 of address 13 low and then high again at the same
time in both devices.
HSP45314
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +5.5V
Grounds, AGND To DGND. . . . . . . . . . . . . . . . . . . . . -0.3V To +0.3V
Digital Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA,
TA = 25oC for All Typical Values
HSP45314
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
14
-
-
Bits
DAC CHARACTERISTICS
DAC Resolution
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-5
+2.5
+6
LSB
Differential Linearity Error, DNL
(Note 7)
-2
+1.5
+4
LSB
Offset Error, IOS
(Note 7)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/oC
Full Scale Gain Error
With Internal Reference (Notes 2, 7)
-10
±1
+10
% FSR
Full Scale Gain Drift
With Internal Reference (Note 7)
-
±50
-
ppm
FSR/oC
Full Scale Output Current
(Note 3)
2
-
20
mA
Output Voltage Compliance Range
(Note 3, 7)
-1.0
-
1.25
V
Maximum Clock Rate, fCLK
+5V DVDD , +5V AVDD (Note 3)
125
-
-
MSPS
Maximum Clock Rate, fCLK
+3.3V DVDD , +5V AVDD (Note 3)
100
-
-
MSPS
Output Settling Time, (tSETT)
±0.05% (±8 LSB) (Note 7)
-
35
-
ns
Output Rise Time
Full Scale Step
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
-
25
-
pF
IOUTFS = 20mA
-
50
-
pA/√Hz
IOUTFS = 2mA
-
30
-
pA/√Hz
DAC DYNAMIC CHARACTERISTICS
Output Capacitance
Output Noise
6
HSP45314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA,
TA = 25oC for All Typical Values (Continued)
HSP45314
TA = -40oC TO 85oC
MIN
TYP
MAX
UNITS
fCLK = 100MSPS, fOUT = 20MHz, 5MHz Span
-
93
-
dBc
fCLK = 100MSPS, fOUT = 5MHz, 8MHz Span
-
93
-
dBc
fCLK = 50MSPS, fOUT = 5MHz, 8MHz Span
-
93
-
dBc
fCLK = 125MSPS, fOUT = 40.4MHz
-
40
-
dBc
fCLK = 125MSPS, fOUT = 10.1MHz
57
63
-
dBc
fCLK = 125MSPS, fOUT = 5.02MHz
-
72
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz
-
40
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz
-
49
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz
-
72
-
dBc
fCLK = 100MSPS, fOUT = 2.51MHz
-
73
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz
-
45
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz
-
68
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz
-
72
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz
-
71
-
dBc
fCLK = 25MSPS, fOUT = 1.0MHz
-
72
-
dBc
1.13
1.2
1.28
V
Internal Reference Voltage Drift
-
±60
-
ppm/oC
Internal Reference Output Current
Sink/Source Capability
-
±0.1
-
µA
Reference Input Impedance
-
1
-
MΩ
Reference Input Multiplying Bandwidth (Note 7)
-
1.4
-
MHz
PARAMETER
TEST CONDITIONS
AC CHARACTERISTICS
Spurious Free Dynamic Range,
SFDR Within a Window (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2) (Notes 4, 7)
DAC REFERENCE VOLTAGE
Internal Reference Voltage, VFSADJ
Pin 13 Voltage with Internal Reference
DIGITAL INPUTS
Input Logic High Voltage with
5V Digital Supply, VIH
(Note 3)
3.5
5
-
V
Input Logic High Voltage with
3V Digital Supply, VIH
(Note 3)
2.0
3
-
V
Input Logic Low Voltage with
5V Digital Supply, VIL
(Note 3)
-
0
1.3
V
Input Logic Low Voltage with
3V Digital Supply, VIL
(Note 3)
-
0
0.8
V
Input Logic Current, IIH
-10
-
+10
µA
Input Logic Current, IIL
-10
-
+10
µA
-
4
-
pF
Digital Input Capacitance, CIN
7
HSP45314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA,
TA = 25oC for All Typical Values (Continued)
HSP45314
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS
Maximum Clock Rate, fCLK
+5V DVDD , +5V AVDD (Note 3)
125
-
-
MSPS
Maximum Clock Rate, fCLK
+3.3V DVDD , +5V AVDD (Note 3)
100
-
-
MSPS
CLK Pulse Width, tCW
CLK (Note 3)
5
-
-
ns
Maximum Parallel Write Rate
Rate of WR
50
-
-
MSPS
WR Pulse Width, tWW
(Note 3)
5
-
-
ns
Data Setup Time, tDS
Between DATA and WR (Note 3)
10
-
-
ns
Data Hold Time, tDH
Between DATA and WR (Note 3)
0
-
-
ns
Address Setup Time, tAS
Between ADDR and WR (Note 3)
12
-
-
ns
Address Hold Time, tAH
Between ADDR and WR (Note 3)
0
-
-
ns
UPDATE Pulse Width, tUW
(Note 3)
5
-
-
ns
UPDATE Setup Time, tUS
Between UPDATE and CLK (Note 3)
2
-
-
ns
UPDATE Hold Time, tUH
Between UPDATE and CLK (Note 3)
4
-
-
ns
UPDATE Latency, tUL
After UPDATE, before analog output change, if asserted after
writing to the control registers
-
14
-
Clock
Cycles
UPDATE Latency, tUL
After UPDATE, before analog output change, if asserted before
writing to the control registers
-
11
-
Clock
Cycles
Phase Pulse Width, tPW
PH(1:0) (Note 3)
5
-
-
ns
Phase Setup Time, tPS
Between PH(1:0) change and CLK (Note 3)
2
-
-
ns
Phase Hold Time, tPH
Between PH(1:0) change and CLK (Note 3)
4
-
-
ns
Phase Latency, tPL
Between PH(1:0) change and analog output change
-
12
-
Clock
Cycles
ENOFR Pulse Width, tEW
ENOFR (Note 3)
5
-
-
ns
ENOFR Setup Time, tES
Between ENOFR and CLK (Note 3)
2
-
-
ns
ENOFR Hold Time, tEH
Between ENOFR and CLK (Note 3)
4
-
-
ns
ENOFR Latency, tEL
After ENOFR, before analog output change
-
14
-
Clock
Cycles
Write Enable Pulse Width, tWR
WE (Note 3)
5
-
-
ns
Write Enable Setup Time, tWS
Between WE and WR (Note 3)
2
-
-
ns
Write Enable Hold Time, tWH
Between WE and WR (Note 3)
4
-
-
ns
RESET Pulse Width, tRW
RESET (Note 3)
5
-
-
ns
RESET Setup Time, tRS
Between RESET and CLK
-
2
-
ns
RESET Latency to Output, tRL
After RESET, before analog output reflects reset values
-
11
-
Clock
Cycles
RESET Latency to Write, tRE
After RESET, before the control registers can be written to
-
1
-
Clock
Cycles
8
HSP45314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA,
TA = 25oC for All Typical Values (Continued)
HSP45314
TA = -40oC TO 85oC
MIN
TYP
MAX
UNITS
Input Capacitance
-
4
-
pF
Input Resistance
-
>1
-
MΩ
Input Current
-
1
-
µA
-
4.0
3.75
V
Minimum Input Voltage, Peak-to-Peak (Dependent on noise)
-
0.1
-
Vpp
Propagation Delay, High to Low
(Note 8)
-
6
-
ns
Propagation Delay, Low to High
(Note 8)
-
5
-
ns
Output Rise Time
(Note 8)
-
1.5
-
ns
Output Fall Time
(Note 8)
-
1.3
-
ns
Output High Voltage, VOH
IOH = -4mA
2.6
-
-
V
Output Low Voltage, VOL
IOL = +4mA
-
-
0.4
V
Maximum Output Toggle Rate
High Z Load (~1MΩ)
-
100
-
MHz
AVDD (Analog) Power Supply
4.5
5.0
5.5
V
DVDD (Digital) Power Supply
3.0
3.3
5.5
V
5V, IOUTFS = 20mA (Note 10)
-
25
30
mA
5V, IOUTFS = 2mA
-
7
-
mA
5V (Notes 5, 10)
-
90
100
mA
3.3V (Notes 6, 9)
-
50
55
mA
AVDD = 5V, DVDD = 3.3V, IOUTFS = 20mA (Notes 6, 9)
-
290
363
mW
AVDD = 5V, DVDD = 5V, IOUTFS = 20mA (Notes 5, 10)
-
625
715
mW
-0.2
-
+0.2
% FSR/V
PARAMETER
TEST CONDITIONS
COMPARATOR CHARACTERISTICS
Maximum Input Voltage Allowed
(Excluding comparator sleep mode)
POWER SUPPLY CHARACTERISTICS
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)
Power Dissipation
Power Supply Rejection
Single 5V Supply (Note 7)
NOTES:
2. Gain Error for the DAC is measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA);
ideally the ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering.
5. Measured with the clock at 125MSPS and the output frequency at 10MHz.
6. Measured with the clock at 100MSPS and the output frequency at 10MHz.
7. See “Definition of Specifications”.
8. 50MHz, High Z Load (~1MΩ), 15pF capacitance, (IN- = 0.5Vpp), (IN+ = 0.25VDC).
9. For maximum value, 5.5V AVDD and 3.6V DVDD are used.
10. For maximum value, 5.5V AVDD and 5.5V DVDD are used.
9
HSP45314
Definition of Specifications
Differential Non-Linearity, DNL, is the measure of the step
size output deviation from code to code. Ideally the step size
should be 1LSB. A DNL specification of 1LSB or less
guarantees monotonicity.
Integral Non-Linearity, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Full Scale Gain Drift, is measured by setting the DAC
inputs to be all logic high (all 1s) and measuring the output
voltage through a known resistance as the temperature is
varied from TMIN to TMAX . It is defined as the maximum
deviation from the value measured at room temperature to
the value measured at either TMIN or TMAX . The units are
ppm of FSR (Full Scale Range) per oC.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the DAC output current and the full scale adjust
current (through RSET).
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX .
The units are ppm per oC.
Offset Drift, is measured by setting the DAC inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance as the temperature is varied from TMIN to
TMAX . It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX . The units are ppm of FSR (Full Scale
Range) per degree oC.
10
Offset Error, is measured by setting the DAC inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance. Offset error is defined as the maximum
deviation of the output current from a value of 0mA.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement is done by switching quarter scale.
Termination impedance was 25Ω due to the parallel
resistance of the 50Ω loading on the output and the
oscilloscope’s 50Ω input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed at either IOUTA or
IOUTB does not violate the compliance range.
Power Supply Rejection, is measured using a single power
supply. The supply’s nominal +5V is varied ±10% and the
change in the DAC full scale output current is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs to the DAC set to all 1s. The frequency
is increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
HSP45314
Timing Diagrams
tWS
WE
tAS
tWH
tAH
ADDR
A0
A1
A2
A3
A4
A5
DON’T CARE
DATA
W0
W1
W2
W3
W4
W5
DON’T CARE
tDS
tDH
WRITE
DON’T CARE
6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD
CLK
DON’T CARE
tUS
UPDATE
tUL = 14 CLK RISING EDGES
tUD
ANALOG OUT
OLD FREQ
NEW FREQ
FIGURE 2. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH)
tWH
tWS
WE
tAS tAH
ADDR
A0
A1
A2
A3
A4
A5
DON’T CARE
DATA
W0
W1
W2
W3
W4
W5
DON’T CARE
tDS
tDH
WRITE
DON’T CARE
t = 6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD
CLK
DON’T CARE
tUL= 11 CLK RISING EDGES
UPDATE
PREVIOUS FREQ
ANALOG OUT
ENTIRE NEW FREQ
PARTIAL UPDATES
FIGURE 3. PARALLEL-LOAD METHOD 2, UPDATE ACTIVE WHILE LOADING REGISTERS (RESET = HIGH)
11
HSP45314
Timing Diagrams
(Continued)
ONE CLK RISING EDGE
REQUIRED WHILE RESET LOW
CLK
tRS
RESET
tRL = 11 CLK RISING EDGES
PREVIOUS REGISTER VALUES
ANALOG OUT
RESET REGISTER VALUES
FIGURE 4. RESET TIMING AND LATENCY
CLK
tEH
ENOFR
tES
CENTER FREQUENCY ONLY
ANALOG OUT
CENTER + OFFSET
CENTER ONLY
CENTER
+ OFFSET
tEL = 14 CLK RISING EDGES
FIGURE 5. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH)
Pin Descriptions
PIN NO.
PIN NAME
TYPE
PIN DESCRIPTION
44-48, 1-3
C(7:0)
Input
8-bit Processor Input Data Bus. C7 is the MSB. Data is written to the control register selected on
A(3:0) on the rising edge of WR when WE is active.
42
WR
Input
Write Clock For The Processor Interface. Parallel data is clocked into the chip on the rising edge
of WR.
40
WE
Input
Write Enable. Active low. WE must be active when writing data to the chip.
35-38
A(3:0)
Input
Processor Interface Address Bus. These pins select the destination register for data on the C(7:0)
bus. A3 is the MSB.
6
CLK
Clock
NCO and DAC Clock. The phase accumulator and DAC output update on the rising edge of this
clock. CLK can be asynchronous to the WR clock.
8
RESET
Input
Reset. Active Low. Resets control registers to their default states (see register description table)
and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur.
30
DGND
(Input)
Connect to DGND. Future serial clock input.
27
DGND
(Input)
Connect to DGND. Future serial data input.
32
DGND
(Input)
Connect to DGND. Future serial sync input.
9
UPDATE
Input
12
Active Low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0)
pins. This pin is provided for updating an entire frequency word at once rather than byte by byte.
HSP45314
Pin Descriptions
(Continued)
PIN NO.
PIN NAME
TYPE
PIN DESCRIPTION
33, 34
PH(1:0)
Input
Phase Offset Bits. The phase of the output is shifted. If not used, these pins should be grounded.
00 – 0 degrees reference
01 – 90 degrees shift
10 – 180 degrees shift
11 – 270 degrees shift
4
ENOFR
Input
Enable Offset Frequency. Active High. When high, the offset frequency bus is enabled to the
phase accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the
contents of the offset frequency registers. If not used, the pin should be grounded.
10
COMPOUT
Output
11
REFLO
Input
Connect to analog ground to enable the DAC’s internal 1.2V reference or connect to AVDD to
disable the internal reference.
12
REFIO
Input
Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a
0.1µF cap to ground from the REFIO pin when a DC reference voltage is used.
13
FSADJ
Full Scale Current Adjust for the DAC. Use a resistor to ground (RSET) to adjust the full scale
output current. Full Scale Output Current = 32 x VFSADJ/RSET, where VFSADJ equals the
reference voltage.
14
COMP1
Noise reduction for the DAC. Connect a 0.1µF cap to AVDD plane.
19
COMP2
Noise reduction for the DAC. Connect a 0.1µF cap to AGND plane.
18
IOUTA
Output
DAC Current Output.
17
IOUTB
Output
DAC Complementary Current Output.
20
AVDD
Power
Analog Supply Voltage.
15, 16, 21, 24
AGND
Gnd
7, 26, 31, 43
DVDD
Power
5, 25, 28, 29, 41
DGND
Gnd
Digital Ground.
22, 23
IN+, IN-
Input
Comparator Inputs. To power down the comparator, connect both of these pins to the analog
power supply. This will conserve ~4mA of current.
39
NC
NC
Comparator Output.
Analog Ground.
Digital Supply Voltage.
No Connect.
Control Register Descriptions
DESCRIPTION
RESET
STATE
ADDRESS
BITS
0
7:0
Center frequency bits CF(7:0) (Least Significant Byte).
00 h
1
7:0
Center frequency bits CF(15:8).
00 h
2
7:0
Center frequency bits CF(23:16).
00 h
3
7:0
Center frequency bits CF(31:24).
00 h
4
7:0
Center frequency bits CF(39:32).
00 h
5
7:0
Center frequency bits CF(47:40) (MSByte). (Reset gives fCLK/4 output).
40 h
6
7:0
Offset frequency bits OF(7:0) (LSByte).
00 h
7
7:0
Offset frequency bits OF(15:8).
00 h
8
7:0
Offset frequency bits OF(23:16).
00 h
9
7:0
Offset frequency bits OF(31:24).
00 h
10
7:0
Offset frequency bits OF(39:32).
00 h
11
7:0
Offset frequency bits OF(47:40) (MSByte).
00 h
13
HSP45314
Control Register Descriptions
ADDRESS
BITS
12
7:1
0
13
14
7:0
(Continued)
RESET
STATE
DESCRIPTION
Bits 7 through 1 are Intersil reserved for future serial input control. Do Not Change.
00 h
Center Frequency Enable. 1 = enable, 0 = center frequency disabled.
This bit can be used to zero the center frequency (CF(47:0)) to the phase accumulator. This does not zero
the processor interface registers - just the data path from the registers to the phase accumulator.
1b
NCO control word.
F8 h
7
Intersil reserved. Do Not Change.
1b
6
Intersil Reserved. Do Not Change. Future Serial output frequency register enable.
1b
5
Phase accumulator feedback. 0 = accumulator feedback disabled, 1 = accumulator enabled.
1b
4:0
Intersil reserved. Do Not Change.
11000 b
7:0
User should write 30 h to address 14 after RESET.
10 h
5:4
NCO-to-DAC setup and hold time control. Set to 11b.
01 b
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
14
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Similar pages