DATASHEET

HSP50215
TM
Data Sheet
January 1999
File Number
4346.4
Digital UpConverter
Features
The HSP50215 Digital UpConverter (DUC) is a QASK/FM
modulator/FDM upconverter designed for high dynamic range
applications such as cellular basestations. The DUC combines
shaping and interpolation filters, a complex modulator, and
Timing and Carrier NCO’s into a single package. Each DUC
can create a single FDM channel. Multiple DUC’s can be
cascaded digitally for multi-channel applications.
• Output Sample Rates Up to 52 MSPS (48 MSPS
Industrial); Input Data Rates Up to 3.25 MSPS
• I/Q Vector, FM, and Shaped FM Modulation Formats
• 32-Bit Programmable Carrier NCO; 30-Bit Programmable
Symbol Timing NCO
• Programmable I and Q, 256 Tap, Shaping FIR Filters with
Interpolation by 4, 8 or 16
The HSP50215 supports both vector and FM modulation. In
vector modulation mode, the DUC accepts 16-bit I and Q
samples to generate virtually any quadrature AM or PM
modulation format. The DUC also has two FM modulation
modes. In the FM with pulse shaping mode, the 16-bit
frequency samples are pulse shaped/bandlimited prior to FM
modulation. No bandlimiting filter follows the FM modulator.
This FM mode is useful for GMSK type modulation formats. In
the FM with bandlimiting filter mode, the 16-bit frequency
samples directly drive the FM modulator. The FM modulator
output is filtered to limit the spectral occupancy. This FM mode
is useful for analog FM or FSK modulation formats.
• Interpolation Filter Up Samples Shaping Filter Output to
Output Sample Rate Under NCO Control
• Processing Capable of >90dB SFDR
• Cascade Input for Multiple Channel Transmissions
• 16-Bit µProcessor Interface for Configuration and User
Data Input
Applications
• Single or Multiple Channel Digital Software Radio
Transmitters (Wide-Band or Narrow-Band)
The DUC includes an NCO driven interpolation filter, which
allows the input and output sample rate to have a noninteger or variable relationship. This re-sampling feature
simplifies cascading modulators with sample rates that do
not have harmonic or integer frequency relationships.
• Base Station Transceivers
• Operates with HSP50214 in Software Radio Solutions
• Compatible with the HI5741 D/A Converter
• HSP50215EVAL Evaluation Board Available
The DUC offers digital output spectral purity that exceeds
85dB at the maximum output sample rate of 52 MSPS, for
input sample rates as high as 300 KSPS.
Ordering Information
PART
NUMBER
A 16-bit microprocessor compatible interface is used to load
configuration and baseband data. A programmable FIFO depth
interrupt simplifies the interface to the I and Q input FIFOs.
TEMP
RANGE (oC)
PACKAGE
PKG. NO
HSP50215VC
0 to 70
100 Ld MQFP
Q100.14x20
HSP50215VI
-40 to 85
100 Ld MQFP
Q100.14x20
Block Diagram
MUX
CE
C(15:0)
A(9:0)
CONTROL
QIN(15:0) †
IIN(15:0) †
CF(31:0) †
SF(29:0) †
COS
I FM
Q FM
WR
RD
LIMITER
+
OUT(15:0)
OE
FM
MOD
RST
+
SIN
REFCLK
SYNCIN
GAIN
CTRL
INTERPOLATION
FILTER
QFIFO
MUX
†
SHAPING FILTER
QIN(15:0)
IFIFO
MUX
†
1-7 DEEP
FIFO
IIN(15:0)
OUTPUT FORMATTER
† = µP CONTROL SIGNALS
CAS(15:0)
CASZ
OFM
NCO
CF(31:0)
NCO
†
SYNCOUT
FIFORDY
SAMPCLK
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
Functional Block Diagram
CAS(1P5:0)
CASZ
MOD (1:0)
†
I FM
RTH (2:0)†
MOD (1:0) †
RST
COARSE
PHASE
†
†
NCO
ICOEFFICIENTS(15:0)
†
†
QCOEFFICIENTS(15:0)
CF(31:0)
†
OUTGAIN (7:0)†
EN OUT †
DLYSEL †
DS (3:0)†
CONTROL
+
OUT(15:0)
OFM
OE
NCO
SR(29:0)
CE
C(15:0)
A(9:0)
+
EN_OUT †
MOD (1:0) †
SET
CLOSE
TO LIMIT
†
MOD (1:0)
WR
RD
INTERPOLATION
FILTER
HSP50215
RST
GAIN
CTRL
LIMITER
SHAPING
FILTER
COS
QFIFO
(-3dBFS)
0.707
SIN
†
MUX
QIN(15:0)
1-7 DEEP
FIFO
REFCLK
IFIFO
LIMITER
3-2
IIN(15:0) †
(-2dBFS)
0.8 MAX
OUTPUT FORMATTER
Q FM
MUX
MUX
FM
MOD
EnNCO
IP (1:0)†
FINE
PHASE
SR
CF
EN_OUT
MOD
OUTGAIN
FIFORDY
IFIFOEMPTY
QFIFOEMPTY
RTH
EnNCO
SYNCPOL
DS
IP
FIFORDY
SAMPCLK
STATUS
SYNCPOL †
SYNCSEL †
SYNC
CW3 WR
SYNCIN
SYNCOUT
† = µP CONTROL SIGNALS
HSP50215
Pinout
OUT15
OUT14
OUT13
OUT12
VCC
OUT11
OUT10
OUT9
GND
OUT8
OE
OUT7
VCC
OUT6
OUT5
OUT4
GND
OUT3
OUT2
OUT1
100 LEAD MQFP
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
OFM
CASZ
CAS0
CAS1
GND
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
VCC
GND
REFCLK
CAS8
CAS9
CAS10
CAS11
VCC
CAS12
CAS13
CAS14
CAS15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
FIFORDY
A0
A1
GND
A2
A3
A4
VCC
A5
A6
A7
GND
A8
A9
WR
VCC
CE
RD
RST
SYNCIN
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3-3
OUT0
C15
C14
C13
VCC
C12
C11
C10
C9
GND
C8
C7
C6
C5
VCC
C4
SAMPCK
C3
C2
GND
C1
C0
SYNCOUT
HSP50215
Pin Descriptions
NAME
TYPE
DESCRIPTION
VCC
-
+5V Power supply input.
GND
-
Power supply ground input.
C(15:0)
I/O
µP Bidirectional Data bus. The C(15:0) bus is used for loading the configuration data and sample vectors for modulation. C15 is the MSB.
A(9:0)
I
µP Address Bus. The A(9:0) bus is used for addressing the proper registers for loading the configuration data and
sample vectors for modulation. A9 is the MSB.
WR
I
µP Write Strobe. When CE is asserted, data on the C(15:0) data bus is loaded into the address location found on
the A(9:0) bus on the rising edge of the WR signal. In some cases, there is an internal synchronization to the master
clock that must be completed before the next data is written. See the µP interface section for more information.
RD
I
µP Read Control. When RD and CE are low, the data found in the address location defined by A(9:0) is routed to
the C(15:0) µP data bus on the next rising edge of REFCLK.
CE
I
µP Chip Enable. Used to gate the WR and RD µP interface control signals.
FIFORDY
O
FIFO Ready. A FIFORDY assertion indicates that the I and Q FIFOs have reached the programmed FIFO depth and
more samples are required to maintain that FIFO depth.
REFCLK
I
Reference Clock. REFCLK is the master clock for the DUC. All timing is relative to the REFCLK rising edge. The
frequency of the reference clock is denoted fCLK, and is the rate at which data is output from the part.
CAS(15:0)
I
Cascade Input Bus. This input bus is used to cascade multiple parts by routing the digital modulated signal from
one DUC into the output summer of a second DUC. CAS(15:0) is 2’s complement format and is sampled on the
rising edge of REFCLK. CAS15 is the MSB.
CASZ
I
Cascade Input Bus Zero. When CASZ is asserted (pulled high), the part places zeroes on the CAS(15:0) data path.
CASZ is asynchronous (not registered) to REFCLK and should not be changed on the fly. When unused, pull high
with a pull up resistor (~22kΩ).
OUT(15:0)
O
Output Data Bus. OUT(15:0) contains the digital modulated DUC output samples and is updated on the rising edge
of the REFCLK. OUT15 is the MSB.
OFM
I
Output Data Bus Format. When OFM is asserted (pulled high), the output bus format is 2’s complement. When not
asserted, the output format is offset binary. The OFM input is asynchronous (not registered) to REFCLK and should
not be changed on the fly.
OE
I
Output Data Bus Enable. When OE is asserted (dropped low), the output data bus OUT(15:0) is enabled. When OE
is not asserted (pulled high), the output data bus OUT(15:0) is placed in the high impedance state.
SYNCIN
I
Sync Input. The SYNCIN input is used to synchronize the processing of multiple parts. The SYNCOUT of one part
acts as a master and is connected to the SYNCIN of all of the DUC’s that are to by synchronized. The DUC can be
programmed so that either rising or falling edge of this signal initiates the processing.
SYNCOUT
O
Sync Output. The SYNCOUT output is used to synchronize the processing of multiple parts. The SYNCOUT of one
part acts as a master, and is connected to the SYNCIN of all of the DUC’s that are to be synchronized.
SAMPCLK
O
Sample Clock. This clock is provided to the data source to indicate when data is being transferred from the FIFO to
the shaping filter. The SAMPCLK output is generated by the sample rate NCO when the digital filter takes a new
sample. It has approximately 50% duty cycle. The sample is taken on the high-to-low transition. SAMPCLK may be
used instead of FIFORDY.
RST
I
Reset. When the RST input is asserted (dropped low), the DUC is reset and all processing halts. The DUC may
also be reset on µP command. Processing remains halted until a sync is generated either by µP command or
assertion of SYNCIN. See the Reset section details of the specific functions halted by this control signal.
3-4
HSP50215
Functional Description
The FIFOs provide the data interface between the µP and
either the FM modulator or the shaping filters. Multiplexers
route the I data to the FM modulator in the FM with
bandlimiting filter mode. Both I and Q are routed to the 256
tap FIR shaping filters in the QASK mode. The shaping filter
serves to both shape and interpolate the sample rate to 4, 8,
or 16 times the input sample rate. The I shaping filter output
can also be routed to the FM modulator for the FM with pulse
shaping mode. Multiplexers select either the FM modulator
output or the shaping filter output to be scaled and routed to
the interpolation filters.
The I and Q interpolation filters allow a non-integer increase in
sample rate, up to the reference clock rate. The interpolation
filter output data is upconverted or modulated by the Carrier
NCO and multipliers. The modulated signal is added to
modulated inputs from other cascaded DUC’s. The output
formatter sets the output buffer state and the output data
format.
Programmable FIFO
The Programmable FIFOs provide a data storage and
interface between the microprocessor data write holding
register and the shaping filter or the FM modulator. Signal
routing out of the FIFO is set by the modulation format. Each
FIFO has seven 16-bit registers. Figure 1 shows the
conceptual details of the I and Q FIFOs.
DFF2
DFF3
DFF4
R
E
G
R
E
G
R
E
G
R
E
G
A(000)
>
WR
IIN(15:0)
>
>
>
>
† ALL REGISTERS
ARE CLOCKED AT
REFCLK UNLESS
SHOWN OTHERWISE
WRITE SHIFT ENABLE
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
ZERO’S
8:1 MUX
COMP
A(2:0)
DFF
COMP
RTH(2:0)
IFIFO(15:0)
FIFORDY
QFIFO(15:0)
FM ENABLED
8:1 MUX
QIN(15:0)
>
R
E
G
>
R
E
G
>
WR
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
WRITE SHIFT ENABLE
DFF1
DFF2
DFF3
DFF4
R
E
G
R
E
G
R
E
G
R
E
G
A(001)
>
WR
>
>
>
FIGURE 1. I AND Q FIFO BLOCK DIAGRAM
WR
1
2
3
4
REFCLK
DLY DATA
DFF 1
DFF 2
DFF 3
DFF 4
WR SHFT EN
REG1
FIFO NEEDS
FIFORDY MORE DATA
FIFO NEEDS
MORE DATA
FIGURE 2. FIFORDY AND DATA DELAY TIMING
3-5
R
E
G
WR
1
The DUC is configured via the 16-bit microprocessor data
bus, using the address bus and RD, WR and CE control
signals. Configuration data that is loaded via this bus
includes the 30-bit Sample Rate NCO center frequency, the
32-bit Carrier NCO center frequency, the modulation format,
gain control, FIFO control, reset control and sync control.
The I and Q baseband channels each have a 256 tap FIR
filter whose coefficients and configuration are also
programmed via the µP interface. Similarly, the control
signals for the I and Q channel interpolation filters are
programmed via the µP interface. Once the operational
configuration for the device has been set, the 16-bit µP
interface is used to input the I and Q data into the associated
FIFOs.
DFF1
0
The HSP50215 Digital UpConverter (DUC) converts digital
baseband data into modulated or frequency translated digital
samples. The DUC can be configured to create any
quadrature amplitude shift-keyed (QASK) data modulated
signal, including QPSK, BPSK, and m-ary QAM. The DUC
can also be configured to create both shaped and unfiltered
FM signals. A minimum of 16 bits of resolution is maintained
throughout the internal processing.
HSP50215
NOTE: The Write rate is not the parameter that determines the
maximum input rate, the shaping filter is. The maximum input for the shaping filter is 52MHz/(IP)(DS), which is
52MHz/16 = 3.25 MHz for a minimal shaping filter (DS = IP =
4). See the Shaping Filter Section for more details.
The timing details of these FIFO registers are shown in Figure
2. While the data for the I and Q inputs are independent, the
Write cycle limitations of the FIFO constrains the maximum
input symbol rate of quadrature symbols (both I and Q data) as
noted.
When the Shaping Filter requires another sample of data, a
request is made to the FIFO for data and the FIFO counter is
decremented. Figure 3 indicates the timing of a request for data
from the Shaping filter to the actual appearance of data at the
FIFO output. The FIFO has circuitry for detecting an empty
FIFO as well as a full FIFO. An “empty” FIFO detection causes
“zero” data to be entered into the shaping filter. A “full” FIFO
detection prevents data from being pushed out of the FIFO
before the filter requests it.
NOTE: Do not write to a full FIFO. Writing to a full FIFO is an error condition and the part will be reset to prevent transmission of erroneous data over the air.
A programmable FIFO depth threshold sets when the
FIFORDY signal is asserted, alerting the data source that more
data is required. The FIFORDY signal assists a data source in
maintaining the desired FIFO data depth. Control Word 18, bits
0-2 are used to set the data FIFO depth threshold for both I and
Q inputs.
NOTE: SAMPCLK may be used instead of FIFORDY to indicate
that data is transferred from the FIFO to the shaping filter.
See the Pin Description Table.
with post-modulation filtering, and 10:FM with premodulation pulse shaping. These modulation paths are
defined in the following subsections.
Modulation Mode 00 - QASK
This modulation mode configures the PUC as a BPSK,
QPSK, OQPSK, MSK or m-QAM modulator. The filter
configuration is shown in Figure 4. The data FIFO outputs
are routed to the shaping filters. Here the samples are
interpolated by 4, 8, or 16 and shaped using a FIR filter with
up to a 256 taps. The filter impulse response can span 4-16
input samples. A half (input) sample delay can be set in the I
channel for implementing OQPSK modulation. The output of
the shaping filter is routed through a gain adjust multiplier
and into the interpolation filter. The interpolation filter
interpolates by a factor set in the resampling NCO. The
output of the interpolation filter is at the master clock
frequency, REFCLK. The samples are then mixed with the
carrier L.O. for quadrature upconversion. The output is then
summed with the cascade input signal, saturated (in the
case of overflow), and formatted for output.
I
Q
SHAPING
FILTER
INTERPOLATION
FILTER
TO
MODULATOR
FIGURE 4. QASK
Modulation Mode 01 - FM with Bandlimiting Filter
This mode configures the PUC as an FM modulator with
post-modulation filtering. This mode provides for FSK and
FM modulation schemes. In this mode, the I input samples
drive the frequency control section of a quadrature NCO to
produce a zero IF FM signal. The FM quadrature signals are
then routed to the shaping FIR filter and into the interpolation
filter for bandlimiting and interpolation up to the master clock
rate as shown in Figure 5. The quadrature filtered FM signals
are then upconverted to the carrier frequency by the carrier
NCO and mixers. The output is then summed with the
cascade input signal, saturated (in the case of overflow), and
formatted for output. Note that pulse shaping in this mode
must be provided prior to the PUC.
.
I
REFCLK
FM
MODULATOR
SHAPING
FILTER
INTERPOLATION
FILTER
EnFIFO
TO
MODULATOR
Data enters the FIFO with a write command to either Control
Word 0 (for I data), or Control Word 1 (for Q data). This
transfers data from the microprocessor holding register into the
first 16-bit register of the FIFO. The FIFO counter is
incremented every time data is written into the FIFO. Four
REFCLK periods are required from the rising edge of a WR
signal before another WR rising edge can occur, (i.e., before
data can once again be written into either the I or Q FIFO). This
limits the maximum data input (write) rate to 52MHz/4 =
13MHz.
FIGURE 5. FM WITH BANDLIMITING
IFIFO
FIGURE 3. FIFO DATA AND ENABLE TIMING
Data Modulation Path
Three data path options are provided, one for each
modulation format. The modulation format is selected using
Control Word 16 (See the Microprocessor Write section).
Control Word 16 bits (1:0) are defined as: 00:QASK, 01:FM
3-6
Modulation Mode 10 - FM with Pulse Shaping
This mode configures the PUC as an FM modulator with premodulation baseband pulse shaping. The data from the
FIFO (I channel only) is routed to the FIR shaping filter. The
FIR shaping filter output drives the frequency control section
of a quadrature NCO to produce a zero I.F. FM signal. These
HSP50215
I
SHAPING
FILTER
FM
MODULATOR
INTERPOLATION
FILTER
TO
MODULATOR
FM modulated quadrature samples are then up sampled in
the interpolation filter to the output sample rate. The
baseband modulated signal is then upconverted to the
carrier frequency by the carrier NCO and mixers. The output
is then summed with the cascade input signal, saturated,
and formatted for output.
FIGURE 6. FM WITH PULSE SHAPING
In Mode 10, the amplitude out of the shaping filter needs to
be limited in order to prevent frequency excursions that
cannot be filtered out in the interpolation filter. The quality of
the FM signal is affected by the amplitude slew rate out of
the shaping filter. As a rule of thumb, limiting this slew rate to
less than 1/8 the sample rate will minimize this distortion.
FM Modulator
The FM modulator provides for frequency modulation of the
carrier center frequency by the PUC input data. The FM
modulator is driven either directly by the PUC I input (Mode
1) or by the output of the FIR shaping filter (Mode 2). The
input data to the FM Modulator, is defined as dφ(n)/dt, where
φ(nT) is the phase of a theoretical sinusoid described by:
s ( n ) = A (cos [ φ ( nT ) ]+ j sin [ φ ( nT ) ]); A ≈ 1 in Modulator (EQ. 1)
Figure 7 illustrates the conceptual design of the FM modulator.
The input to the FM modulator, dφ(n)/dt, is integrated via the
carrier NCO accumulator. The NCO accumulator output
represents phase and is used to address a SIN/COS generator,
synthesizing a sinusoid of the form described in Equation 1.
The phase accumulator feedback of the NCO is 16 bits and
sixteen bits of the phase word are routed to the SIN/COS
generator. Sixteen bits of resolution are provided on the Sine
and Cosine outputs.
16
16
dφ(nT)/dt
∑
>
EnNCO
MODE
1 OR 2
R
E
G
SIN/COS
ROM
φ(nT)
16 COS[φ(nT)]
16 SIN[φ(nT)]
FIGURE 7. FM MODULATOR BLOCK DIAGRAM
The transfer function of the FM modulator is defined by the
change in degrees per sample value, dφ(nT)/dt, where
dφ(nT)/dt is a 16-bit, twos complement, fractionally notated
frequency control word with a range from -FSAMP/2 to
+FSAMP/2. FSAMP is defined as the sample rate into FM
modulator. The maximum phase step that can occur in one
3-7
clock is ±180 degrees. Table 1 provides the change in phase
weighting of the input bits.
TABLE 1. FM MODULATOR TRANSFER FUNCTION
dφ(nT)/dt
DEGREES/SAMPLE
1000 0000 0000 0000
-180
0000 0000 0000 0000
0
0111 1111 1111 1111
~+180
Shaping Filter
The shaping filter provides the necessary pulse shaping
required on the input data to implement various quadrature
ASK and shaped FM modulation formats. Two identical
shaping filters (one each for the I and Q channels) are
provided. The filters can implement a 4-16 input sample
span impulse response using up to 256 taps with 16 bits of
resolution in the coefficients.
The range of valid digital values for the coefficients is from
8001 to 7FFF. The value 8000 is not allowed. The coefficient
format is 2’s complement. The span of the Impulse response
of the polyphase filter can be from 4-16 samples. The
desired sample span value minus one is programmed into
the Data Samples (DS) field in Control Word 19, bits 2-5.
The filter has a programmable interpolation rate (IP) of 4, 8,
or 16. This interpolation rate is programmed by Control
Address 19, bits 0 and 1. Thus, the required number of
coefficients (or filter span) becomes
# Coefficients = (DS)(IP)
(EQ. 2)
with 256 being the maximum number of coefficients.
Note that
REFCLK > ( DS ) ( IP ) ( f S )
(EQ. 3)
where fS is the input sample rate of the shaping filter. For a
16 input sample impulse response span, the total impulse
response is 64, 128 or 256 filter taps for interpolation rates of
4, 8 or 16, respectively. The filter structure precludes
coefficient re-use for symmetric filters, so both asymmetric
and symmetric filters have up to 256 taps available and are
loaded in identical manner.
The maximum input sample rate is:
f S = f CLK ⁄ [ ( IP ) ( DS ) ]
(EQ. 4)
where fCLK is the frequency of the reference clock, IP is the
shaping filter interpolate rate; and DS is the number of data
samples in the filter span. For example, if fCLK = 52MHz, the
filter span is 16 samples, and the interpolation rate is 16,
then the maximum input sample rate, fS is 52/256 = 203kHz.
Table 2 shows several examples of calculations for FIR input
sample rates based on master reference clock rate, number
of data samples, and interpolation rate.
HSP50215
TABLE 2. EXAMPLES OF THE DIFFERENT CASES AND
DIFFERENT FIR INPUT SAMPLING FREQUENCIES
EXAMPLE
fCLK
DS
IP
1
52MHz
16
16
52/256 = 203kHz
2
52MHz
16
8
52/128 = 406kHz
3
52MHz
16
4
52/64 = 813kHz
4
5
6
52MHz
52MHz
52MHz
10
8
4
4
4
4
MAX fS
where Gain is the desired signal level relative to fullscale,
GaindB is the desired signal level in dB relative to fullscale,
and OutGain is the control word value.
Table 3 details a few key control words and the associated
attenuations for the I and Q signals.
TABLE 3. SCALING GAIN ATTENUATION
CONTROL WORD
GAIN
(dBFS)
52/40 = 1300kHz
1111 1111yt
-0.033996
52/32 = 1625kHz
1000 0000
-6.021
50.0
0100 0000
-12.041
25.0
0010 0000
-18.062
12.5
0001 0000
-24.082
6.25
52/16 = 3,250kHz
(fCLK = 48MHz for industrial temperature range).
SCALING GAIN
(VOUT/VIN)%
99.6
0000 1000
-30.103
3.125
Shaping Filter Application Issues
0000 0100
-36.124
1.5625
Note that when using quadrature modulation,
saturation/overflow can occur when the input values for I and Q
exceed 0.707 peak. Also note that there is gain in Interpolation
filter. Because of these two implementation constraints, the
Shaping filter coefficients may need to be reduced from full
scale to provide unity gain in the PUC and to prevent saturation
in the shaping filter. After the shaping filter computation, a gain
scaling control is provided. It is possible to allow the shaping
filter computation to approach unity on each channel and then
scale the I/Q magnitudes in the Gain Control.
0000 0010
-42.144
0.78125
0000 0001
-48.165
0.390625
The delay through the shaping and interpolation filters is 20
CLKs and the shaping filter delay.
Gain Control
Between the Shaping filter and the Interpolation filter is a gain
adjustment stage that provides for identical scaling of the I
and Q shaped signals. Gain adjustment is from 0 to slightly
less than unity. This gain control can be used to prevent signal
overflow in the Interpolation filter or saturation in the
quadrature mixer.
The interpolation filter can have a gain of 2dB. If a full scale
signal is required at the output of the shaping filter, apply 2dB
back off in the Gain Adjust Circuit. For worst case conditions,
the interpolation filter can have 25% overshoot. (See the
annotations on the Functional Block Diagram). Gain control
can also be used to set the level of a signal prior to summing
multiple signals in the Modulated Output Section.
The scaling multiplier value is programmed using an bits 0-7
in Control Word 17. The attenuation is set by:
Gain = OutGain/2
8
(EQ. 5)
8
Gain dB = 20 log [ OutGain ⁄ 2 ]
8
OutGain = [ ( Gain )2 ]Hex
OutGain = 10
( Gain dB ⁄ 20 ) 8
2 ]Hex
3-8
Re-Sampling NCO
The Sample Rate NCO provides the sample clock and
sample clock phase information to both the shaping and
Interpolation filters. Figure 8 details the conceptual design.
The sample frequency is set with 30-bit resolution. The LSB is
REFCLK/232. The internal accumulator resolution in 32 bits.
The MSB of the accumulator is the sample clock for the filters.
Four bits of coarse timing phase resolution control the
Shaping filter, while twelve bits of fine timing phase resolution
control the Interpolation filter.
The Resampling NCO frequency control word is double
buffered. The 30-bit timing NCO frequency is written to
Control Addresses 2 and 3. The frequency control word is
transferred from the buffer into the Re-Sampling NCO on a
pulse from SYNCIN or on a write to Control Word 2. Control
Word 22, bit 0, sets which action, (the SYNCIN or write to
CW2), causes a frequency control word transfer in the NCO.
Assertion of RST stops the Re-Sampling NCO and clears
the accumulator contents. It is held disabled until a SYNCIN
or write to Control Word 3 generates an EnNCO signal to
restart the NCO.
The PUC input sample rate is set by the Re-Sampling NCO.
The maximum error is 52MHz/(232) = 0.012Hz for the
commercial part and 48MHz/(232) = 0.011Hz for the
industrial part. The frequency control word is computed by:
F RESAMP = SR ( 29:0 ) × f CLK × 2
– 32
(EQ. 6)
where SR(29:0) is the 30-bit frequency control word and
fCLK is REFCLK.
(EQ. 5A)
Equation 6 can be rearranged to solve for SR(29:0).
(EQ. 5B)
f RESAMP
32
SR(29:0) = RND -------------------------- × 2
f CLK
(EQ. 5C)
The range of SR(29:0) is: [0 to 2
30
– 1]
HSP50215
Figures 9A through 9C for an interpolate by 16 filter (the
interpolation ratio, L, is equal to 16). The Interpolation filter
has a pipeline delay of 3 coarse input samples plus 3
REFCLK cycles.
SAMPLE FREQUENCY
30
ZERO
2
EN
REG
SYNCSEL
<
0
-20
EnNCO
(CARRIER NCO)
START
EDGE
GEN
32
>
WR CW21
>
RST
>
R
E
G
-40
-60
-80
REG
-100
RESET
EDGE
GEN
SAMPCK
(MSB)
R
E
G
-120
512
1024
1536 2048 2560
SAMPLE TIMES
3072
3584
4096
FIGURE 9A. INTERPOLATION FILTER IMPULSE RESPONSE
L = 16; FOUT = 4096
SHIFTER
IP(1:0)
MAGNITUDE (dB)
1
WR CW3
INTERPOLATION FILTER RESPONSE
∑
MUX
SYNCIN
0
ACC
0
12
† ALL REGISTERS ARE
CLOCKED AT REFLCK
INTERPOLATION FILTER RESPONSE
REG
4, 3, OR 2
FINE
PHASE
COARSE
PHASE
FIGURE 8. RE-SAMPLING NCO BLOCK DIAGRAM
Re-Sampling NCO Application Issues
-20
MAGNITUDE (dB)
>
-40
-60
-80
1. Common clocking of the PUC and PDC:
2. Improving the NCO Accuracy
The Re-Sampler NCO frequency can be adjusted to
maintain phase and frequency lock to a reference clock, if
more accuracy is required.
-100
-120
64
128
192
256
320
SAMPLE TIMES
384
448
512
FIGURE 9B. INTERPOLATION FILTER IMPULSE RESPONSE
L = 16; FOUT = 4096
0
-0.05
-0.1
-0.15
MAGNITUDE (dB)
Note that at a board level, the HSP50214 (PDC) and
HSP50215 (DUC) sample rate NCO’s typically utilize
different clocks. The DUC circuitry is clocked at the master
clock, REFCLK, rate. The PDC output circuitry runs off the
decimated sample rate. If a common sample clock is used
for both parts, then synchronization can be achieved by
scaling and/or truncating the PDC frequency control word to
match the PUC frequency control word. Powers of 2 are
handled by simply truncating the PDC frequency control
word to match the bit width of the DUC frequency control
word. If the PDC decimation factor is not power of 2, then
errors will accumulate.
INTERPOLATION FILTER RESPONSE
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
-0.55
-0.6
Interpolation Filter
The Interpolation filter provides sampling rate conversion
from the shaping filter output rate to the final output sample
rate. The nulls in the interpolation filter frequency response
align with the interpolation images of the shaping filter. The
impulse response of the Interpolation filter is shown in
3-9
-0.65
-0.7
8
16
24
32
40
SAMPLE TIMES
48
56
FIGURE 9C. INTERPOLATION FILTER IMPULSE RESPONSE
L = 16; FOUT = 4096
64
HSP50215
Carrier NCO
The Carrier NCO provides the quadrature local oscillator
references for the Vector Modulator/Mixer. The Carrier NCO
input carrier frequency control word has 32 bits of resolution.
The block diagram is shown in Figure 10.
The carrier frequency is a single buffered 32-bit frequency
control, loaded 16 bits at a time into Control Words 4 and 5.
Since the DUC requires two loads, there is a possibility of a
phase glitch.
The Carrier NCO is disabled during a RST assertion or a
reset caused by writing to CW21. The Carrier NCO stays
disabled until a sync assertion is detected independent of
the initiating sync source (SYNCIN or WR CW3). The Carrier
NCO is also disabled by programming a zero in Control
Word 16 bit 3. This bit freezes the NCO and also disables
the output of the modulator.
CARRIER
FREQUENCY
WR CW3
>
R
E
G
F CARRIER = CR ( 31:0 ) × f CLK × 2
– 32
(EQ. 7)
where CR(31:0) is the 32-bit frequency control word which can
range from -231 to ~231 for a NCO output range of -fCLK/2 to
~fCLK/2. fCLK is the REFCLK frequency.
This NCO frequency range allows for spectral inversion.
Given a desired carrier frequency, the value for CR(31:0)
loaded into the part can be calculated by:
CR ( 31:0 ) = INT [ F C ⁄ f CLK *2
32
]
(EQ. 8)
where INT[X] is the integer part of the real number X.
The most significant 18 bits of the 32-bit phase word from
the Carrier NCO drives a Sin/Cos generator. Eighteen bit
resolution is supplied on the sinusoid outputs.
Assertion of RST stops the Carrier NCO and clears the
accumulator contents. It is held disabled until a SYNCIN or
write to Control Word 3 generates an EnNCO signal to
restart the NCO.
1
MUX
>
R
E
G
32
0
SYNCIN
The maximum error is 52MHz/(232) = 0.012Hz for the
commercial part and 0.011Hz for the industrial part. The
carrier frequency can be calculated from the value loaded
into Control Address 4 and 5 by:
Vector Modulator/Mixer
SYNCSEL
WR CW21
>
RST
>
R
E
G
R
E
G
The frequency resolution of the vector modulator is 32 bits.
The conceptual block diagram of the Vector Modulator/Mixer
is shown in Figure 11. The modulator operates at maximum
frequency of 52MHz (commercial). The mixer takes the
sin/cos terms generated by the carrier NCO sin/cos
generator and mixes it with the input data lines I and Q. The
resulting output is given by
START
EDGE
GEN
RESET
EDGE
GEN
(EQ. 9)
Output = I * cos – Q * sin
ACC
∑
EnNCO
EN OUT
>
R
E
G
32
>
NOTE: There is no overflow protection provided at the output of
the modulator summer, so care must be taken to ensure
that the input signals are scaled prior to input to prevent
overflow.
The mixers can be bypassed by programming Control Words
4 and 5 to zero, which sets COS = 1 and SIN = 0.
REG
16
I(15:0)
SIN/COS
GEN
† ALL REGISTERS ARE
CLOCKED AT REFLCK
TO
MODULATOR
OUTPUT
18
18
SIN COS
FIGURE 10. CARRIER NCO BLOCK DIAGRAM
To avoid the phase glitch, noted above, the phase
accumulator can be disabled at reset, and the frequency can
be pre-loaded prior to asserting sync.
3-10
COS
SIN
Q(15:0)
18
18
∑
+
-
16
MOD(15:0)
16
EN OUT
FIGURE 11. VECTOR MODULATOR/MIXER BLOCK DIAGRAM
HSP50215
Cascade Input
The cascade input allows multiple modulated signals to be
summed together prior to routing to a DAC. Figure 12 is a
block diagram of the cascade circuitry. CAS(15:0) is the
input when cascading with other DUC’s. The CASZ is used
to zero the CAS(15:0) input when it is not used. Both the
CAS(15:0) and the modulator data path are registered, prior
to summation. The output of the summation is saturated to
prevent roll-over.
CAS(15:0)
Configuration data is written into the HSP50215 by setting up
the address (A9:0) and data (C15:0) and generating a rising
edge on WR. A DUC configuration sequence is shown in
Figure 13. Figure 13 assumes that CE is asserted. The filter
coefficients for the shaping filter are loaded in a similar
manner into Control Word addresses 512 - 1023.
WR
(10:0) 2
3
4
5
16
16
>
CASZ
R
E
G
17
18
19
22
23
(15:0)
∑
SATURATE
CIRCUITRY
16
LOAD CONFIGURATION DATA
FIGURE 13. CONTROL REGISTER LOADING SEQUENCE
FROM
MODULATOR
16
† ALL REGISTERS ARE
>
R
E
G
CLOCKED AT REFLCK
FIGURE 12. CASCADE INPUT BLOCK DIAGRAM
Output Formatter
The output can be either twos complement or offset binary
format. The OFM signal is used to select the output format.
OFM = 1 is twos complement. OFM = 0 is Offset Binary
format. The OE signal is used to enable the data bus output.
OE = 0 enables the output.
NOTE: The HSP43216 can be used to double the output sample
rate of the DUC, in applications where a higher sample
rate into the DAC is required.
The Re-Sampler NCO Center Frequency data is double
buffered and transfers from the Microprocessor Interface
holding registers to the Center Frequency Register on the
assertion of SYNCIN or a Write to Configuration Control
Word 3. The timing waveforms for this process are shown in
Figure 14.
REFCLK
WR
SYNCIN
A0-2
02
03
C0-7
MSB
LSB
Microprocessor Interface
CW02
The microprocessor interface is a memory mapped direct
access interface. The control pins are RD, WR and CE. The
10-bit address bus is A(9:0) [address space is 1024 words]
and the 16-bit data bus is C(15:0). The CE signal gates the
RD and WR. Care must be taken in changing the address
and data lines, as the addresses are updated asynchronous
to REFCLK except in the cases noted in the Microprocessor
Write Section. Most addresses are intended to be
programmed after RESET and before the Start Sequence,
and left alone after that. See the RESET and Start
Sequence sections from more details on initiating operation
of the part.
CW03
Reads are asynchronous to clock. The shaping filter
coefficients cannot be read. See the Configuration Control
Register Bit Definitions section for programming details of
the 14 Control Words and the 512 Coefficient Registers.
Microprocessor Write
The Microprocessor Write Interface is used for loading data
into the DUC control registers. Write registers are accessed
via the 10-bit address bus (A9:0) and the 16-bit data bus
(C15:0). The address map for these registers is given in the
Configuration Control Register Bit Definition section.
3-11
SR(29:0)
MSB
LSB
NEW SR
VALUE
FIGURE 14. RESAMPLER CENTER FREQUENCY CONTROL
REGISTER LOADING SEQUENCE
When SYNCIN is sampled “high” by the rising edge of clock,
the contents of the holding registers are transferred to the
Sample Center Frequency Register. Caution should be
taken when using the SYNCIN since the holding register
contents will be transferred to the Sample Center Frequency
Register whenever SYNCIN is asserted (and external sync
is selected via CW22).
Shaping filter I coefficients are loaded from the first coefficient
(C0) in address 0x200h to the last address in 0x2FFh.
Because interpolation by 16 is possible, the coefficient
addresses are structured in blocks of 16, one address for
each phase of the interpolation. With a 256 tap filter using an
interpolation of 16, there are 16 multiplies required to
implement the filter. Tables 4 and 5 detail the coefficient
address allocation, with the Interpolation Phase indicated by
the IP number on the left, and the multiplier number
indicated by the numbers 0 through 15 across the top.
HSP50215
TABLE 4. I SHAPING FILTER COEFFICIENT ADDRESSES
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
IP0
512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
IP1
513
529
545
561
577
593
609
625
641
657
673
689
705
721
737
753
IP2
514
530
546
562
578
594
610
626
642
658
674
690
706
722
738
754
IP3
515
531
547
563
579
595
611
627
643
659
675
691
707
723
739
755
IP4
516
532
548
564
580
596
612
628
644
660
676
692
708
724
740
756
IP5
517
533
549
565
581
597
613
629
645
661
677
693
709
725
741
757
IP6
518
534
550
566
582
598
614
630
646
662
678
694
710
726
742
758
IP7
519
535
551
567
583
599
615
631
647
663
679
695
711
727
743
759
IP8
520
536
552
568
584
600
616
632
648
664
680
696
712
728
744
760
IP9
521
537
553
569
585
601
617
633
649
665
681
697
713
729
745
761
IP10
522
538
554
570
586
602
618
634
650
666
682
698
714
730
746
762
IP11
523
539
555
571
587
603
619
635
651
667
683
699
715
731
747
763
IP12
524
540
556
572
588
604
620
636
652
668
684
700
716
732
748
764
IP13
525
541
557
573
589
605
621
637
653
669
685
701
717
733
749
765
IP14
526
542
558
574
590
606
622
638
654
670
686
702
718
734
750
766
IP15
527
543
559
575
591
607
623
639
655
671
687
703
719
735
751
767
TABLE 5. I COEFFICIENT ADDRESSING FOR A 16 TAP INTERPOLATED BY 4 FILTER
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
IP0
512 =
C0
528 =
C4
544 =
C8
560 =
C12
576
592
608
624
640
656
672
688
704
720
736
752
IP1
513 =
C1
529 =
C5
545 =
C9
561 =
C13
577
593
609
625
641
657
673
689
705
721
737
753
IP2
514 =
C2
530 =
C6
546 =
C10
562 =
C14
578
594
610
626
642
658
674
690
706
722
738
754
IP3
515 =
C3
531 =
C7
547 =
C11
563 =
C15
579
595
611
627
643
659
675
691
707
723
739
755
IP4
516
532
548
564
580
596
612
628
644
660
676
692
708
724
740
756
IP5
517
533
549
565
581
597
613
629
645
661
677
693
709
725
741
757
IP6
518
534
550
566
582
598
614
630
646
662
678
694
710
726
742
758
IP7
519
535
551
567
583
599
615
631
647
663
679
695
711
727
743
759
IP8
520
536
552
568
584
600
616
632
648
664
680
696
712
728
744
760
IP9
521
537
553
569
585
601
617
633
649
665
681
697
713
729
745
761
IP10
522
538
554
570
586
602
618
634
650
666
682
698
714
730
746
762
IP11
523
539
555
571
587
603
619
635
651
667
683
699
715
731
747
763
IP12
524
540
556
572
588
604
620
636
652
668
684
700
716
732
748
764
IP13
525
541
557
573
589
605
621
637
653
669
685
701
717
733
749
765
IP14
526
542
558
574
590
606
622
638
654
670
686
702
718
734
750
766
IP15
527
543
559
575
591
607
623
639
655
671
687
703
719
735
751
767
3-12
HSP50215
TABLE 6. Q SHAPING FILTER COEFFICIENT ADDRESSES
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
IP0
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1008
IP1
769
785
801
817
833
849
865
881
897
913
929
945
961
977
993
1009
IP2
770
786
802
818
834
850
866
882
898
914
930
946
962
978
994
1010
IP3
771
787
803
819
835
851
867
883
899
915
931
947
963
979
995
1011
IP4
772
788
804
820
836
852
868
884
900
916
932
948
964
980
996
1012
IP5
773
789
805
821
837
853
869
885
901
917
933
949
965
981
997
1013
IP6
774
790
806
822
838
854
870
886
902
918
934
950
966
982
998
1014
IP7
775
791
807
823
839
855
871
887
903
919
935
951
967
983
999
1015
IP8
776
792
808
824
840
856
872
888
904
920
936
952
968
984
1000
1016
IP9
777
793
809
825
841
857
873
889
905
921
937
953
969
985
1001
1017
IP10
778
794
810
826
842
858
874
890
906
922
938
954
970
986
1002
1018
IP11
779
795
811
827
843
859
875
891
907
923
939
955
971
987
1003
1019
IP12
780
796
812
828
844
860
876
892
908
924
940
956
972
988
1004
1020
IP13
781
797
813
829
845
861
877
893
909
925
941
957
973
989
1005
1021
IP14
782
798
814
830
846
862
878
894
910
926
942
958
974
990
1006
1022
IP15
783
799
815
831
847
863
879
895
911
927
943
959
975
991
1007
1023
The convolution multiplies C0 by the most recent data
sample. For a 16 tap, interpolate-by-4 filter, the calculations
are:
OUTPUT0 = (C0*D[n]) + (C4*D[n-1]) + (C8*D[n-2]) +
(C12*D[n-3])
OUTPUT1 = (C1*D[n]) + (C5*D[n-1]) + (C9*D[n-2]) +
(C13*D[n-3])
OUTPUT2 = (C2*D[n]) + (C6*D[n-1]) + (C10*D[n-2]) +
(C14*D[n-3])
OUTPUT3 = (C3*D[n]) + (C7*D[n-1]) + (C11*D[n-2]) +
(C15*D[n-3])
Table 6 indicates how the I coefficients should be loaded for
this example. Notice that 16 filter coefficients are required.
All other addresses not used. The filter interpolates by 4
and the coefficients are loaded sequentially through the 4
interpolation phases starting at 512 - 515, then jumping to
528 - 531 for the next four addresses, and so on until 16
coefficients have been loaded.
Shaping filter Q coefficients are loaded from the first
coefficient (B0) in address 0x300h to the last address in
0x3FFh. The convolution multiplies B0 by the most recent
data sample. For a 16 tap, interpolate-by-4 filter, the
calculations are:
OUTPUT0 = (B0*D[n]) + (B4*D[n-1]) + (B8*D[n-2]) +
(B12*D[n-3])
OUTPUT1 = (B1*D[n]) + (B5*D[n-1]) + (B9*D[n-2]) +
(B13*D[n-3])
3-13
OUTPUT2 = (B2*D[n]) + (B6*D[n-1]) + (B10*D[n-2]) +
(B14*D[n-3])
OUTPUT3 = (B3*D[n]) + (B7*D[n-1]) + (B11*D[n-2]) +
(B15*D[n-3])
Table 7 indicates how the Q coefficients should be loaded for
this example. Identical to the I filter, notice that since 16 filter
coefficients are required. All other addresses not used. The
filter interpolates by 4, and the coefficients are loaded
sequentially through the 4 interpolation phases, starting at
768-771, then jumping to 784-787 for the next four addresses,
and so on until 16 coefficients have been loaded.
Microprocessor Read
The DUC offers the microprocessor access to all of the
control data configuration registers through a read process.
The shaping filter coefficients, however, cannot be read.
With CE asserted, a “read” consists of dropping the RD line
low to transfer data from the register addresses selected by
A(9:0). The read address mapping is provided in Table 8.
The timing is detailed in Figure 15.
HSP50215
TABLE 7. Q COEFFICIENT ADDRESSING FOR A 16 TAP INTERPOLATED BY 4 FILTER
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
IP0 768 =
D0
784 =
D4
800 =
D8
816 =
D12
832
848
864
880
896
912
928
944
960
976
992
1008
IP1 769 =
D1
785 =
D5
801 =
D9
817 =
D13
833
849
865
881
897
913
929
945
961
977
993
1009
IP2 770 =
D2
786 =
D6
802 =
D10
818 =
D14
834
850
866
882
898
914
930
946
962
978
994
1010
IP3 771 =
D3
787 =
D7
803 =
D11
819 =
D15
835
851
867
883
899
915
931
947
963
979
995
1011
IP4
772
788
804
820
836
852
868
884
900
916
932
948
964
980
996
1012
IP5
773
789
805
821
837
853
869
885
901
917
933
949
965
981
997
1013
IP6
774
790
806
822
838
854
870
886
902
918
934
950
966
982
998
1014
IP7
775
791
807
823
839
855
871
887
903
919
935
951
967
983
999
1015
IP8
776
792
808
824
840
856
872
888
904
920
936
952
968
984
1000
1016
IP9
777
793
809
825
841
857
873
889
905
921
937
953
969
985
1001
1017
IP10
778
794
810
826
842
858
874
890
906
922
938
954
970
986
1002
1018
IP11
779
795
811
827
843
859
875
891
907
923
939
955
971
987
1003
1019
IP12
780
796
812
828
844
860
876
892
908
924
940
956
972
988
1004
1020
IP13
781
797
813
829
845
861
877
893
909
925
941
957
973
989
1005
1021
IP14
782
798
814
830
846
862
878
894
910
926
942
958
974
990
1006
1022
IP15
783
799
815
831
847
863
879
895
911
927
943
959
975
991
1007
1023
TABLE 8. READ ADDRESS MAP FOR MICRO PROCESSOR INTERFACE
A4
A2
A1
A0
DESCRIPTION
0
X
0
0
Carrier Center Frequency: CF(31:16)
0
X
0
1
Carrier Center Frequency: CF(15:0)
0
X
1
0
Re-Sampler Center Frequency: SF(29:16)
0
X
1
1
Re-Sampler Center Frequency: SF(15:0)
1
0
0
0
Modulation Control: En Out bit 3; Mod(2:0)
1
0
0
1
Gain Control: OUTGAIN(7:0)
1
0
1
0
FIFO Control: FIFO Ready bit 5; I FIFO Empty bit 4; Q FIFO Empty bit 3; RTH(2:0)
1
0
1
1
Poly-Phase Control: DS(3:0) = b5-2; IP(1:0)
1
1
0
X
EnNCO
1
1
1
0
Sync Control: Ext Sync Polarity bit 1; Sync Sel bit 0
1
1
1
1
Test Control
FIFO Ready is the logical inverse of the FIFORDY output. I and Q FIFO empty bits are the output of a “zero” state detector operating on the
address bus for the respective FIFO.
WR
RD
DON’T CARE
A(9:0)
1000
1001
1010
1011
C(15:0)
HI-Z
READ
HI-Z
READ
HI-Z
READ
HI-Z
NOTE: See Table 8 for valid Read Addresses.
FIGURE 15. TYPICAL READ SEQUENCE
3-14
READ
HI-Z
HSP50215
Reset
Starting Sequence
There are two ways to invoke a reset in the DUC: Assert the
RST signal, or write to Control Word 21. While a reset does
not stop the internal clocking, the data processing halts
because of the following actions:
DUC internal processing can be initiated by either pulsing
the SYNCIN pin (when it must be synchronized to a system
event) or by writing to the LSByte of the Sampling NCO
center frequency Control Word. The start up for the SYNCIN
pin occurs on either the rising or falling edge of the pulse,
whichever is selected in CW22, Bit 1.
• Zeros are placed into the Sample Rate and Carrier NCO
accumulator registers. These registers will be held at zero
until a sync enables the NCOs to again accept the
frequency input word.
• The I and Q FIFO depth counters are reset to zero and the
FIFORDY flipflop is Cleared, pulling the DUC FIFORDY
output high.
• The data path is disabled between the shaping filter and
the FM modulator in the prefiltered FM mode, and the
Gain adjust circuit in the QASK mode.
• In the interpolation filter, the coefficient RAM select is
disabled, the data into the data RAM is set to zeroes, the
Q channel data RAM select is disabled and the Data RAM
address is zeroed, beginning a 16 address increment to
both the I and Q Data RAMS. This enables the data
RAMS to be written with zeros.
Commanding the DUC to reset by asserting the RST signal
causes the all internal processing to halt. Furthermore,
asserting RST clears both the Sampling and Carrier NCO
frequency accumulator registers (sets the outputs = 0). The
center and offset frequency registers are not cleared by
RST. The NCO accumulator registers are held at zero until
the NCO is loaded with the first frequency value. The
Sampling and Carrier NCO center and offset frequency
registers are held at zero until an input sync has been
detected. Because the Sampling NCO does not start until
the detection of a sync (after a RST assertion), the shaping
FIR filter is also kept from processing data. Reset is
performed by either dropping the RST low or writing to
Control Word 21 (see Microprocessor Write).
3-15
For multiple DUC operation, the SYNCOUT of the first chip
acts as a master and is tied to the SYNCIN of the remaining
chips, as shown in Figure 16. When the first chip receives an
input sync from a write to the LSByte of the timing NCO
control word, then the SYNCOUT will synchronize all other
DUC’s slaved to that chip.
SYNCOUT
HSP50215
HSP50215
HSP50215
SYNCIN
SYNCIN
SYNCIN
FIGURE 16. CONFIGURATION FOR SYNCHRONIZATION OF
MULTIPLE DUCs
HSP50215
Configuration Control Register Bit Definitions
CONTROL ADDRESS 0: I CHANNEL INPUT
BIT
POSITION
15-0
FUNCTION
DESCRIPTION
I Channel QASK Input or
FM Input
IIN(15:0). In QASK mode, this is the I input vector. The format is 2’s complement. The MSB is bit 15.
The mixer operation is:
OUT = (I*COS) - (Q*SIN).
In FM mode, this is interpreted as an offset frequency to the center frequency. The modulation index
depends on the mode and the filter coefficients. In FM with post filter mode, the phase change per
input sample can range from -180 to 180 degrees, so the deviation is limited to ±(input sample rate)/2.
CONTROL ADDRESS 1: Q CHANNEL INPUT
BIT
POSITION
15-0
FUNCTION
Q Channel Input
DESCRIPTION
QIN(15:0). In QASK mode, this is the Q input vector. See address 0 above. In FM mode, this input is
not used.
CONTROL ADDRESS 2: TIMING NCO FREQUENCY MSBYTE CONTROL WORD
BIT
POSITION
FUNCTION
DESCRIPTION
15-14
Reserved (Note 1)
Reserved (Note 1).
13-0
Sample Rate Ratio’s
Most Significant 14 Bits
SR(29:16). The sample rate is controlled by a 30-bit NCO clocked at the output clock rate. The upper
MSByte of the sample rate ratio SR(29:0), or SR(29:16), is loaded in this address. The sample rate is
computed by the formula:
FRESAMP = SR(29:0) x fCLK x 2-32; SR (29:0) = INT[(FRESAMP/fCLK) X 232].
CONTROL ADDRESS 3: TIMING NCO FREQUENCY LSBYTE CONTROL WORD
BIT
POSITION
15-0
FUNCTION
Sample Rate Ratio’s
Least Significant 16 Bits
DESCRIPTION
SR(15:0). See Control Address 2. SR(15:0) is loaded in this address.
CONTROL ADDRESS 4: CARRIER CENTER FREQUENCY MSBYTE CONTROL WORD
BIT
POSITION
15-0
FUNCTION
Carrier Center
Frequency’s Most
Significant 16 Bits
DESCRIPTION
CF(31:16). The SIN/COS ROM is controlled by a 32-bit NCO clocked at the input clock rate. The upper
MSByte of the sample rate ratio CF(31:0), or CF(31:16), is loaded in this address. The center frequency is computed by the formula:
fC = CF(31:0) x fCLK x 2-32; CF(31:0) = INT(fC/fCLK X 232). Setting CW 4 and 5 to zero bypasses the
mixers (COS = 1; SIN = 0).
CONTROL ADDRESS 5: CARRIER CENTER FREQUENCY LSBYTE CONTROL WORD
BIT
POSITION
15-0
FUNCTION
Carrier Center
Frequency’s Least
Significant 16 Bits
DESCRIPTION
CF(15:0). See Control Address 4. CF(15:0) is loaded in this address. Setting CW 4 and 5 to zero bypasses the mixers (COS = 1; SIN = 0).
CONTROL ADDRESS 16: MODULATION CONTROL
BIT
POSITION
15-4
3
FUNCTION
DESCRIPTION
Reserved (Note 1)
Reserved (Note 1).
Enable Output
EN OUT.
3-16
HSP50215
CONTROL ADDRESS 16: MODULATION CONTROL (CONTINUED)
BIT
POSITION
2
FUNCTION
Delay Select
DESCRIPTION
DLYSEL.
1 = no delay.
0 = 1/2 coarse sample delay.
1-0
Mod Type
MOD(1:0):
00 = QASK.
01 = FM with filtering after modulation (analog FM with baseband filtering provided before
HSP50215). In this mode, both I and Q filters are used.
10 = FM with filtering before modulation (FSK, GMSK). This mode uses only the I filter bank.
11 = not used.
CONTROL ADDRESS 17: GAIN CONTROL
BIT
POSITION
FUNCTION
DESCRIPTION
15-8
Reserved
Reserved.
7-0
Output Gain
OUTGAIN(7:0)
OUTGAIN (7:0)
ATTENUATION
(dBFS)
SCALING GAIN
((VOUT/VIN)%)
1111 1111
-0.033996
99.6
1000 0000
-6.021
50.0
0100 0000
-12.041
25.0
0010 0000
-18.062
12.5
0001 0000
-24.082
6.25
0000 1000
-30.103
3.125
0000 0100
-36.124
1.5625
0000 0010
-42.144
0.78125
0000 0001
-48.165
0.390625
CONTROL WORDS 18: FIFO CONTROL
BIT
POSITION
FUNCTION
DESCRIPTION
15-3
Reserved (Note 1)
Reserved (Note 1).
2-0
FIFORDY Threshold
RTH(2:0). Programmable FIFO READY Threshold. This digital word represents the FIFO depth
threshold (number of data samples in the FIFO) at which the FIFORDY will be asserted, alerting the
data source that more input data is required in the FIFO. The FIFO threshold sets both the I and Q
FIFO thresholds. RTH2 is the MSB.
CONTROL WORDS 19: POLYPHASE CONTROL
BIT
POSITION
FUNCTION
DESCRIPTION
15-6
Reserved (Note 1)
Reserved (Note 1).
5-2
DS
DS(3:0). Number of data samples in shaping filter, 4-16. Load with number of data samples minus 1.
1-0
IP
IP(1:0). Number of interpolation phases:
00 = not valid.
01 = 4.
10 = 8.
11 = 16.
3-17
HSP50215
CONTROL ADDRESS 20: SPARE
BIT
POSITION
15-0
FUNCTION
Reserved (Note 1)
DESCRIPTION
Reserved (Note 1).
CONTROL ADDRESS 21: RESET CONTROL
BIT
POSITION
15-0
FUNCTION
Reset
DESCRIPTION
RST. Writing to this registers will reset this part.
CONTROL ADDRESS 22: SYNC CONTROL
BIT
POSITION
15-2
1
FUNCTION
DESCRIPTION
Reserved (Note 1)
Reserved (Note 1).
External Sync Polarity
SYNCPOL.
0 defines a Sync assertion as a transition from a logic low to a logic high; 1 defines a Sync assertion
as a transition from a logic high to a logic low:
0=
0
Sync Select
1=
SYNCSEL. 0 = Sync via a Write to Control Word 3; 1 = Sync via SYNCIN control input.
CONTROL WORDS 23: TEST CONTROL
BIT
POSITION
15-0
FUNCTION
Reserved (Note 1)
DESCRIPTION
Reserved (Note 1).
CONTROL WORDS 512-767: I CHANNEL POLY-PHASE COEFFICIENTS 512-767 (0X200H = 0X2FFH)
BIT
POSITION
15:0
FUNCTION
I Coefficients
DESCRIPTION
ICOEFFICIENTS(15:0). Coefficients are loaded from the first coefficient (C0) in address 0x200h to the
last address in 0x2FFh. The convolution multiplies C0 by the most recent data sample. For a 16 tap,
interpolate-by-4 filter, the calculations are:
OUTPUT0 = (C0*D[n]) + (C4*D[n-1]) + (C8*D[n-2]) + (C12*D[n-3]).
OUTPUT1 = (C1*D[n]) + (C5*D[n-1]) + (C9*D[n-2]) + (C13*D[n-3]).
OUTPUT2 = (C2*D[n]) + (C6*D[n-1]) + (C10*D[n-2]) + (C14*D[n-3]).
OUTPUT3 = (C3*D[n]) + (C7*D[n-1]) + (C11*D[n-2]) + (C15*D[n-3]).
See Microprocessor Write section for more detail.
CONTROL WORDS 768-1023: Q CHANNEL POLY-PHASE COEFFICIENTS 768-1023 (0X300H = 0X3FFH)
BIT
POSITION
15:0
FUNCTION
Q Coefficients
DESCRIPTION
QCOEFFICIENTS(15:0). Coefficients are loaded from the first coefficient (B0) in address 0x300h to
the last address in 0x3FFh. The convolution multiplies B0 by the most recent data sample. For a 16
tap, interpolate-by-4 filter, the calculations are:
OUTPUT0 = (B0*D[n]) + (B4*D[n-1]) + (B8*D[n-2]) + (B12*D[n-3]).
OUTPUT1 = (B1*D[n]) + (B5*D[n-1]) + (B9*D[n-2]) + (B13*D[n-3]).
OUTPUT2 = (B2*D[n]) + (B6*D[n-1]) + (B10*D[n-2]) + (B14*D[n-3]).
OUTPUT3 = (B3*D[n]) + (B7*D[n-1]) + (B11*D[n-2]) + (B15*D[n-3]).
See Microprocessor Write section for more detail.
NOTE:
1. Reserved bits should be set to logic 0.
3-18
HSP50215
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V
Typical De-rating Factor . . . . . . . . . . . . 2mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
Maximum Package Power Dissipation at 70oC
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.22W
Maximum Package Power Dissipation at 85oC
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.81W
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40oC to 85oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . 1V/ns Max
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
VCC = 5 ±5%, TA = 0oC to 70oC, Commercial; TA = -40oC to 85oC Industrial
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Logical One Input Voltage
VIH
VCC = 5.25V
2.0
-
V
Logical Zero Input Voltage
VIL
VCC = 4.75V
-
0.8
V
Clock Input High
VIHC
VCC = 5.25V
3.0
-
V
Clock Input Low
VIHL
VCC = 4.75V
-
0.8
V
Output High Voltage
VOH
IOH = -400µA, VCC = 4.75V
2.6
-
V
Output Low Voltage
VOL
IOL = +2.0mA, VCC = 4.75V
-
0.4
V
Input Leakage Current
IL
VIN = VCC or GND, VCC = 5.25V
-10
+10
µA
Output Leakage Current
IO
VIN = VCC or GND, VCC = 5.25V
-10
+10
µA
Standby Power Supply Current
ICCSB
VCC = 5.25V, Outputs Not Loaded
-
500
µA
Operating Power Supply Current
(Commercial)
ICCOP
f = 52MHz, VIN = VCC or GND,
VCC = 5.25V
-
156
mA
(Note 3)
Operating Power Supply Current (Industrial)
ICCOP
f = 48MHz, VIN = VCC or GND,
VCC = 5.25V
-
144
mA
(Note 3)
Freq = 1MHz, VCC Open, All Measurements Are
Referenced To Device Ground
-
10
pF
(Note 4)
-
12
pF
(Note 4)
Input Capacitance
CIN
Output Capacitance
COUT
NOTES:
3. Power Supply current is proportional to operation frequency. Typical rating for ICCOP is 2mA/MHz.
4. Capacitance TA = 25oC, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
3-19
HSP50215
AC Electrical Specifications
VCC = 5 ±5%, TA = 0oC to 70oC, Commercial; TA = -40oC to 85oC, Industrial (Note 5)
52MHz
PARAMETER
SYMBOL
MIN
MAX
UNITS
REFCLK Clock Period (Commercial)
t CP
19
-
ns
REFCLK Clock Period (Industrial)
t CP
21
-
ns
REFCLK High
t CH
7
-
ns
REFCLK Low
t CL
7
-
ns
Setup Time CAS(15:0), SYNCIN to REFCLK
t DS
6
-
ns
Hold Time CAS(15:0), SYNCIN to REFCLK
t DH
1
-
ns
Setup Time A(9:0) to Rising Edges of WR or CE Low
t AS
12
-
ns
Setup Time C(15:0) to Rising Edges of WR or CE Low
t CS
6
-
ns
Hold Time A(9:0) to Rising Edges of WR or CE Low
t AH
2
-
ns
Hold Time C(15:0) to Rising Edges of WR or CE Low
t CH
2
-
ns
Read Address Low to Data Valid
t ADO
-
16
ns
Rising Edge of WR or CE to FIFORDY High (FIFO Write)
t WF
12
-
ns
REFCLK to OUT(15:0)
t DO
-
8
ns
REFCLK to SYNCOUT, SAMPCLK and FIFORDY Valid
t DOC
-
12
ns
WR High
t WRH
7
-
ns
WR Low
t WRL
7
-
ns
RD Low
t RL
9
-
ns
RD LOW and CE LOW to Data Valid
t RDO
-
8
ns
RD HIGH and CE HIGH to Output Disable
t ROD
-
10
(Note 6)
ns
Output Enable Time
t OE
-
7
ns
Output Disable Time
t OD
-
8
(Note 6)
ns
Output Rise, Fall Time
t RF
-
5
(Note 6)
ns
NOTES:
5. AC tests performed with CL = 40pF, IOL = 2mA, and IOH = -400µA. Input reference level for CLK is 2.0V, all other inputs 1.5V.
Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
S1
DUT
CL †
SWITCH S1 OPEN FOR ICCSB AND ICCOP
† TEST HEAD CAPACITANCE
3-20
IOH
±
1.5V
EQUIVALENT CIRCUIT
IOL
HSP50215
Waveforms
t WRL
t WRH
WR OR-ED CE
t AS
t AH
A9-0
t WF
FIFORDY
t RF
t RF
2.0V
0.8V
C15-0
t CS
t CH
FIGURE 17. TIMING RELATIVE TO WR OR WITH CE
FIGURE 18. OUTPUT RISE AND FALL TIMES
OE
t CP
t CL
1.5V
1.5V
t CH
t OE
REFCLK
t OD
1.7V
t DS
t DH
OUT(15:0)
1.3V
CAS(15:0),
SYNCIN
FIGURE 20. OUTPUT ENABLE/DISABLE
SAMPCLK, SYNCOUT,
FIFORDY
t RL
t DOC
RD OR’ed CE
OUT(15:0)
t DO
A9-0
NOTE: CASZ, OFM, OE are signals that must remain constant with
respect to REFCLK until the part is reset. In the write mode,
either CE or WR must be clocked while the other is tied low.
In read mode, either CE or RD must be clocked while the other is tied low. Never tie all three interface signals (CE, RD and
WR) low at the same time.
FIGURE 19. TIMING RELATIVE TO REFCLK
C15-0
t RDO
t ROD
t ADO
FIGURE 21. TIMING RELATIVE TO READ OR TO CE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
3-21
Similar pages