5 4 3 2 1 D D ISL5216EVAL Schematics Table Of Contents Page 1 ISL5216EVAL Schematics - Title Page Page 2 ISL5216EVAL Schematics - ISL5216 Page 3 ISL5216EVAL Schematics - Data Input Page 4 ISL5216EVAL Schematics - Data Output Page 5 ISL5216EVAL Schematics - Clock Distribution Page 6 ISL5216EVAL Schematics - Programable Logic Page 7 ISL5216EVAL Schematics - Control Interface Page 8 ISL5216EVAL Schematics - SRAM Page 9 ISL5216EVAL Schematics - Power Highest Referenced Designators: C109 J14 JP12 L1 R61 TP11 T9 U17 Y1 C B C B Unused Designators: A A Intersil Corporation, 2000 Title ISL5216EVAL Schematics - Title Page Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 1 of 9 5 4 3 2 1 D D Vqpdc_3 B5 B7 F2 G13 J13 K2 N6 N8 B9 E13 H2 N10 Vqpdc_2 QpdcA[15:0] QpdcEnib D1 D3 E1 E3 F1 F3 G1 H3 J1 J3 K1 K3 L1 L2 M1 M2 L3 QpdcEnic N1 N2 P1 M3 P2 N3 P3 N4 P4 M4 P5 M5 P6 M6 P7 M7 P8 QpdcEnid M8 P9 M9 P10 M10 P11 N11 P12 N12 P13 N13 P14 M12 N14 M13 M14 M11 QpdcB15 QpdcB14 QpdcB13 QpdcB12 QpdcB11 QpdcB10 QpdcB9 QpdcB8 QpdcB7 QpdcB6 QpdcB5 QpdcB4 QpdcB3 QpdcB2 QpdcB1 QpdcB0 QpdcB[15:0] QpdcC15 QpdcC14 QpdcC13 QpdcC12 QpdcC11 QpdcC10 QpdcC9 QpdcC8 QpdcC7 QpdcC6 QpdcC5 QpdcC4 QpdcC3 QpdcC2 QpdcC1 QpdcC0 QpdcC[15:0] B QpdcD15 QpdcD14 QpdcD13 QpdcD12 QpdcD11 QpdcD10 QpdcD9 QpdcD8 QpdcD7 QpdcD6 QpdcD5 QpdcD4 QpdcD3 QpdcD2 QpdcD1 QpdcD0 QpdcD[15:0] TP3 1 3 5 7 9 11 13 15 17 19 QpdcOe QpdcP14 QpdcP12 QpdcP10 QpdcP8 QpdcP6 QpdcP4 QpdcP2 QpdcP0 2 4 6 8 10 12 14 16 18 20 PreHostClk QpdcP15 QpdcP13 QpdcP11 QpdcP9 QpdcP7 QpdcP5 QpdcP3 QpdcP1 QpdcP15 QpdcP14 QpdcP13 QpdcP12 QpdcP11 QpdcP10 QpdcP9 QpdcP8 QpdcP7 QpdcP6 QpdcP5 QpdcP4 QpdcP3 QpdcP2 QpdcP1 QpdcP0 C13 C14 D13 D14 E12 E14 F12 F14 G12 G14 H12 H14 J12 J14 K12 K14 QpdcP[15:0] TP4 A 1 3 5 7 9 11 13 15 17 19 DipSw1 DipSw3 DipSw5 FpgaUnused5 QpdcIntrpt QpdcWr QpdcAdd2 QpdcAdd0 2 4 6 8 10 12 14 16 18 20 DipSw0 DipSw2 DipSw4 QpdcReset FpgaUnused4 QpdcOe QpdcCe QpdcAdd1 QpdcAdd0 QpdcAdd1 QpdcAdd2 B13 B14 D11 QpdcWr QpdcOe QpdcCe QpdcReset L14 L13 L12 D12 RxClk2 H1 Vcc1 Vcc1 Vcc1 Vcc1 Vcc1 Vcc1 Vcc1 Vcc1 Vcc2 Vcc2 Vcc2 Vcc2 QpdcEnia A_15 A_14 A_13 A_12 A_11 A_10 A_09 A_08 A_07 A_06 A_05 A_04 A_03 A_02 A_01 A_00 ENIAb SD1A SD2A SYNCA SD1B SD2B SYNCB SD1C SD2C SYNCC B_15 B_14 B_13 B_12 B_11 B_10 B_09 B_08 B_07 B_06 B_05 B_04 B_03 B_02 B_01 B_00 ENIBb SD1D SD2D SYNCD SERCLK INTRPT SYNCO SYNCI SYNCIn_A SYNCIn_B SYNCIn_C SYNCIn_D Am1 Bm1 Cm1 Dm1 C_15 C_14 C_13 C_12 C_11 C_10 C_09 C_08 C_07 C_06 C_05 C_04 C_03 C_02 C_01 C_00 ENICb NC NC NC NC NC NC NC NC TDI TRSTb TCLK TMS TDO A7 C7 A8 QpdcSd1a QpdcSd2a C8 C9 A9 QpdcSynca QpdcSd1b QpdcSd2b QpdcSyncb B11 C10 A11 QpdcSd1c QpdcSd2c QpdcSyncc B12 C11 A12 QpdcSd1d QpdcSd2d QpdcSyncd A10 C12 QpdcIntrpt A14 A13 H11 G11 F11 D9 QpdcSynco QpdcSynci QpdcSyncI_A QpdcSyncI_B QpdcSyncI_C QpdcSyncI_D D4 K4 L7 L11 Am1 Bm1 Cm1 Dm1 C R53 24 QpdcSclk1 R6 24 QpdcSclk2 R54 24 QpdcSclk3 D5 E4 L4 L5 L10 K11 D10 E11 L6 H4 G4 F4 D7 Qpdc_tdi Qpdc_trstb Qpdc_tck Qpdc_tms Qpdc_tdo B D_15 D_14 D_13 D_12 D_11 D_10 D_09 D_08 D_07 D_06 D_05 D_04 D_03 D_02 D_01 D_00 ENIDb P_15 P_14 P_13 P_12 P_11 P_10 P_09 P_08 P_07 P_06 P_05 P_04 P_03 P_02 P_01 P_00 ADD_0 ADD_1 ADD_2 WRb OEb CEb RESETb GND GND GND GND GND GND GND GND GND GND GND GND GND C A6 C6 A5 C5 A4 B4 A3 B3 A2 B2 A1 C3 B1 C2 C1 D2 C4 CLOCK Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal L9 L8 K10 K9 K8 K7 K6 K5 J11 J10 J9 J8 J7 J6 J5 J4 H10 H9 H8 H7 H6 H5 G10 G9 G8 G7 G6 G5 F10 F9 F8 F7 F6 F5 E10 E9 E8 E7 E6 E5 D8 D6 A B6 B8 B10 E2 F13 G2 G3 H13 J2 K13 N5 N7 N9 QpdcA15 QpdcA14 QpdcA13 QpdcA12 QpdcA11 QpdcA10 QpdcA9 QpdcA8 QpdcA7 QpdcA6 QpdcA5 QpdcA4 QpdcA3 QpdcA2 QpdcA1 QpdcA0 U1 ISL5216 Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - ISL5216 Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 2 of 9 5 4 3 2 1 D D QpdcC10 QpdcC11 QpdcC12 QpdcC13 QpdcC14 QpdcC15 QpdcC[15:0] RxC10 RxC11 RxC12 RxC13 RxC7 RxC6 RxC5 RxC4 RxC3 RxC2 RxC1 RxC0 Am1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 100 1 2 3 4 5 6 7 8 100 JP4 R5 RxC6 RxC7 RxC8 RxC9 AMP556591 RxC14 RxC15 RxClkA RxClkC1 RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 NC LVDS GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS Vcc LVDS GND RxIN2RxIN2+ RxCLK INRxCLK IN+ LVDS GND PLL GND PLL Vcc PLL GND PWRDWN RxCLK OUT RxOUT0 Vcc RxOUT16 RxOUT15 RxOUT14 GND RxOUT13 Vcc RxOUT12 RxOUT11 RxOUT10 GND RxOUT9 Vcc RxOUT8 RxOUT7 RxOUT6 GND RxOUT5 RxOUT4 RxOUT3 Vcc RxOUT2 RxOUT1 GND V33 QpdcEnia 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 QpdcA15 QpdcA14 QpdcA13 TP1 QpdcA12 QpdcA11 QpdcA10 QpdcA9 QpdcA8 QpdcA7 QpdcA6 QpdcA5 QpdcA4 QpdcA3 QpdcA1 QpdcA3 QpdcA5 QpdcA7 QpdcA9 QpdcA11 QpdcA13 QpdcA15 QpdcA2 QpdcA1 C 2 1 C U3 DS90CR218A V33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 100 RxC4 RxC5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 R4 RxC2 RxC3 RxC15 RxC14 RxC13 RxC12 RxC11 RxC10 RxC9 RxC8 RxClkC 100 QpdcC6 QpdcC7 QpdcC8 QpdcC9 RxC0 RxC1 R3 QpdcC4 QpdcC5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CLK1 D1_0 D1_1 GND D1_2 D1_3 Vcc D1_4 D1_5 GND D1_6 D1_7 D2_0 D2_1 GND D2_2 D2_3 Vcc D2_4 D2_5 GND D2_6 D2_7 CLK2 R2 QpdcC2 QpdcC3 OE1 Q1_0 Q1_1 GND Q1_2 Q1_3 Vcc Q1_4 Q1_5 GND Q1_6 Q1_7 Q2_0 Q2_1 GND Q2_2 Q2_3 Vcc Q2_4 Q2_5 GND Q2_6 Q2_7 OE2 T1 Z1D13Y680M510KAT2A 19 17 15 13 11 9 7 5 3 1 V33 J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 QpdcC0 QpdcC1 1 2 3 20 18 16 14 12 10 8 6 4 2 V33 JP2 RxC[15:0] U2 74LPT16374 QpdcA14 QpdcA12 QpdcA10 QpdcA8 QpdcA6 QpdcA4 QpdcA2 QpdcA0 T2 Z1D13Y680M510KAT2A QpdcA0 QpdcEnic 3 2 1 QpdcA[15:0] JP9 JP3 QpdcD3 QpdcD2 QpdcD1 QpdcD0 QpdcD[15:0] RxD5 RxD4 RxD3 RxD2 RxD1 RxD0 RxClkC1 1 2 3 4 5 6 7 8 AMP556591 RxD[15:0] 100 RxD7 RxD6 RxD5 RxD4 RxD3 RxD2 RxD1 RxD0 JP5 R10 RxD9 RxD8 RxD7 RxD6 Bm1 100 RxD11 RxD10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 R9 QpdcD5 QpdcD4 RxD13 RxD12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 RxD15 RxD14 RxD13 RxD12 RxD11 RxD10 RxD9 RxD8 100 QpdcD9 QpdcD8 QpdcD7 QpdcD6 RxD15 RxD14 100 QpdcD11 QpdcD10 CLK1 D1_0 D1_1 GND D1_2 D1_3 Vcc D1_4 D1_5 GND D1_6 D1_7 D2_0 D2_1 GND D2_2 D2_3 Vcc D2_4 D2_5 GND D2_6 D2_7 CLK2 R8 QpdcD13 QpdcD12 B OE1 Q1_0 Q1_1 GND Q1_2 Q1_3 Vcc Q1_4 Q1_5 GND Q1_6 Q1_7 Q2_0 Q2_1 GND Q2_2 Q2_3 Vcc Q2_4 Q2_5 GND Q2_6 Q2_7 OE2 U5 DS90CR218A V33 R7 QpdcD15 QpdcD14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 NC LVDS GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS Vcc LVDS GND RxIN2RxIN2+ RxCLK INRxCLK IN+ LVDS GND PLL GND PLL Vcc PLL GND PWRDWN RxCLK OUT RxOUT0 Vcc RxOUT16 RxOUT15 RxOUT14 GND RxOUT13 Vcc RxOUT12 RxOUT11 RxOUT10 GND RxOUT9 Vcc RxOUT8 RxOUT7 RxOUT6 GND RxOUT5 RxOUT4 RxOUT3 Vcc RxOUT2 RxOUT1 GND V33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 QpdcEnib 1 2 3 RxClkA4 QpdcB15 QpdcB14 19 17 15 13 11 9 7 5 3 1 V33 J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 QpdcB13 B TP2 20 18 16 14 12 10 8 6 4 2 U4 74LPT16374 V33 QpdcB14 QpdcB12 QpdcB10 QpdcB8 QpdcB6 QpdcB4 QpdcB2 QpdcB0 QpdcB12 QpdcB11 QpdcB10 QpdcB9 QpdcB8 QpdcB7 QpdcB6 QpdcB5 QpdcB4 QpdcB3 QpdcB1 QpdcB3 QpdcB5 QpdcB7 QpdcB9 QpdcB11 QpdcB13 QpdcB15 QpdcB2 QpdcB1 QpdcB0 QpdcB[15:0] Test point for extra floating point bits for C & D (A & B are connected to the LVDS connectors) JP12 Cm1 Dm1 1 3 QpdcEnid 2 4 A 3 2 1 A JP10 Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - Data Input Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 3 of 9 5 4 3 2 1 D D TP6 C DacQ14 DacQ12 DacQ10 DacQ8 DacQ6 DacQ4 DacQ2 DacQ0 C 2 4 6 8 10 12 14 16 18 20 DacQ1 DacQ3 DacQ5 DacQ7 DacQ9 DacQ11 DacQ13 DacQ15 1 3 5 7 9 11 13 15 17 19 DacClk2 DacQ[15:0] DacQ8 DacQ9 DacQ10 DacQ11 DacQ12 DacQ13 DacQ14 DacQ15 QpdcSyncd C95 C3 .1 uF .1 uF 2 J7 5 1 161-3501 C5 .1 uF 51 .1 uF 1.87K C7 R15 51 R14 R58 51 1 2 3 4 5 6 7 8 9 10 11 12 QpdcSd1d QpdcSd2d C4 R13 QpdcSyncc 24 23 22 21 20 19 18 17 16 15 14 13 R12 QpdcSclk2 QpdcSyncb QpdcSd1c QpdcSd2c Avdd QCMP1 QOUTA QOUTB FSADJ AGND REFLO REFIO IOUTB IOUTA ICMP1 Avdd 51 QpdcSd1b QpdcSd2b OD03 OD02 OD01 (LSB) OD00 NC NC (MSB) ID11 ID10 ID09 ID08 ID07 ID06 C6 .1 uF 37 38 39 40 41 42 43 44 45 46 47 48 QpdcSynca QD04 QD05 QD06 QD07 QD08 QD09 QD10 (MSB) QD11 CLK DGND AGND QCMP2 36 35 34 33 32 31 30 29 28 27 26 25 C94 .1 uF U7 HI5828 ID05 ID04 ID03 ID02 ID01 ID00 (LSB) NC NC SLEEP Dvdd AGND ICMP2 QpdcSd1a QpdcSd2a 500 J8 1 2 3 R59 500 .1 uF B T5 DNI DacI9 DacI8 DacI7 DacI6 DacI5 DacI4 DacI3 DacI2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2 B OE4 A1_0 A1_1 GND A1_2 A1_3 Vcc A2_0 A2_1 GND A2_2 A2_3 A3_0 A3_1 GND A3_2 A3_3 Vcc A4_0 A4_1 GND A4_2 A4_3 OE3 DacI15 DacI14 DacI13 DacI12 DacI11 DacI10 R52 0 OE1 Y1_0 Y1_1 GND Y1_2 Y1_3 Vcc Y2_0 Y2_1 GND Y2_2 Y2_3 Y3_0 Y3_1 GND Y3_2 Y3_3 Vcc Y4_0 Y4_1 GND Y4_2 Y4_3 OE2 1 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Avdd V33 R11 DacQ2 DacQ3 DacQ4 DacQ5 DacQ6 DacQ7 U6 74LPT16244 V33 DacClk1 V33 TP5 1 3 5 7 9 11 13 15 17 19 DacI15 DacI13 DacI11 DacI9 DacI7 DacI5 DacI3 DacI1 DacI0 DacI2 DacI4 DacI6 DacI8 DacI10 DacI12 DacI14 DacI[15:0] 2 4 6 8 10 12 14 16 18 20 A A Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - Data Output Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 4 of 9 5 4 3 2 1 D 2 1 D C T9 DNI C JP1 RxClkC1 V33 1 2 3 4 5 6 7 8 SysClk V33 1 2 3 4 5 6 7 8 RxClkA 10K 10K R44 RxClkAMuxS2 R43 RxClkCMuxS2 10K REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 R42 RxClkCMuxS1 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 U9 CY2309 REF CLKOUT CLKA1 CLKA4 CLKA2 CLKA3 VDD VDD GND GND CLKB1 CLKB4 CLKB2 CLKB3 S2 S1 V33 16 15 14 13 12 11 10 9 C9 DNI RxClkA4 RxClkAMuxS1 10K 16 15 14 13 12 11 10 9 1 2 3 R45 V33 C8 DNI RxClkC U8 CY2309 TP7 1 2 RxClk2 1 2 1 2 T4 Z1D13Y680M510KAT2A 2 1 RxClk4 T6 Z1D13Y680M510KAT2A Note: Terminators are to be placed at the end of each clock net as close to the ending compenent as reasonable. B B V33 Y1 SG636 1 2 OE GND OUT Vcc 3 SysClk 4 A A Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - Clock Distribution Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 5 of 9 5 4 3 2 1 V33 R60 10k QpdcP0 QpdcP2 QpdcP1 QpdcWr QpdcOe QpdcCe QpdcSynco QpdcReset RxD[15:0] D RxD15 RxD14 RxD13 RxD12 RxD11 RxD10 RxD9 RxD8 D QpdcP8 QpdcP7 QpdcP6 QpdcP5 QpdcP4 QpdcP3 QpdcAdd0 QpdcAdd1 QpdcAdd2 QpdcIntrpt QpdcSyncd QpdcSd2d QpdcSd1d QpdcSyncc QpdcSd2c QpdcSd1c QpdcSyncb QpdcSd2b QpdcSd1b QpdcSynca QpdcSd2a QpdcSd1a QpdcP14 QpdcP13 QpdcP12 QpdcP11 QpdcP10 QpdcP9 QpdcP15 QpdcP[15:0] SysClk QpdcSclk1 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 2 1 CpldTdi T3 DNI PcIocs16 PcReset DipSw6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SramData0 SramData1 SramData2 SramData3 SramData4 SramData5 SramData6 SramData7 SramData8 FB2_14 NC NC FB2_15 FB2_16 FB2_17 FB1_17 GND NC FB1_18 FB1_16 Vccint FB1_15 FB1_14 NC FB1_13 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 U12 XC9536XL-VQ64 V33 PcAdd9 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DipSw5 DipSw4 PcIrq10 JtagTdo PcAdd8 PcAdd7 DipSw3 DipSw2 NC NC TCK TMS TDI FB1_12 NC FB1_11 FB1_10 NC FB1_9 GND FB1_8 FB1_6 NC FB1_7 (GCK3) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PcIor PcIrq5 JtagTck JtagTms CpldTdi FpgaCclk SramData9 SramData10 FpgaDone PpAckDataReq PcIow PpIeee1284Active PpDataAvail PpXflag PcAen PpInit SramData[15:0] SramAdd[19:0] SramAdd9 SramAdd10 SramAdd11 SramAdd12 SramAdd13 PcAdd4 PcAdd3 PpPtrBusy PpPtrClk PpHostClk SramAdd14 SramAdd15 SramAdd16 SramAdd17 SramAdd18 SramAdd19 0 DNI SramCe1Not SramCe2 SramCe2Not SramRw SramCenNot GND IO_002 (GCK1) IO_003 IO_004 IO_005 IO_006 (TDI) IO_007 (TCK) IO_008 IO_009 IO_010 IO_011 IO_012 IO_013 GND IO_015 IO_016 IO_017 (TMS) IO_018 Vcc IO_020 IO_021 GND IO_023 IO_024 IO_025 IO_026 IO_027 IO_028 GND Vcc IO_031 IO_032 IO_033 IO_034 IO_035 IO_036 GND IO_038 IO_039 Vcc IO_041 IO_042 IO_043 IO_044 GND IO_046 IO_047 IO_048 IO_049 IO_050 IO_051 IO_052 IO_053 IO_054 IO_055 IO_056 IO_057 (GCK2) M1 GND M0 V33 Vcc CCLK (GCK6/DOUT) IO_178 (D0/DIN) IO_177 IO_176 IO_175 IO_174 (D1) IO_173 IO_172 IO_171 IO_170 IO_169 IO_168 IO_167 GND IO_165 IO_164 IO_163 IO_162 Vcc IO_160 (D2) IO_159 GND IO_157 IO_156 IO_155 IO_154 IO_153 (D3) IO_152 GND Vcc IO_149 (D4) IO_148 IO_147 IO_146 IO_145 IO_144 GND IO_142 (D5) IO_141 Vcc IO_139 IO_138 IO_137 IO_136 GND IO_134 IO_133 IO_132 IO_131 IO_130 (D6) IO_129 IO_128 IO_127 IO_126 IO_125 (GCK5) IO_124 (D7) IO_123 PROGRAM Vcc 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 FpgaCclk RxClk4 RxD7 RxD6 RxD5 RxD4 RxD3 RxD2 RxD1 RxD0 C QpdcSync1 QpdcSync2 QpdcSync3 RxClk4 HostData0 HostData1 HostData8 HostData2 HostData9 HostData10 HostData11 HostData12 HostData13 HostData3 HostData14 HostData4 HostData15 PpHostClk PpPtrClk PpPtrBusy PpAckDataReq HostData5 PpDataAvail PpInit PpIeee1284Active PpHostBusy PpXflag Pp1284Dir FpgaUnused5 FpgaUnused4 B HostData6 SramP2 SramP1 HostData7 FpgaProgram HostData[15:0] 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 R16 PcAdd[9:3] R18 DNI V33 R17 PcAdd5 HostData3 HostData2 HostData1 HostData0 PcAdd6 HostData4 HostData[15:0] SramData13 SramData14 SramData15 SramAdd0 SramAdd1 SramAdd2 SramAdd3 SramAdd4 SramAdd5 SramAdd6 SramAdd7 SramAdd8 PpHostBusy SysClk B JtagTms SramData11 SramData12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DipSw1 DipSw0 HostData7 HostData6 HostData5 FB2_18 FB2_13 NC NC TDO GND Vccio FB2_12 FB2_11 NC NC FB2_10 FB2_9 FB2_8 FB2_7 (GSR) FB2_6 NC FB2_5 (GTS2) Vccint NC FB2_3 (GTS1) FB2_4 FB2_2 FB2_1 FB1_1 FB1_2 FB1_4 NC NC NC FB1_3 (GCK1) FB1_5 (GCK2) C JtagTdi JtagTck U11 XCS30XL Vcc (GCK8) IO_239 IO_238 IO_237 IO_236 IO_235 IO_234 IO_233 IO_232 IO_231 IO_230 IO_229 IO_228 GND IO_226 IO_225 IO_224 IO_223 Vcc IO_221 IO_220 GND IO_218 IO_217 IO_216 IO_215 IO_214 IO_213 Vcc GND IO_210 IO_209 IO_208 IO_207 IO_206 IO_205 GND IO_203 IO_202 Vcc IO_200 IO_199 IO_198 IO_197 GND NC IO_194 IO_193 IO_192 IO_191 IO_190 IO_189 IO_188 (CS1) IO_187 IO_186 IO_185 (GCK7) IO_184 IO_183 GND (TDO) O181 PcIochrdy QpdcIntrpt FpgaCsOrLdc FpgaResetOrInit FpgaRw PcSbhe FpgaProgram Vcc PWRDWN IO_063 (GCK3) IO_064 (HDC) IO_065 IO_066 IO_067 IO_068 (LDC) IO_069 IO_070 IO_071 IO_072 IO_073 IO_074 GND IO_076 IO_077 IO_078 IO_079 Vcc IO_081 IO_082 GND IO_084 IO_085 IO_086 IO_087 IO_088 IO_089 (INIT) Vcc GND IO_092 IO_093 IO_094 IO_095 IO_096 IO_097 GND IO_099 IO_100 Vcc IO_102 IO_103 IO_104 IO_105 GND IO_107 IO_108 IO_109 IO_110 IO_111 IO_112 IO_113 IO_114 IO_115 IO_116 IO_117 IO_118 (GCK4) GND DONE Pp1284Dir DipSw7 Pp1284Hd DNI DacQ7 DacQ8 DacQ9 DacQ10 DacQ11 DacQ12 DacQ13 DacQ14 DacQ15 DacQ3 DacQ4 DacQ5 DacQ6 DacQ1 DacQ2 DacI11 DacI12 DacI13 DacI14 DacI15 DacQ0 DacI6 DacI7 DacI8 DacI9 DacI10 DacI4 DacI5 DacClk1 DacClk2 DacI0 DacI1 DacI2 DacI3 FpgaRw FpgaCsOrLdc RxClkAMuxS2 RxClkAMuxS1 RxClkCMuxS2 RxClkCMuxS1 R21 DNI R20 R19 DNI FpgaDone SramOeNot SramAdvLd DacI[15:0] DacQ[15:0] FpgaResetOrInit A A Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - Programable Logic Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 6 of 9 5 4 3 2 1 D D J1 PreHostBusy PreDataAvail PreInit R25 R39 R40 0 0 0 PreIeee1284Active V33 JtagTck JtagTdo JtagTdi JtagTms Qpdc_tck 10K 10K R55 R56 Qpdc_tdi Qpdc_tms V33 R48 10K Qpdc_tdo U14 74LVX161284 V33 2 4 6 8 10 Pp1284Hd PpPtrClk PpPtrBusy PpAckDataReq PpXflag PpDataAvail HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6 HostData7 B HostData[15:0] PpHostClk PpHostBusy PpInit PpIeee1284Active 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C R49 10K JP11 1 3 5 7 9 J9 1 2 3 4 5 6 10K Qpdc_trstb 14 15 16 17 18 19 20 21 22 23 24 25 26 10K PreD6 PreD7 PrePtrClk PrePtrBusy PreAckDataReq PreXflag JTAG Header for ISL5216 14 15 16 17 18 19 20 21 22 23 24 25 26 R51 R26 0 R27 0 1 2 3 4 5 06 07 08 09 10 11 12 13 R50 PreD4 PreD5 C 1 2 3 4 5 06 07 08 09 10 11 12 13 PreHostClk PreD0 PreD1 PreD2 PreD3 HD A9 A10 A11 A12 A13 Vcc A1 A2 GND A3 A4 A5 A6 GND A7 A8 Vcc PLHin A14 A15 A16 A17 HLH DIR Y9 Y10 Y11 Y12 Y13 Vcable B1 B2 GND B3 B4 B5 B6 GND B7 B8 Vcable PLH C14 C15 C16 C17 HLHin V50 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Pp1284Dir PrePtrClk PrePtrBusy PreAckDataReq PreXflag PreDataAvail JP7 QpdcSync1 QpdcSync2 QpdcSync3 QpdcSynco QpdcSynci PreD0 PreD1 QpdcSyncI_A QpdcSyncI_B QpdcSyncI_C QpdcSyncI_D PreD2 PreD3 PreD4 PreD5 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 PreD6 PreD7 B PreHostClk PreHostBusy PreInit PreIeee1284Active C98 2200pF C 9 8 s h o u ld be placed between U14 and T P 3 , b a s i cally to have ground connected t o g ether with C78 A A Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - Control Interface Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 7 of 9 5 4 3 2 1 SramAdd19 SramAdd18 SramAdd8 SramAdd9 D SramAdd6 SramAdd7 D SramCe1Not SramCe2 SramCe2Not SramData12 SramData13 DNI DNI R31 R32 SramData14 SramData15 SramP2 1 0 V33 A10 NC NC Vddq Vss NC IO_P1 IO_07 IO_06 Vss Vddq IO_05 IO_04 Vss Vdd Vdd Vss IO_03 IO_02 Vddq Vss IO_01 IO_00 NC NC Vss Vddq NC NC NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE1 CE2 NC NC BW2 BW1 CE2 Vdd Vss CLK R/W CEN OE ADV/LD (A19) NC (A18) NC A8 A9 DNI V33 SramAdd10 C SramP1 SramData7 SramData6 SramData5 SramData4 SramData3 SramData2 SramData1 SramData0 DNI SramData10 SramData11 NC NC NC Vddq Vss NC NC IO_08 IO_09 Vss Vddq IO_10 IO_11 Vdd Vdd Vdd Vss IO_12 IO_13 Vddq Vss IO_14 IO_15 IO_P2 NC Vss Vddq NC NC NC U15 IDT71V65803 R33 SramData8 SramData9 SramData[15:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO A5 A4 A3 A2 A1 A0 NC NC Vss Vdd NC NC A11 A12 A13 A14 A15 A16 A17 0 R29 C 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 0 R28 V33 T7 2 QpdcSclk3 SramRw SramCenNot SramOeNot SramAdvLd SramAdd11 SramAdd12 SramAdd13 SramAdd14 SramAdd15 SramAdd16 SramAdd17 B SramAdd5 SramAdd4 SramAdd3 SramAdd2 SramAdd1 SramAdd0 B SramAdd[19:0] A A Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - SRAM Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 8 of 9 5 4 3 2 1 IN GND OUT U16 MIC29300-3.3BU D V50 1 2 1 2 1 2 10 uF C12 + C13 .01 uF R62 160 10 uF 10 uF NOTE: The supply planes of the ISL5216 are isolated to provide the means for measuring current consumption of the part. Vqpdc_2 Vqpdc_3 V33 R34 0 D2 597-3311-402 U17 MIC39300-2.5BU TP8 TP9 TP10 TP11 1 1 1 1 G r een LED IN GND OUT N O TE: When HSP50216 installed on board, use V33 plane for supply. W h en ISL5216 installed on board, use V25 plane for supply. 1 V33 1 Vqpdc_2x 1 V25 1 2 C14 + 1 0 J14 R35 .005 + C11 R61 Avdd 1 2 3 J13 Vqpdc_2x D L1 EXC-ML32A68OU V33 JP8 1 2 3 HEADER 3 1 2 3 V25 R57 .005 NOTE: This header should NOT be installed on the board. Instead, a zero Ohm resistor, or a piece of wire will go between the supply plane and Vqpdc_2, depending if ISL5216 or HSP50216 are on board. + C99 10 uF C101 + C100 .01 uF R63 160 10 uF Blue LED D1 597-3311-404 C C U8. Connect one set to Vdd pin 4 and another to Vdd pin 13. Connect the caps between the pin and the via. Ground each cap with at least one via. .1 uF .1 uF C49 .1 uF C46 C48 .1 uF C45 .1 uF .01 uF .001 uF C44 .1 uF C42 C43 .01 uF .001 uF C41 .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF C67 C68 C69 C70 C71 C72 C73 V33 .1 uF V33 C66 V33 .1 uF V33 C65 V33 .1 uF V33 .1 uF V33 C64 V33 C63 V33 .1 uF V33 C62 V33 .01 uF V33 U12. Connect one each to pins 3, 26, 37 and 55. C57 100 pF C54 U11. Connect one each to Vcc pins 19, 40, 80, 101, 140, 161, 201 and 222 V33 Avdd Avdd .01 uF .01 uF C53 V33 100 pF 100 pF C52 V33 C56 .01 uF V33 C55 100 pF V33 C51 V33 V33 C40 .01 uF .001 uF C38 U9. Connect one set to Vdd pin 4 and another to Vdd pin 13. Connect the caps between the pin and the via. Ground each cap with at least one via. C39 .1 uF .1 uF C35 C37 .1 uF C34 V33 C36 .01 uF .001 uF V33 U6. Connect one each to Vcc pins 7 and 31. C47 U5. Connect one set to pin 20, PLL Vcc; another to pin 12, LVDS Vcc and the last to pin 36, Vcc V33 C33 .1 uF C31 V33 C32 .01 uF .001 uF .1 uF C28 U4. Connect one each to Vcc pins 7 and 31. V33 C30 .01 uF .001 uF C27 .1 uF V33 C26 C25 .1 uF C24 V33 C50 V33 V33 .1 uF .01 uF C22 V33 C23 .01 uF .1 uF Vqpdc_2 C21 Vqpdc_2 C20 .01 uF .1 uF .1 uF C17 C19 .01 uF Vqpdc_2 C18 .1 uF C16 Vqpdc_2 C15 .01 uF Vqpdc_3 C109 .01 uF C107 C108 .1 uF Vqpdc_3 C106 .1 uF C105 .01 uF Vqpdc_3 C104 .1 uF .01 uF C103 C102 .1 uF Vqpdc_3 U3. Connect one set to pin 20, PLL Vcc; another to pin 12, LVDS Vcc and the last to pin 36, Vcc C29 U2. Connect one each to Vcc pins 7 and 31. U1. Place sets on each side of the part U7. Connect one to Dvdd pin 10 and one each to Avdd pin 13 and 24. B B .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF .1 uF V33 V33 V33 V33 V50 V50 Vqpdc_2 Vqpdc_3 + C89 C88 C87 C86 C85 C84 C83 C82 C81 C80 C79 C78 C77 C76 C75 C74 + + + + + 10 uF V33 + + C97 V33 10 uF V33 C96 V33 10 uF V33 C93 V33 10 uF V33 C92 V33 10 uF V33 C91 V50 Distibute evenly around Vqpdc supply plane 10 uF V50 C90 V33 Distibute evenly around V50 supply plane 10 uF V33 Distibute evenly around V33 supply plane 10 uF V33 .1 uF Y1. Connect to Vcc pin 4. .1 uF U18. Connect one each to Vdd pins 15, 41, 65 and 91. Connect one each to Vddq pins 4, 27, 54 and 77 .1 uF U14. Connect one each to Vcc pins 7 and 18 and one each to Vcable pins 31 and 42. .1 uF U13. Connect to Vcc near R37 and pin 2 A A Copyrighted by Intersil Corp, 1999 Title ISL5216EVAL Schematics - Power Size C Date: 5 4 3 2 Document Number 0 Rev 1.0 Thursday, May 03, 2001 Sheet 1 9 of 9