ESIGNS R NEW D N T O F D E D N EME COMME REPL AC D E N OT R E D N E enter at OMM upport C om/tsc S l N O REC a ic n h ec rsil.c our TData www.inte contact ERS IL orSheet T N 1-888-I HSP9501 August 2004 FN2786.5 Programmable Data Buffer Features The HSP9501 is a 10-Bit wide programmable data buffer designed for use in high speed digital systems. Two different modes of operation can be selected through the use of the MODSEL input. In the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data. In the data recirculate mode, the output data path is internally routed back to the input to provide a programmable circular buffer. • DC to 32MHz Operating Frequency The length of the buffer or amount of delay is programmed through the use of the 11-bit Length Control Input Port (LC010) and the Length Control Enable (LCEN). An 11-bit value is applied to the LC0-10 inputs, LCEN is asserted, and the next selected clock edge loads the new count value into the Length Control Register. The delay path of the HSP9501 consists of two registers with a programmable delay RAM between them, therefore, the value programmed into the Length Control Register is the desired length - 2. The range of values which can be programmed into the Length Control Register are from 0 to 1279, which in turn results in an overall range of programmable delays from 2 to 1281. • Programmable Buffer Length from 2 to 1281 Words • Supports Data Words to 10 Bits • Clock Select Logic for Positive or Negative Edge System Clocks • Data Recirculate or Delay Modes of Operation • Expandable Data Word Width or Buffer Length • Three-State Outputs • TTL Compatible Inputs/Outputs • Low Power CMOS Applications • Sample Rate Conversion • Data Time Compression/Expansion • Software Controlled Data Alignment • Programmable Serial Data Shifting Clock select logic is provided to allow the use of a positive or negative edge system clock as the CLK input to the HSP9501. The active edge of the CLK input is controlled through the use of the CLKSEL input. All synchronous timing (i.e., data setup, hold, and output delays) are relative to the clock edge selected by CLKSEL. An additional clock enable input (CLKEN) provides a means of disabling the internal clock and holding the existing contents temporarily. All outputs of the HSP9501 are three-state outputs to allow direct interfacing to system or multi-use buses. • Audio/Speech Data Processing Video/Image Processing The HSP9501 is recommended for digital video processing or any applications which require a programmable delay or circular data buffer. Ordering Information Video/Image Processing • 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples: - High Resolution Monitor Delay Line - Comb Filter Designs - Progressive Scanning Display - TV Standards Conversion - Image Processing PART NUMBER HSP9501JC-32 1 TEMP. RANGE (°C) 0 to 70 PACKAGE 44 Ld PLCC PKG. DWG. # N44.65 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1999, Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HSP9501 Pinout LCEN CLKSEL NC NC CLK EN CLK LC2 LC3 LC4 LC5 MODSEL 44 LEAD PLCC TOP VIEW 6 5 4 3 2 1 44 43 42 41 40 DO3 10 36 DI3 DO4 11 35 DI4 VCC 12 34 VCC GND 13 33 GND DO5 14 32 DI5 DO6 15 31 DI6 DO7 16 30 DI7 DO8 17 29 DI8 OE 19 DO9 18 20 21 22 23 24 25 26 27 28 NC 37 DI2 DI9 9 LC6 DO2 LC7 38 DI1 LC8 8 LC9 DO1 LC10 39 DI0 LC1 7 LC0 DO0 Block Diagram DI 0 -9 10 MODSEL REGISTER MUX 10 CLKSEL CLKEN CLK CLOCK GENERATOR REGISTER 10 11 LC0 -10 REGISTER EN LCEN 11 10 PROGRAMMABLE DELAY RAM 0-1279 DELAYS 10 REGISTER 10 OE 10 DO0-9 2 HSP9501 Pin Descriptions NAME PIN NUMBER VCC 12, 34 The +5V power supply pin. A 0.1F capacitor between the VCC and GND pin is recommended. GND 13, 33 The device ground. CLK 1 I Input Clock. This clock signal is used to control the data movement through the programmable buffer. It is also the signal which latches the input data, length control word and mode select. Input setup and hold times with respect to the clock must be met for proper operation. DIO-9 27, 29-32, 35-39 I Data Inputs. This 10-bit input port is used to provide the input data. When MODSEL is low, data on the DI0-9 inputs is latched on the clock edge selected by CLKSEL. DO0-9 7-11, 14-18 O Data Outputs. This 10-bit port provides the output data from the Internal Delay Registers. Data latched into the DI0-9 inputs will appear at the DO0 9 outputs on the Nth clock cycle, where N is the total delay programmed. LC0-10 20-26, 41-44 I Length Control Inputs. These inputs are used to specify the number of clock cycles of delay between the DI0-9 inputs and the DO0-9 outputs. An integer value between 0 and 1279 is placed on the LC0-10 inputs, and the total delay length (N) programmed is the LC0-10 value plus 2. In order to properly load an active length control word, the value must be presented to the LC0-10 inputs and LCEN must be asserted during an active clock edge selected by CLKSEL. LCEN 6 I Length Control Enable. LCEN is used in conjunction with LC0-10 and CLK to load a new length control word. An 11-bit value is loaded on the LC0-10 inputs, LCEN is asserted, and the next selected clock edge will load the new count value. Since this operation is synchronous, LCEN must meet the specified setup/hold times with respect to CLK for proper operation. OE 19 I Output Enable. This input controls the state of the DO0-9 output port. A low on this control line enables the port for output. When OE is high, the output drivers are in the high impedance state. Internal latching or transfer of data is not affected by this input. MODSEL 40 I Mode Select. This input is used to control the mode of operation of the HSP9501. A low on MODSEL causes the device to latch new data at the DI0-9 inputs on every clock cycle, and operate as a programmable pipeline register. When MODSEL is high, the HSP9501 is in the recirculate mode, and will operate as a programmable length circular buffer. This control signal may be used in a synchronous fashion during device operation, however, care must be taken to ensure the required setup/hold times with respect to CLK are met. CLKSEL 5 I Clock Select Control. This input is used to determine which edge of the CLK signal is used for controlling all internal events. A low on CLKSEL selects the negative going edge, therefore, all setup, hold, and output delay times are with respect to the negative edge of CLK. When CLKSEL is high, the positive going edge is selected and all synchronous timing is with respect to the positive edge of the CLK signal. CLKEN 2 I Clock Enable. This control signal can be used to enable or disable the CLK input. When low, the CLK input is enabled and will operate in a normal fashion. A high on CLKEN will disable the CLK input and will “hold'' all internal operations and data. This control signal may also be used in a synchronous fashion, however, setup and hold requirements with respect to CLK must be met for proper device operation. This signal takes effect on the clock following the one that latches it in. 3 TYPE DESCRIPTION HSP9501 All synchronous timing (i.e., setup, hold and output propagation delay times are relative to the CLK edge selected by CLKSEL. Functional timing waveforms for each state of CLKSEL are provided (refer to Timing Waveforms for details). Functional Description The HSP9501 is a 10-bit wide programmable length data buffer. The length of delay is programmable from 2 to 1281 delays in single delay increments. Data into the delay line may be selected from the data input bus (DI0-9) or as recirculated output, depending on the state of the mode select (MODSEL) control input. Delay Path Control The HSP9501 buffer length is programmable from 2 to 1281 data words in one word increments. The minimum number of delays which can be programmed is two, consisting of the input and Output Buffer Registers only. Mode Select The MODSEL control pin selects the source of the data moving into the delay line. When MODSEL is low, the data input bus (DI0-9) is the source of the data. When MODSEL is high, the output of the HSP9501 is routed back to the input to form a circular buffer. The length control inputs (LC0-10) are used to set the length of the programmable delay ram which can vary in length from 0 to 1279. The total length of the HSP9501 data buffer will then be equal to the programmed value on LC0-10 plus 2. The programmed delay is established by the 11-bit integer value of the LC0-10 inputs with LC-10 as the MSB and LC0 as the LSB. The MODSEL control line is latched at the input by the CLK signal. The edge which latches this control signal is determined by the CLKSEL control line. In either case, the MODSEL line is latched on one edge of the CLK signal with the following edge moving data into and through the HSP9501. Refer to the functional timing waveforms for specific timing references. For example, LC10 9 8 7 6 5 4 3 2 1 LC0 0 0 0 0 1 0 0 0 0 0 1 Clock Select Logic programs a length value of 26 + 20 = 65. The total length of the delay will be 65 + 2 or 67 delays. The clock select logic is provided to allow the use of positive or negative edge system clocks. The active edge of the CLK input to the HSP9501 is controlled through the use of the CLKSEL input. Table 1 indicates several programming values. The decimal value placed on LC0-10 must not exceed 1279. Controlled operation with larger values is not guaranteed. When CLKSEL is low, the negative going edge of CLK is used to control all internal operations. A high on CLKSEL selects the positive going edge of CLK. Values on LC0-10 are latched on the CLK edge selected by the CLKSEL control line, when LCEN is active. LC0-10 and LCEN must meet the specified setup and hold times relative to the selected CLK edge for proper device operation. TABLE 1. LENGTH CONTROL PROGRAMMING EXAMPLES LC10 210 LC9 29 LS8 28 LC7 27 LC6 26 LC5 25 LC4 24 LC3 23 LC2 22 LC1 21 LC0 20 PROGRAMMED LENGTH TOTAL LENGTH N 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 1 1 0 1 1 0 118 120 0 1 1 0 0 1 0 1 0 0 0 808 810 1 0 0 0 0 0 1 1 0 0 1 1049 1051 1 0 0 1 1 1 1 1 1 1 1 1279 1281 4 HSP9501 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input, Output or Voltage Applied . . . . . . . . GND -0.5V to VCC +0.5V Thermal Resistance (Typical, Note 1) JA (°C/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (PLCC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to 70°C Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to 5.25V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER VCC = 5.0V +5%, TA = 0°C to 70°C, Commercial SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V 2.4 - V - 0.4 V Output HIGH Voltage VOH IOH = -4mA VCC = 4.75V Output LOW Voltage VOL IOL = +4.0mA VCC = 4.75V Input Leakage Current II VIN = GND or VCC VCC = 5.25V -10 10 A Output Leakage Current IO VOUT = GND or VCC = 5.25V -10 10 A Standby Current ICCSB VIN = VCC or GND, VCC = 5.25V, Note 3 - 500 A Operating Power Supply Current ICCOP f = 25MHz, VIN = VCC or GND VCC = 5.25V, Notes 2, 3 - 125 mA FREQ = 1MHz, VCC = Open, All measurements are referenced to device GND - 10 pF - 10 pF Input Capacitance CIN Output Capacitance CO AC Electrical Specifications VCC = 5.0V 5%, TA = 0°C to +70°C, Commercial, (Note 5) -32 PARAMETER -25 SYMBOL MIN MAX MIN MAX UNITS NOTES t CP 31 - 40 - ns - Clock Pulse Width High t PWH 12 - 15 - ns - Clock Pulse Width Low t PWL 12 - - 15 ns - Data Input Setup Time t DS 10 - 12 - ns - Data Input Hold Time t DH 2 - 2 - ns - Output Enable Time t ENA - 20 - 25 ns - Output Disable Time t DIS - 24 - 25 ns Note 4 CLKEN to Clock Setup t ES 10 - 12 - ns - CLKEN to Clock Hold t EH 2 - 2 - ns - LC0-10 Setup Time t LS 10 - 13 - ns - LC0-10 Hold Time t LH 2 - 2 - ns - LCEN to Clock Setup t LES 10 - 13 - ns - Clock Period 5 HSP9501 AC Electrical Specifications VCC = 5.0V 5%, TA = 0°C to +70°C, Commercial, (Note 5) (Continued) -32 PARAMETER -25 SYMBOL MIN MAX MIN MAX UNITS NOTES LCEN to Clock Hold t LEH 2 - 2 - ns - MODSEL Setup Time t MS 10 - 13 - ns - MODSEL Hold Time t MH 2 - 2 - ns - Clock to Data Out TOUT - 16 - 22 ns - Output Hold from Clock TOH 4 - 4 - ns - Rise, Fall Time TRF - 6 - 6 ns Note 4 NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 5mA/MHz. 3. Output load per test load circuit with switch open and CL = 40pF. 4. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 5. AC Testing is performed as follows: Input levels: 0V and 3.0V, timing reference levels = 1.5V, input rise and fall times driven at 1ns/V, output load CL = 40pF. Test Load Circuit S1 DUT CL (NOTE) SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH 1.5V IOL EQUIVALENT CIRCUIT NOTE: Includes stray and jig capacitance. Timing Waveforms tCP CLK MODSEL tPWH tMS tPWL tDH tDS DI 0 -9 tMH OE tOUT tDIS 1.7 DO 0 -9 tOH tENA 1.3 FIGURE 1. FUNCTIONAL TIMING (CLKSEL = LOW) 6 HSP9501 Timing Waveforms (Continued) CLK tES TEH tES CLKEN INTERNAL CLOCK FIGURE 2. CLEN TIMING (CLKSEL = LOW) CLK tLES 2.0V tLEH 2.0V 0.8V 0.8V tRF LCEN tRF tLS tLH LC0 -10 FIGURE 3. OUTPUT RISE AND FALL TIMES FIGURE 4. LENGTH CONTROL TIMING (CLKSEL = LOW) tCP CLK tMS tPWL MODSEL tMH tPWH tDS tDH DI 0 -9 OE tOUT DO 0 -9 tOH tDIS tENA 1.7 1.3 FIGURE 5. FUNCTIONAL TIMING (CLKSEL = HIGH) 7 HSP9501 Timing Waveforms (Continued) CLK tES tES tEH CLKEN INTERNAL CLOCK FIGURE 6. CLKEN TIMING (CLKSEL = HIGH) CLK tLES tLEH LCEN tLS tLH LC 0 -10 FIGURE 7. LENGTH CONTROL TIMING (CLKSEL = HIGH) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8